Add files via upload
diff --git a/verilog/rtl/a.out b/verilog/rtl/a.out
new file mode 100644
index 0000000..fc4722f
--- /dev/null
+++ b/verilog/rtl/a.out
@@ -0,0 +1,3884 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x55ab20ccb6b0 .scope module, "fulladd" "fulladd" 2 226;
+ .timescale 0 0;
+ .port_info 0 /INPUT 3 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e890a0 .functor XOR 1, L_0x55ab20e88f30, L_0x55ab20e88fd0, C4<0>, C4<0>;
+L_0x55ab20e89250 .functor XOR 1, L_0x55ab20e890a0, L_0x55ab20e891b0, C4<0>, C4<0>;
+L_0x55ab20e894d0 .functor AND 1, L_0x55ab20e89360, L_0x55ab20e89430, C4<1>, C4<1>;
+L_0x55ab20e896a0 .functor AND 1, L_0x55ab20e890a0, L_0x55ab20e895c0, C4<1>, C4<1>;
+L_0x55ab20e89790 .functor OR 1, L_0x55ab20e894d0, L_0x55ab20e896a0, C4<0>, C4<0>;
+v0x55ab20c3dea0_0 .net *"_ivl_1", 0 0, L_0x55ab20e88f30; 1 drivers
+v0x55ab20c4e0c0_0 .net *"_ivl_11", 0 0, L_0x55ab20e89360; 1 drivers
+v0x55ab20c4df40_0 .net *"_ivl_13", 0 0, L_0x55ab20e89430; 1 drivers
+v0x55ab20c00e50_0 .net *"_ivl_14", 0 0, L_0x55ab20e894d0; 1 drivers
+v0x55ab20d54660_0 .net *"_ivl_17", 0 0, L_0x55ab20e895c0; 1 drivers
+v0x55ab20e088b0_0 .net *"_ivl_18", 0 0, L_0x55ab20e896a0; 1 drivers
+v0x55ab20c50e60_0 .net *"_ivl_3", 0 0, L_0x55ab20e88fd0; 1 drivers
+v0x55ab20d01160_0 .net *"_ivl_7", 0 0, L_0x55ab20e891b0; 1 drivers
+v0x55ab20cff930_0 .net "carry", 0 0, L_0x55ab20e89790; 1 drivers
+v0x55ab20cff9f0_0 .net "sum", 0 0, L_0x55ab20e89250; 1 drivers
+v0x55ab20cfe100_0 .net "w", 0 0, L_0x55ab20e890a0; 1 drivers
+o0x7f6c34811228 .functor BUFZ 3, C4<zzz>; HiZ drive
+v0x55ab20cfe1c0_0 .net "x", 2 0, o0x7f6c34811228; 0 drivers
+L_0x55ab20e88f30 .part o0x7f6c34811228, 2, 1;
+L_0x55ab20e88fd0 .part o0x7f6c34811228, 1, 1;
+L_0x55ab20e891b0 .part o0x7f6c34811228, 0, 1;
+L_0x55ab20e89360 .part o0x7f6c34811228, 2, 1;
+L_0x55ab20e89430 .part o0x7f6c34811228, 1, 1;
+L_0x55ab20e895c0 .part o0x7f6c34811228, 0, 1;
+S_0x55ab20cfb0d0 .scope module, "user_proj_example" "user_proj_example" 2 38;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "wb_clk_i";
+ .port_info 1 /INPUT 1 "wb_rst_i";
+ .port_info 2 /INPUT 1 "wbs_stb_i";
+ .port_info 3 /INPUT 1 "wbs_cyc_i";
+ .port_info 4 /INPUT 1 "wbs_we_i";
+ .port_info 5 /INPUT 4 "wbs_sel_i";
+ .port_info 6 /INPUT 32 "wbs_dat_i";
+ .port_info 7 /INPUT 32 "wbs_adr_i";
+ .port_info 8 /OUTPUT 1 "wbs_ack_o";
+ .port_info 9 /OUTPUT 32 "wbs_dat_o";
+ .port_info 10 /INPUT 128 "la_data_in";
+ .port_info 11 /OUTPUT 128 "la_data_out";
+ .port_info 12 /INPUT 128 "la_oenb";
+ .port_info 13 /INPUT 2 "io_in";
+ .port_info 14 /OUTPUT 2 "io_out";
+ .port_info 15 /OUTPUT 2 "io_oeb";
+ .port_info 16 /OUTPUT 3 "irq";
+P_0x55ab20ce41c0 .param/l "BITS" 0 2 39, +C4<00000000000000000000000000100000>;
+v0x55ab20e87670_0 .net *"_ivl_10", 36 0, L_0x55ab20e89dd0; 1 drivers
+L_0x7f6c347c8060 .functor BUFT 1, C4<0000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x55ab20e87770_0 .net *"_ivl_13", 33 0, L_0x7f6c347c8060; 1 drivers
+L_0x7f6c347c80a8 .functor BUFT 1, C4<0000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x55ab20e87850_0 .net/2u *"_ivl_14", 18 0, L_0x7f6c347c80a8; 1 drivers
+v0x55ab20e87910_0 .net *"_ivl_16", 37 0, L_0x55ab20e99fa0; 1 drivers
+L_0x7f6c347c8018 .functor BUFT 1, C4<x>, C4<0>, C4<0>, C4<0>;
+v0x55ab20e879f0_0 .net *"_ivl_5", 0 0, L_0x7f6c347c8018; 1 drivers
+v0x55ab20e87ad0_0 .net *"_ivl_7", 1 0, L_0x55ab20e89bc0; 1 drivers
+v0x55ab20e87bb0_0 .net *"_ivl_9", 2 0, L_0x55ab20e89c90; 1 drivers
+v0x55ab20e87c90_0 .net "en_mode", 0 0, L_0x55ab20e89ad0; 1 drivers
+v0x55ab20e87d30_0 .net "in1", 17 0, L_0x55ab20e898a0; 1 drivers
+v0x55ab20e87dd0_0 .net "in2", 17 0, L_0x55ab20e89990; 1 drivers
+o0x7f6c34825598 .functor BUFZ 2, C4<zz>; HiZ drive
+v0x55ab20e87e70_0 .net "io_in", -1 0, o0x7f6c34825598; 0 drivers
+o0x7f6c348255c8 .functor BUFZ 2, C4<zz>; HiZ drive
+v0x55ab20e87f30_0 .net "io_oeb", -1 0, o0x7f6c348255c8; 0 drivers
+v0x55ab20e88010_0 .net "io_out", -1 0, L_0x55ab20e9a0e0; 1 drivers
+o0x7f6c34825628 .functor BUFZ 3, C4<zzz>; HiZ drive
+v0x55ab20e880f0_0 .net "irq", 2 0, o0x7f6c34825628; 0 drivers
+o0x7f6c34825658 .functor BUFZ 128, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x55ab20e881d0_0 .net "la_data_in", 127 0, o0x7f6c34825658; 0 drivers
+o0x7f6c34825688 .functor BUFZ 128, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x55ab20e882b0_0 .net "la_data_out", 127 0, o0x7f6c34825688; 0 drivers
+o0x7f6c348256b8 .functor BUFZ 128, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x55ab20e88390_0 .net "la_oenb", 127 0, o0x7f6c348256b8; 0 drivers
+v0x55ab20e88470_0 .net "out", 18 0, L_0x55ab20ef6b10; 1 drivers
+o0x7f6c348256e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55ab20e88530_0 .net "wb_clk_i", 0 0, o0x7f6c348256e8; 0 drivers
+o0x7f6c34825718 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55ab20e885d0_0 .net "wb_rst_i", 0 0, o0x7f6c34825718; 0 drivers
+o0x7f6c34825748 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55ab20e88690_0 .net "wbs_ack_o", 0 0, o0x7f6c34825748; 0 drivers
+o0x7f6c34825778 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x55ab20e88750_0 .net "wbs_adr_i", 31 0, o0x7f6c34825778; 0 drivers
+o0x7f6c348257a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55ab20e88830_0 .net "wbs_cyc_i", 0 0, o0x7f6c348257a8; 0 drivers
+o0x7f6c348257d8 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x55ab20e888f0_0 .net "wbs_dat_i", 31 0, o0x7f6c348257d8; 0 drivers
+o0x7f6c34825808 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x55ab20e889d0_0 .net "wbs_dat_o", 31 0, o0x7f6c34825808; 0 drivers
+o0x7f6c34825838 .functor BUFZ 4, C4<zzzz>; HiZ drive
+v0x55ab20e88ab0_0 .net "wbs_sel_i", 3 0, o0x7f6c34825838; 0 drivers
+o0x7f6c34825868 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55ab20e88b90_0 .net "wbs_stb_i", 0 0, o0x7f6c34825868; 0 drivers
+o0x7f6c34825898 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55ab20e88c50_0 .net "wbs_we_i", 0 0, o0x7f6c34825898; 0 drivers
+L_0x55ab20e898a0 .part L_0x55ab20e89dd0, 19, 18;
+L_0x55ab20e89990 .part L_0x55ab20e89dd0, 1, 18;
+L_0x55ab20e89ad0 .part L_0x55ab20e89dd0, 0, 1;
+L_0x55ab20e89bc0 .part o0x7f6c34825598, 0, 2;
+L_0x55ab20e89c90 .concat [ 2 1 0 0], L_0x55ab20e89bc0, L_0x7f6c347c8018;
+L_0x55ab20e89dd0 .concat [ 3 34 0 0], L_0x55ab20e89c90, L_0x7f6c347c8060;
+L_0x55ab20e99fa0 .concat [ 19 19 0 0], L_0x55ab20ef6b10, L_0x7f6c347c80a8;
+L_0x55ab20e9a0e0 .part L_0x55ab20e99fa0, 0, 2;
+S_0x55ab20d54e20 .scope module, "adder" "adder" 2 83, 2 119 0, S_0x55ab20cfb0d0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 18 "p";
+ .port_info 1 /INPUT 18 "q";
+ .port_info 2 /INPUT 1 "mode";
+ .port_info 3 /OUTPUT 19 "sum";
+P_0x55ab20df4a90 .param/l "num" 0 2 121, +C4<00000000000000000000000000010010>;
+L_0x55ab20ef1ee0 .functor XOR 19, L_0x55ab20ef1870, L_0x55ab20ef1e40, C4<0000000000000000000>, C4<0000000000000000000>;
+L_0x55ab20ef2430 .functor XOR 1, L_0x55ab20e89ad0, L_0x55ab20ef1ff0, C4<0>, C4<0>;
+L_0x55ab20ef2e70 .functor XOR 19, L_0x55ab20ef24f0, L_0x55ab20ef2d80, C4<0000000000000000000>, C4<0000000000000000000>;
+L_0x55ab20ef4460 .functor XOR 1, L_0x55ab20ef3fe0, L_0x55ab20e89ad0, C4<0>, C4<0>;
+L_0x55ab20ef45b0 .functor AND 1, L_0x55ab20ef3f40, L_0x55ab20ef4460, C4<1>, C4<1>;
+L_0x55ab20ef52e0 .functor XOR 1, L_0x55ab20ef4db0, L_0x55ab20ef5240, C4<0>, C4<0>;
+L_0x55ab20ef6420 .functor XOR 1, L_0x55ab20ea3990, L_0x55ab20ef5f70, C4<0>, C4<0>;
+L_0x55ab20ef6530 .functor XOR 1, L_0x55ab20ef6420, L_0x55ab20e89ad0, C4<0>, C4<0>;
+v0x55ab20e84ff0_0 .net *"_ivl_216", 0 0, L_0x55ab20ef1450; 1 drivers
+v0x55ab20e850f0_0 .net *"_ivl_217", 18 0, L_0x55ab20ef1870; 1 drivers
+L_0x7f6c347c80f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
+v0x55ab20e851d0_0 .net/2u *"_ivl_219", 1 0, L_0x7f6c347c80f0; 1 drivers
+v0x55ab20e85290_0 .net *"_ivl_222", 16 0, L_0x55ab20ef1a10; 1 drivers
+v0x55ab20e85370_0 .net *"_ivl_223", 18 0, L_0x55ab20ef1e40; 1 drivers
+v0x55ab20e85450_0 .net *"_ivl_228", 0 0, L_0x55ab20ef1ff0; 1 drivers
+v0x55ab20e85530_0 .net *"_ivl_229", 0 0, L_0x55ab20ef2430; 1 drivers
+v0x55ab20e85610_0 .net *"_ivl_231", 18 0, L_0x55ab20ef24f0; 1 drivers
+L_0x7f6c347c8138 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
+v0x55ab20e856f0_0 .net/2u *"_ivl_233", 1 0, L_0x7f6c347c8138; 1 drivers
+v0x55ab20e85860_0 .net *"_ivl_236", 16 0, L_0x55ab20ef2930; 1 drivers
+v0x55ab20e85940_0 .net *"_ivl_237", 18 0, L_0x55ab20ef2d80; 1 drivers
+v0x55ab20e85a20_0 .net *"_ivl_244", 0 0, L_0x55ab20ef2f80; 1 drivers
+v0x55ab20e85b00_0 .net *"_ivl_248", 0 0, L_0x55ab20ef33e0; 1 drivers
+v0x55ab20e85be0_0 .net *"_ivl_253", 0 0, L_0x55ab20ef3f40; 1 drivers
+v0x55ab20e85cc0_0 .net *"_ivl_255", 0 0, L_0x55ab20ef3fe0; 1 drivers
+v0x55ab20e85da0_0 .net *"_ivl_256", 0 0, L_0x55ab20ef4460; 1 drivers
+v0x55ab20e85e80_0 .net *"_ivl_258", 0 0, L_0x55ab20ef45b0; 1 drivers
+v0x55ab20e86070_0 .net *"_ivl_264", 0 0, L_0x55ab20ef4db0; 1 drivers
+v0x55ab20e86150_0 .net *"_ivl_266", 0 0, L_0x55ab20ef5240; 1 drivers
+v0x55ab20e86230_0 .net *"_ivl_267", 0 0, L_0x55ab20ef52e0; 1 drivers
+v0x55ab20e86310_0 .net *"_ivl_274", 0 0, L_0x55ab20ea3990; 1 drivers
+v0x55ab20e863f0_0 .net *"_ivl_276", 0 0, L_0x55ab20ef5f70; 1 drivers
+v0x55ab20e864d0_0 .net *"_ivl_277", 0 0, L_0x55ab20ef6420; 1 drivers
+v0x55ab20e865b0_0 .net *"_ivl_279", 0 0, L_0x55ab20ef6530; 1 drivers
+v0x55ab20e86690_0 .net *"_ivl_281", 1 0, L_0x55ab20ef6640; 1 drivers
+L_0x7f6c347c8180 .functor BUFT 1, C4<0000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x55ab20e86770_0 .net *"_ivl_283", 18 0, L_0x7f6c347c8180; 1 drivers
+v0x55ab20e86850_0 .net *"_ivl_288", 0 0, L_0x55ab20ef6d50; 1 drivers
+v0x55ab20e86930_0 .net *"_ivl_290", 0 0, L_0x55ab20ef6df0; 1 drivers
+v0x55ab20e86a10_0 .net *"_ivl_292", 17 0, L_0x55ab20ef6930; 1 drivers
+v0x55ab20e86af0_0 .net *"_ivl_293", 18 0, L_0x55ab20ef69d0; 1 drivers
+v0x55ab20e86bd0_0 .net "a", 18 0, L_0x55ab20ef46c0; 1 drivers
+v0x55ab20e86cb0_0 .net "a1", 18 0, L_0x55ab20ef1ee0; 1 drivers
+v0x55ab20e86d90_0 .net "b", 18 0, L_0x55ab20ef3480; 1 drivers
+v0x55ab20e86e70_0 .net "b1", 18 0, L_0x55ab20ef2e70; 1 drivers
+v0x55ab20e86f50_0 .net "mode", 0 0, L_0x55ab20e89ad0; alias, 1 drivers
+v0x55ab20e87010_0 .net "p", 17 0, L_0x55ab20e898a0; alias, 1 drivers
+v0x55ab20e870f0_0 .net "q", 17 0, L_0x55ab20e89990; alias, 1 drivers
+v0x55ab20e871d0_0 .net "sum", 18 0, L_0x55ab20ef6b10; alias, 1 drivers
+v0x55ab20e872b0_0 .net "temp", 18 0, L_0x55ab20ef05a0; 1 drivers
+v0x55ab20e87390_0 .net "temp1", 18 0, L_0x55ab20ef6780; 1 drivers
+v0x55ab20e87470 .array "x", 5 0;
+v0x55ab20e87470_0 .net v0x55ab20e87470 0, 37 0, L_0x55ab20ef5480; 1 drivers
+v0x55ab20e87470_1 .net v0x55ab20e87470 1, 37 0, L_0x55ab20ebb860; 1 drivers
+v0x55ab20e87470_2 .net v0x55ab20e87470 2, 37 0, L_0x55ab20ecbe30; 1 drivers
+v0x55ab20e87470_3 .net v0x55ab20e87470 3, 37 0, L_0x55ab20eda6a0; 1 drivers
+v0x55ab20e87470_4 .net v0x55ab20e87470 4, 37 0, L_0x55ab20ee4ef0; 1 drivers
+v0x55ab20e87470_5 .net v0x55ab20e87470 5, 37 0, L_0x55ab20ee8010; 1 drivers
+L_0x55ab20e9a780 .part L_0x55ab20ef1ee0, 1, 1;
+L_0x55ab20e9a820 .part L_0x55ab20ef2e70, 1, 1;
+L_0x55ab20e9afc0 .part L_0x55ab20ef1ee0, 2, 1;
+L_0x55ab20e9b0b0 .part L_0x55ab20ef2e70, 2, 1;
+L_0x55ab20e9b870 .part L_0x55ab20ef1ee0, 3, 1;
+L_0x55ab20e9b910 .part L_0x55ab20ef2e70, 3, 1;
+L_0x55ab20e9c0c0 .part L_0x55ab20ef1ee0, 4, 1;
+L_0x55ab20e9c1f0 .part L_0x55ab20ef2e70, 4, 1;
+L_0x55ab20e9c9d0 .part L_0x55ab20ef1ee0, 5, 1;
+L_0x55ab20e9ca70 .part L_0x55ab20ef2e70, 5, 1;
+L_0x55ab20e9d220 .part L_0x55ab20ef1ee0, 6, 1;
+L_0x55ab20e9d2c0 .part L_0x55ab20ef2e70, 6, 1;
+L_0x55ab20e9daa0 .part L_0x55ab20ef1ee0, 7, 1;
+L_0x55ab20e9db40 .part L_0x55ab20ef2e70, 7, 1;
+L_0x55ab20e9e2f0 .part L_0x55ab20ef1ee0, 8, 1;
+L_0x55ab20e9e4a0 .part L_0x55ab20ef2e70, 8, 1;
+L_0x55ab20e9ed50 .part L_0x55ab20ef1ee0, 9, 1;
+L_0x55ab20e9edf0 .part L_0x55ab20ef2e70, 9, 1;
+L_0x55ab20e9f5a0 .part L_0x55ab20ef1ee0, 10, 1;
+L_0x55ab20e9f640 .part L_0x55ab20ef2e70, 10, 1;
+L_0x55ab20e9fd60 .part L_0x55ab20ef1ee0, 11, 1;
+L_0x55ab20e9fe00 .part L_0x55ab20ef2e70, 11, 1;
+L_0x55ab20ea0660 .part L_0x55ab20ef1ee0, 12, 1;
+L_0x55ab20ea0700 .part L_0x55ab20ef2e70, 12, 1;
+L_0x55ab20ea0f70 .part L_0x55ab20ef1ee0, 13, 1;
+L_0x55ab20ea1010 .part L_0x55ab20ef2e70, 13, 1;
+L_0x55ab20ea1890 .part L_0x55ab20ef1ee0, 14, 1;
+L_0x55ab20ea1930 .part L_0x55ab20ef2e70, 14, 1;
+L_0x55ab20ea21c0 .part L_0x55ab20ef1ee0, 15, 1;
+L_0x55ab20ea2260 .part L_0x55ab20ef2e70, 15, 1;
+L_0x55ab20ea2ad0 .part L_0x55ab20ef1ee0, 16, 1;
+L_0x55ab20ea2d80 .part L_0x55ab20ef2e70, 16, 1;
+L_0x55ab20ea37e0 .part L_0x55ab20ef1ee0, 17, 1;
+L_0x55ab20ea3880 .part L_0x55ab20ef2e70, 17, 1;
+L_0x55ab20ea3e70 .part L_0x55ab20ef46c0, 0, 1;
+L_0x55ab20ea3f10 .part L_0x55ab20ef3480, 0, 1;
+L_0x55ab20ea4330 .part L_0x55ab20ef46c0, 1, 1;
+L_0x55ab20ea4420 .part L_0x55ab20ef3480, 1, 1;
+L_0x55ab20ea4910 .part L_0x55ab20ef46c0, 2, 1;
+L_0x55ab20ea49b0 .part L_0x55ab20ef3480, 2, 1;
+L_0x55ab20ea4e60 .part L_0x55ab20ef46c0, 3, 1;
+L_0x55ab20ea4f90 .part L_0x55ab20ef3480, 3, 1;
+L_0x55ab20ea5440 .part L_0x55ab20ef46c0, 4, 1;
+L_0x55ab20ea54e0 .part L_0x55ab20ef3480, 4, 1;
+L_0x55ab20ea59e0 .part L_0x55ab20ef46c0, 5, 1;
+L_0x55ab20ea5a80 .part L_0x55ab20ef3480, 5, 1;
+L_0x55ab20ea5f90 .part L_0x55ab20ef46c0, 6, 1;
+L_0x55ab20ea6030 .part L_0x55ab20ef3480, 6, 1;
+L_0x55ab20ea6520 .part L_0x55ab20ef46c0, 7, 1;
+L_0x55ab20ea65c0 .part L_0x55ab20ef3480, 7, 1;
+L_0x55ab20ea6af0 .part L_0x55ab20ef46c0, 8, 1;
+L_0x55ab20ea6b90 .part L_0x55ab20ef3480, 8, 1;
+L_0x55ab20ea6f40 .part L_0x55ab20ef46c0, 9, 1;
+L_0x55ab20ea6fe0 .part L_0x55ab20ef3480, 9, 1;
+L_0x55ab20ea7530 .part L_0x55ab20ef46c0, 10, 1;
+L_0x55ab20ea75d0 .part L_0x55ab20ef3480, 10, 1;
+L_0x55ab20ea7b30 .part L_0x55ab20ef46c0, 11, 1;
+L_0x55ab20ea7bd0 .part L_0x55ab20ef3480, 11, 1;
+L_0x55ab20ea8140 .part L_0x55ab20ef46c0, 12, 1;
+L_0x55ab20ea81e0 .part L_0x55ab20ef3480, 12, 1;
+L_0x55ab20ea8760 .part L_0x55ab20ef46c0, 13, 1;
+L_0x55ab20ea8800 .part L_0x55ab20ef3480, 13, 1;
+L_0x55ab20ea8d90 .part L_0x55ab20ef46c0, 14, 1;
+L_0x55ab20ea8e30 .part L_0x55ab20ef3480, 14, 1;
+L_0x55ab20ea93d0 .part L_0x55ab20ef46c0, 15, 1;
+L_0x55ab20ea9680 .part L_0x55ab20ef3480, 15, 1;
+L_0x55ab20ea9e40 .part L_0x55ab20ef46c0, 16, 1;
+L_0x55ab20ea9ee0 .part L_0x55ab20ef3480, 16, 1;
+L_0x55ab20eaa470 .part L_0x55ab20ef46c0, 17, 1;
+L_0x55ab20eaa510 .part L_0x55ab20ef3480, 17, 1;
+L_0x55ab20ee81f0 .part L_0x55ab20ef46c0, 0, 1;
+L_0x55ab20ee8290 .part L_0x55ab20ef3480, 0, 1;
+L_0x55ab20ee8890 .part L_0x55ab20ef46c0, 1, 1;
+L_0x55ab20ee8930 .part L_0x55ab20ef3480, 1, 1;
+L_0x55ab20ee8ef0 .part L_0x55ab20ef46c0, 2, 1;
+L_0x55ab20ee8f90 .part L_0x55ab20ef3480, 2, 1;
+L_0x55ab20ee9510 .part L_0x55ab20ef46c0, 3, 1;
+L_0x55ab20ee95b0 .part L_0x55ab20ef3480, 3, 1;
+L_0x55ab20ee9b90 .part L_0x55ab20ef46c0, 4, 1;
+L_0x55ab20ee9c30 .part L_0x55ab20ef3480, 4, 1;
+L_0x55ab20eea220 .part L_0x55ab20ef46c0, 5, 1;
+L_0x55ab20eea2c0 .part L_0x55ab20ef3480, 5, 1;
+L_0x55ab20eea8c0 .part L_0x55ab20ef46c0, 6, 1;
+L_0x55ab20eea960 .part L_0x55ab20ef3480, 6, 1;
+L_0x55ab20eeaf70 .part L_0x55ab20ef46c0, 7, 1;
+L_0x55ab20eeb010 .part L_0x55ab20ef3480, 7, 1;
+L_0x55ab20eeb630 .part L_0x55ab20ef46c0, 8, 1;
+L_0x55ab20eeb6d0 .part L_0x55ab20ef3480, 8, 1;
+L_0x55ab20eebd00 .part L_0x55ab20ef46c0, 9, 1;
+L_0x55ab20eebda0 .part L_0x55ab20ef3480, 9, 1;
+L_0x55ab20eec3e0 .part L_0x55ab20ef46c0, 10, 1;
+L_0x55ab20eec480 .part L_0x55ab20ef3480, 10, 1;
+L_0x55ab20eecad0 .part L_0x55ab20ef46c0, 11, 1;
+L_0x55ab20eecb70 .part L_0x55ab20ef3480, 11, 1;
+L_0x55ab20eed1d0 .part L_0x55ab20ef46c0, 12, 1;
+L_0x55ab20eed270 .part L_0x55ab20ef3480, 12, 1;
+L_0x55ab20eed8e0 .part L_0x55ab20ef46c0, 13, 1;
+L_0x55ab20eedd90 .part L_0x55ab20ef3480, 13, 1;
+L_0x55ab20eee820 .part L_0x55ab20ef46c0, 14, 1;
+L_0x55ab20eee8c0 .part L_0x55ab20ef3480, 14, 1;
+L_0x55ab20eeef50 .part L_0x55ab20ef46c0, 15, 1;
+L_0x55ab20eeeff0 .part L_0x55ab20ef3480, 15, 1;
+L_0x55ab20eef690 .part L_0x55ab20ef46c0, 16, 1;
+L_0x55ab20eef730 .part L_0x55ab20ef3480, 16, 1;
+L_0x55ab20eefe10 .part L_0x55ab20ef46c0, 17, 1;
+L_0x55ab20eefeb0 .part L_0x55ab20ef3480, 17, 1;
+LS_0x55ab20ef05a0_0_0 .concat8 [ 1 1 1 1], L_0x55ab20ee8780, L_0x55ab20ee8de0, L_0x55ab20ee9450, L_0x55ab20ee9a80;
+LS_0x55ab20ef05a0_0_4 .concat8 [ 1 1 1 1], L_0x55ab20eea110, L_0x55ab20eea7b0, L_0x55ab20eeae60, L_0x55ab20eeb520;
+LS_0x55ab20ef05a0_0_8 .concat8 [ 1 1 1 1], L_0x55ab20eebbf0, L_0x55ab20eec2d0, L_0x55ab20eec9c0, L_0x55ab20eed0c0;
+LS_0x55ab20ef05a0_0_12 .concat8 [ 1 1 1 1], L_0x55ab20eed7d0, L_0x55ab20eee710, L_0x55ab20eeee40, L_0x55ab20eef580;
+LS_0x55ab20ef05a0_0_16 .concat8 [ 1 1 1 0], L_0x55ab20eefd00, L_0x55ab20ef0490, L_0x55ab20ef12f0;
+LS_0x55ab20ef05a0_1_0 .concat8 [ 4 4 4 4], LS_0x55ab20ef05a0_0_0, LS_0x55ab20ef05a0_0_4, LS_0x55ab20ef05a0_0_8, LS_0x55ab20ef05a0_0_12;
+LS_0x55ab20ef05a0_1_4 .concat8 [ 3 0 0 0], LS_0x55ab20ef05a0_0_16;
+L_0x55ab20ef05a0 .concat8 [ 16 3 0 0], LS_0x55ab20ef05a0_1_0, LS_0x55ab20ef05a0_1_4;
+L_0x55ab20ef0c90 .part L_0x55ab20ef46c0, 18, 1;
+L_0x55ab20ef10a0 .part L_0x55ab20ef3480, 18, 1;
+L_0x55ab20ef1450 .part L_0x55ab20e898a0, 17, 1;
+LS_0x55ab20ef1870_0_0 .concat [ 1 1 1 1], L_0x55ab20ef1450, L_0x55ab20ef1450, L_0x55ab20ef1450, L_0x55ab20ef1450;
+LS_0x55ab20ef1870_0_4 .concat [ 1 1 1 1], L_0x55ab20ef1450, L_0x55ab20ef1450, L_0x55ab20ef1450, L_0x55ab20ef1450;
+LS_0x55ab20ef1870_0_8 .concat [ 1 1 1 1], L_0x55ab20ef1450, L_0x55ab20ef1450, L_0x55ab20ef1450, L_0x55ab20ef1450;
+LS_0x55ab20ef1870_0_12 .concat [ 1 1 1 1], L_0x55ab20ef1450, L_0x55ab20ef1450, L_0x55ab20ef1450, L_0x55ab20ef1450;
+LS_0x55ab20ef1870_0_16 .concat [ 1 1 1 0], L_0x55ab20ef1450, L_0x55ab20ef1450, L_0x55ab20ef1450;
+LS_0x55ab20ef1870_1_0 .concat [ 4 4 4 4], LS_0x55ab20ef1870_0_0, LS_0x55ab20ef1870_0_4, LS_0x55ab20ef1870_0_8, LS_0x55ab20ef1870_0_12;
+LS_0x55ab20ef1870_1_4 .concat [ 3 0 0 0], LS_0x55ab20ef1870_0_16;
+L_0x55ab20ef1870 .concat [ 16 3 0 0], LS_0x55ab20ef1870_1_0, LS_0x55ab20ef1870_1_4;
+L_0x55ab20ef1a10 .part L_0x55ab20e898a0, 0, 17;
+L_0x55ab20ef1e40 .concat [ 17 2 0 0], L_0x55ab20ef1a10, L_0x7f6c347c80f0;
+L_0x55ab20ef1ff0 .part L_0x55ab20e89990, 17, 1;
+LS_0x55ab20ef24f0_0_0 .concat [ 1 1 1 1], L_0x55ab20ef2430, L_0x55ab20ef2430, L_0x55ab20ef2430, L_0x55ab20ef2430;
+LS_0x55ab20ef24f0_0_4 .concat [ 1 1 1 1], L_0x55ab20ef2430, L_0x55ab20ef2430, L_0x55ab20ef2430, L_0x55ab20ef2430;
+LS_0x55ab20ef24f0_0_8 .concat [ 1 1 1 1], L_0x55ab20ef2430, L_0x55ab20ef2430, L_0x55ab20ef2430, L_0x55ab20ef2430;
+LS_0x55ab20ef24f0_0_12 .concat [ 1 1 1 1], L_0x55ab20ef2430, L_0x55ab20ef2430, L_0x55ab20ef2430, L_0x55ab20ef2430;
+LS_0x55ab20ef24f0_0_16 .concat [ 1 1 1 0], L_0x55ab20ef2430, L_0x55ab20ef2430, L_0x55ab20ef2430;
+LS_0x55ab20ef24f0_1_0 .concat [ 4 4 4 4], LS_0x55ab20ef24f0_0_0, LS_0x55ab20ef24f0_0_4, LS_0x55ab20ef24f0_0_8, LS_0x55ab20ef24f0_0_12;
+LS_0x55ab20ef24f0_1_4 .concat [ 3 0 0 0], LS_0x55ab20ef24f0_0_16;
+L_0x55ab20ef24f0 .concat [ 16 3 0 0], LS_0x55ab20ef24f0_1_0, LS_0x55ab20ef24f0_1_4;
+L_0x55ab20ef2930 .part L_0x55ab20e89990, 0, 17;
+L_0x55ab20ef2d80 .concat [ 17 2 0 0], L_0x55ab20ef2930, L_0x7f6c347c8138;
+L_0x55ab20ef2f80 .part L_0x55ab20ef1ee0, 0, 1;
+L_0x55ab20ef33e0 .part L_0x55ab20ef2e70, 0, 1;
+LS_0x55ab20ef3480_0_0 .concat8 [ 1 1 1 1], L_0x55ab20ef33e0, L_0x55ab20ef45b0, L_0x55ab20e9a6c0, L_0x55ab20e9af00;
+LS_0x55ab20ef3480_0_4 .concat8 [ 1 1 1 1], L_0x55ab20e9b7b0, L_0x55ab20e9bfd0, L_0x55ab20e9c8e0, L_0x55ab20e9d130;
+LS_0x55ab20ef3480_0_8 .concat8 [ 1 1 1 1], L_0x55ab20e9d9e0, L_0x55ab20e9e200, L_0x55ab20e9ec60, L_0x55ab20e9f4b0;
+LS_0x55ab20ef3480_0_12 .concat8 [ 1 1 1 1], L_0x55ab20e9fc70, L_0x55ab20ea0570, L_0x55ab20ea0e80, L_0x55ab20ea17a0;
+LS_0x55ab20ef3480_0_16 .concat8 [ 1 1 1 0], L_0x55ab20ea20d0, L_0x55ab20ea2a10, L_0x55ab20ea3720;
+LS_0x55ab20ef3480_1_0 .concat8 [ 4 4 4 4], LS_0x55ab20ef3480_0_0, LS_0x55ab20ef3480_0_4, LS_0x55ab20ef3480_0_8, LS_0x55ab20ef3480_0_12;
+LS_0x55ab20ef3480_1_4 .concat8 [ 3 0 0 0], LS_0x55ab20ef3480_0_16;
+L_0x55ab20ef3480 .concat8 [ 16 3 0 0], LS_0x55ab20ef3480_1_0, LS_0x55ab20ef3480_1_4;
+L_0x55ab20ef3f40 .part L_0x55ab20e898a0, 17, 1;
+L_0x55ab20ef3fe0 .part L_0x55ab20e89990, 17, 1;
+LS_0x55ab20ef46c0_0_0 .concat8 [ 1 1 1 1], L_0x55ab20ef2f80, L_0x55ab20e9a3b0, L_0x55ab20e9abf0, L_0x55ab20e9b4a0;
+LS_0x55ab20ef46c0_0_4 .concat8 [ 1 1 1 1], L_0x55ab20e9bcc0, L_0x55ab20e9c5d0, L_0x55ab20e9ce20, L_0x55ab20e9d6d0;
+LS_0x55ab20ef46c0_0_8 .concat8 [ 1 1 1 1], L_0x55ab20e9d360, L_0x55ab20e9e9e0, L_0x55ab20e9f230, L_0x55ab20e9f9f0;
+LS_0x55ab20ef46c0_0_12 .concat8 [ 1 1 1 1], L_0x55ab20ea0260, L_0x55ab20ea0b70, L_0x55ab20ea1490, L_0x55ab20ea1dc0;
+LS_0x55ab20ef46c0_0_16 .concat8 [ 1 1 1 0], L_0x55ab20ea2700, L_0x55ab20ea3410, L_0x55ab20ef52e0;
+LS_0x55ab20ef46c0_1_0 .concat8 [ 4 4 4 4], LS_0x55ab20ef46c0_0_0, LS_0x55ab20ef46c0_0_4, LS_0x55ab20ef46c0_0_8, LS_0x55ab20ef46c0_0_12;
+LS_0x55ab20ef46c0_1_4 .concat8 [ 3 0 0 0], LS_0x55ab20ef46c0_0_16;
+L_0x55ab20ef46c0 .concat8 [ 16 3 0 0], LS_0x55ab20ef46c0_1_0, LS_0x55ab20ef46c0_1_4;
+L_0x55ab20ef4db0 .part L_0x55ab20ef1ee0, 18, 1;
+L_0x55ab20ef5240 .part L_0x55ab20ef2e70, 18, 1;
+LS_0x55ab20ef5480_0_0 .concat8 [ 2 2 2 2], L_0x55ab20ef6640, L_0x55ab20ea3bf0, L_0x55ab20ea40e0, L_0x55ab20ea46c0;
+LS_0x55ab20ef5480_0_4 .concat8 [ 2 2 2 2], L_0x55ab20ea4c10, L_0x55ab20ea5290, L_0x55ab20ea5760, L_0x55ab20ea5d10;
+LS_0x55ab20ef5480_0_8 .concat8 [ 2 2 2 2], L_0x55ab20ea62d0, L_0x55ab20ea6870, L_0x55ab20ea66d0, L_0x55ab20ea72b0;
+LS_0x55ab20ef5480_0_12 .concat8 [ 2 2 2 2], L_0x55ab20ea78b0, L_0x55ab20ea7ec0, L_0x55ab20ea84e0, L_0x55ab20ea8b10;
+LS_0x55ab20ef5480_0_16 .concat8 [ 2 2 2 0], L_0x55ab20ea9150, L_0x55ab20ea9bc0, L_0x55ab20eaa220;
+LS_0x55ab20ef5480_1_0 .concat8 [ 8 8 8 8], LS_0x55ab20ef5480_0_0, LS_0x55ab20ef5480_0_4, LS_0x55ab20ef5480_0_8, LS_0x55ab20ef5480_0_12;
+LS_0x55ab20ef5480_1_4 .concat8 [ 6 0 0 0], LS_0x55ab20ef5480_0_16;
+L_0x55ab20ef5480 .concat8 [ 32 6 0 0], LS_0x55ab20ef5480_1_0, LS_0x55ab20ef5480_1_4;
+L_0x55ab20ea3990 .part L_0x55ab20e898a0, 17, 1;
+L_0x55ab20ef5f70 .part L_0x55ab20e89990, 17, 1;
+L_0x55ab20ef6640 .concat [ 1 1 0 0], L_0x55ab20ef6530, L_0x55ab20ef6530;
+L_0x55ab20ef6780 .arith/sub 19, L_0x7f6c347c8180, L_0x55ab20ef05a0;
+L_0x55ab20ef6d50 .part L_0x55ab20ef05a0, 18, 1;
+L_0x55ab20ef6df0 .part L_0x55ab20ef05a0, 18, 1;
+L_0x55ab20ef6930 .part L_0x55ab20ef6780, 0, 18;
+L_0x55ab20ef69d0 .concat [ 18 1 0 0], L_0x55ab20ef6930, L_0x55ab20ef6df0;
+L_0x55ab20ef6b10 .functor MUXZ 19, L_0x55ab20ef05a0, L_0x55ab20ef69d0, L_0x55ab20ef6d50, C4<>;
+S_0x55ab20e31180 .scope generate, "addition" "addition" 2 170, 2 170 0, S_0x55ab20d54e20;
+ .timescale 0 0;
+S_0x55ab20e2e220 .scope generate, "genblk9[0]" "genblk9[0]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20cd0860 .param/l "i" 0 2 171, +C4<00>;
+L_0x55ab20ee8580 .functor XOR 1, L_0x55ab20ee81f0, L_0x55ab20ee8290, C4<0>, C4<0>;
+L_0x55ab20ee8780 .functor XOR 1, L_0x55ab20ee8580, L_0x55ab20ee8690, C4<0>, C4<0>;
+v0x55ab20cfaf00_0 .net *"_ivl_0", 0 0, L_0x55ab20ee81f0; 1 drivers
+v0x55ab20cf81a0_0 .net *"_ivl_1", 0 0, L_0x55ab20ee8290; 1 drivers
+v0x55ab20cf8260_0 .net *"_ivl_2", 0 0, L_0x55ab20ee8580; 1 drivers
+v0x55ab20cf54f0_0 .net *"_ivl_6", 0 0, L_0x55ab20ee8690; 1 drivers
+v0x55ab20cf2800_0 .net *"_ivl_7", 0 0, L_0x55ab20ee8780; 1 drivers
+L_0x55ab20ee8690 .part L_0x55ab20ee8010, 0, 1;
+S_0x55ab20e2c2f0 .scope generate, "genblk9[1]" "genblk9[1]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20cf28e0 .param/l "i" 0 2 171, +C4<01>;
+L_0x55ab20ee8c30 .functor XOR 1, L_0x55ab20ee8890, L_0x55ab20ee8930, C4<0>, C4<0>;
+L_0x55ab20ee8de0 .functor XOR 1, L_0x55ab20ee8c30, L_0x55ab20ee8d40, C4<0>, C4<0>;
+v0x55ab20cefb80_0 .net *"_ivl_0", 0 0, L_0x55ab20ee8890; 1 drivers
+v0x55ab20cece60_0 .net *"_ivl_1", 0 0, L_0x55ab20ee8930; 1 drivers
+v0x55ab20cea190_0 .net *"_ivl_2", 0 0, L_0x55ab20ee8c30; 1 drivers
+v0x55ab20cea250_0 .net *"_ivl_6", 0 0, L_0x55ab20ee8d40; 1 drivers
+v0x55ab20ce74c0_0 .net *"_ivl_7", 0 0, L_0x55ab20ee8de0; 1 drivers
+L_0x55ab20ee8d40 .part L_0x55ab20ee8010, 2, 1;
+S_0x55ab20cf9270 .scope generate, "genblk9[2]" "genblk9[2]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20ce47f0 .param/l "i" 0 2 171, +C4<010>;
+L_0x55ab20ee92a0 .functor XOR 1, L_0x55ab20ee8ef0, L_0x55ab20ee8f90, C4<0>, C4<0>;
+L_0x55ab20ee9450 .functor XOR 1, L_0x55ab20ee92a0, L_0x55ab20ee93b0, C4<0>, C4<0>;
+v0x55ab20ce48b0_0 .net *"_ivl_0", 0 0, L_0x55ab20ee8ef0; 1 drivers
+v0x55ab20ce1b40_0 .net *"_ivl_1", 0 0, L_0x55ab20ee8f90; 1 drivers
+v0x55ab20cdee50_0 .net *"_ivl_2", 0 0, L_0x55ab20ee92a0; 1 drivers
+v0x55ab20cdef10_0 .net *"_ivl_6", 0 0, L_0x55ab20ee93b0; 1 drivers
+v0x55ab20cdc180_0 .net *"_ivl_7", 0 0, L_0x55ab20ee9450; 1 drivers
+L_0x55ab20ee93b0 .part L_0x55ab20ee8010, 4, 1;
+S_0x55ab20cfa030 .scope generate, "genblk9[3]" "genblk9[3]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20cd94d0 .param/l "i" 0 2 171, +C4<011>;
+L_0x55ab20ee98d0 .functor XOR 1, L_0x55ab20ee9510, L_0x55ab20ee95b0, C4<0>, C4<0>;
+L_0x55ab20ee9a80 .functor XOR 1, L_0x55ab20ee98d0, L_0x55ab20ee99e0, C4<0>, C4<0>;
+v0x55ab20cd67e0_0 .net *"_ivl_0", 0 0, L_0x55ab20ee9510; 1 drivers
+v0x55ab20cd3b10_0 .net *"_ivl_1", 0 0, L_0x55ab20ee95b0; 1 drivers
+v0x55ab20cd0e40_0 .net *"_ivl_2", 0 0, L_0x55ab20ee98d0; 1 drivers
+v0x55ab20cd0f00_0 .net *"_ivl_6", 0 0, L_0x55ab20ee99e0; 1 drivers
+v0x55ab20cce110_0 .net *"_ivl_7", 0 0, L_0x55ab20ee9a80; 1 drivers
+L_0x55ab20ee99e0 .part L_0x55ab20ee8010, 6, 1;
+S_0x55ab20cf65a0 .scope generate, "genblk9[4]" "genblk9[4]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20cd3bf0 .param/l "i" 0 2 171, +C4<0100>;
+L_0x55ab20ee9f60 .functor XOR 1, L_0x55ab20ee9b90, L_0x55ab20ee9c30, C4<0>, C4<0>;
+L_0x55ab20eea110 .functor XOR 1, L_0x55ab20ee9f60, L_0x55ab20eea070, C4<0>, C4<0>;
+v0x55ab20d5c930_0 .net *"_ivl_0", 0 0, L_0x55ab20ee9b90; 1 drivers
+v0x55ab20d58b30_0 .net *"_ivl_1", 0 0, L_0x55ab20ee9c30; 1 drivers
+v0x55ab20d58bf0_0 .net *"_ivl_2", 0 0, L_0x55ab20ee9f60; 1 drivers
+v0x55ab20cf7380_0 .net *"_ivl_6", 0 0, L_0x55ab20eea070; 1 drivers
+v0x55ab20cf7460_0 .net *"_ivl_7", 0 0, L_0x55ab20eea110; 1 drivers
+L_0x55ab20eea070 .part L_0x55ab20ee8010, 8, 1;
+S_0x55ab20cf4690 .scope generate, "genblk9[5]" "genblk9[5]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20cf39d0 .param/l "i" 0 2 171, +C4<0101>;
+L_0x55ab20eea600 .functor XOR 1, L_0x55ab20eea220, L_0x55ab20eea2c0, C4<0>, C4<0>;
+L_0x55ab20eea7b0 .functor XOR 1, L_0x55ab20eea600, L_0x55ab20eea710, C4<0>, C4<0>;
+v0x55ab20cf0c40_0 .net *"_ivl_0", 0 0, L_0x55ab20eea220; 1 drivers
+v0x55ab20cf19c0_0 .net *"_ivl_1", 0 0, L_0x55ab20eea2c0; 1 drivers
+v0x55ab20cf1aa0_0 .net *"_ivl_2", 0 0, L_0x55ab20eea600; 1 drivers
+v0x55ab20cedf30_0 .net *"_ivl_6", 0 0, L_0x55ab20eea710; 1 drivers
+v0x55ab20cee010_0 .net *"_ivl_7", 0 0, L_0x55ab20eea7b0; 1 drivers
+L_0x55ab20eea710 .part L_0x55ab20ee8010, 10, 1;
+S_0x55ab20ceecf0 .scope generate, "genblk9[6]" "genblk9[6]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20ceb2d0 .param/l "i" 0 2 171, +C4<0110>;
+L_0x55ab20eeacb0 .functor XOR 1, L_0x55ab20eea8c0, L_0x55ab20eea960, C4<0>, C4<0>;
+L_0x55ab20eeae60 .functor XOR 1, L_0x55ab20eeacb0, L_0x55ab20eeadc0, C4<0>, C4<0>;
+v0x55ab20cec020_0 .net *"_ivl_0", 0 0, L_0x55ab20eea8c0; 1 drivers
+v0x55ab20cec100_0 .net *"_ivl_1", 0 0, L_0x55ab20eea960; 1 drivers
+v0x55ab20ce8590_0 .net *"_ivl_2", 0 0, L_0x55ab20eeacb0; 1 drivers
+v0x55ab20ce8650_0 .net *"_ivl_6", 0 0, L_0x55ab20eeadc0; 1 drivers
+v0x55ab20ce9350_0 .net *"_ivl_7", 0 0, L_0x55ab20eeae60; 1 drivers
+L_0x55ab20eeadc0 .part L_0x55ab20ee8010, 12, 1;
+S_0x55ab20ce58c0 .scope generate, "genblk9[7]" "genblk9[7]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20ce6680 .param/l "i" 0 2 171, +C4<0111>;
+L_0x55ab20eeb370 .functor XOR 1, L_0x55ab20eeaf70, L_0x55ab20eeb010, C4<0>, C4<0>;
+L_0x55ab20eeb520 .functor XOR 1, L_0x55ab20eeb370, L_0x55ab20eeb480, C4<0>, C4<0>;
+v0x55ab20ce6740_0 .net *"_ivl_0", 0 0, L_0x55ab20eeaf70; 1 drivers
+v0x55ab20ce2bf0_0 .net *"_ivl_1", 0 0, L_0x55ab20eeb010; 1 drivers
+v0x55ab20ce2cd0_0 .net *"_ivl_2", 0 0, L_0x55ab20eeb370; 1 drivers
+v0x55ab20ce39b0_0 .net *"_ivl_6", 0 0, L_0x55ab20eeb480; 1 drivers
+v0x55ab20ce3a90_0 .net *"_ivl_7", 0 0, L_0x55ab20eeb520; 1 drivers
+L_0x55ab20eeb480 .part L_0x55ab20ee8010, 14, 1;
+S_0x55ab20ce0ce0 .scope generate, "genblk9[8]" "genblk9[8]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20ce0000 .param/l "i" 0 2 171, +C4<01000>;
+L_0x55ab20eeba40 .functor XOR 1, L_0x55ab20eeb630, L_0x55ab20eeb6d0, C4<0>, C4<0>;
+L_0x55ab20eebbf0 .functor XOR 1, L_0x55ab20eeba40, L_0x55ab20eebb50, C4<0>, C4<0>;
+v0x55ab20cdd270_0 .net *"_ivl_0", 0 0, L_0x55ab20eeb630; 1 drivers
+v0x55ab20cdd350_0 .net *"_ivl_1", 0 0, L_0x55ab20eeb6d0; 1 drivers
+v0x55ab20cde050_0 .net *"_ivl_2", 0 0, L_0x55ab20eeba40; 1 drivers
+v0x55ab20cde110_0 .net *"_ivl_6", 0 0, L_0x55ab20eebb50; 1 drivers
+v0x55ab20cda5c0_0 .net *"_ivl_7", 0 0, L_0x55ab20eebbf0; 1 drivers
+L_0x55ab20eebb50 .part L_0x55ab20ee8010, 16, 1;
+S_0x55ab20cdb340 .scope generate, "genblk9[9]" "genblk9[9]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20cd7920 .param/l "i" 0 2 171, +C4<01001>;
+L_0x55ab20eec120 .functor XOR 1, L_0x55ab20eebd00, L_0x55ab20eebda0, C4<0>, C4<0>;
+L_0x55ab20eec2d0 .functor XOR 1, L_0x55ab20eec120, L_0x55ab20eec230, C4<0>, C4<0>;
+v0x55ab20cd8670_0 .net *"_ivl_0", 0 0, L_0x55ab20eebd00; 1 drivers
+v0x55ab20cd8750_0 .net *"_ivl_1", 0 0, L_0x55ab20eebda0; 1 drivers
+v0x55ab20cd4be0_0 .net *"_ivl_2", 0 0, L_0x55ab20eec120; 1 drivers
+v0x55ab20cd4ca0_0 .net *"_ivl_6", 0 0, L_0x55ab20eec230; 1 drivers
+v0x55ab20cd59a0_0 .net *"_ivl_7", 0 0, L_0x55ab20eec2d0; 1 drivers
+L_0x55ab20eec230 .part L_0x55ab20ee8010, 18, 1;
+S_0x55ab20cd1f10 .scope generate, "genblk9[10]" "genblk9[10]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20cd5af0 .param/l "i" 0 2 171, +C4<01010>;
+L_0x55ab20eec810 .functor XOR 1, L_0x55ab20eec3e0, L_0x55ab20eec480, C4<0>, C4<0>;
+L_0x55ab20eec9c0 .functor XOR 1, L_0x55ab20eec810, L_0x55ab20eec920, C4<0>, C4<0>;
+v0x55ab20cd2d60_0 .net *"_ivl_0", 0 0, L_0x55ab20eec3e0; 1 drivers
+v0x55ab20ccf240_0 .net *"_ivl_1", 0 0, L_0x55ab20eec480; 1 drivers
+v0x55ab20ccf320_0 .net *"_ivl_2", 0 0, L_0x55ab20eec810; 1 drivers
+v0x55ab20cd0000_0 .net *"_ivl_6", 0 0, L_0x55ab20eec920; 1 drivers
+v0x55ab20cd00e0_0 .net *"_ivl_7", 0 0, L_0x55ab20eec9c0; 1 drivers
+L_0x55ab20eec920 .part L_0x55ab20ee8010, 20, 1;
+S_0x55ab20ccd270 .scope generate, "genblk9[11]" "genblk9[11]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20ccc590 .param/l "i" 0 2 171, +C4<01011>;
+L_0x55ab20eecf10 .functor XOR 1, L_0x55ab20eecad0, L_0x55ab20eecb70, C4<0>, C4<0>;
+L_0x55ab20eed0c0 .functor XOR 1, L_0x55ab20eecf10, L_0x55ab20eed020, C4<0>, C4<0>;
+v0x55ab20d9d1e0_0 .net *"_ivl_0", 0 0, L_0x55ab20eecad0; 1 drivers
+v0x55ab20d9d2c0_0 .net *"_ivl_1", 0 0, L_0x55ab20eecb70; 1 drivers
+v0x55ab20e2a7f0_0 .net *"_ivl_2", 0 0, L_0x55ab20eecf10; 1 drivers
+v0x55ab20e2a8b0_0 .net *"_ivl_6", 0 0, L_0x55ab20eed020; 1 drivers
+v0x55ab20e297d0_0 .net *"_ivl_7", 0 0, L_0x55ab20eed0c0; 1 drivers
+L_0x55ab20eed020 .part L_0x55ab20ee8010, 22, 1;
+S_0x55ab20e27de0 .scope generate, "genblk9[12]" "genblk9[12]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20e263f0 .param/l "i" 0 2 171, +C4<01100>;
+L_0x55ab20eed620 .functor XOR 1, L_0x55ab20eed1d0, L_0x55ab20eed270, C4<0>, C4<0>;
+L_0x55ab20eed7d0 .functor XOR 1, L_0x55ab20eed620, L_0x55ab20eed730, C4<0>, C4<0>;
+v0x55ab20e264d0_0 .net *"_ivl_0", 0 0, L_0x55ab20eed1d0; 1 drivers
+v0x55ab20e24ac0_0 .net *"_ivl_1", 0 0, L_0x55ab20eed270; 1 drivers
+v0x55ab20e24ba0_0 .net *"_ivl_2", 0 0, L_0x55ab20eed620; 1 drivers
+v0x55ab20e230f0_0 .net *"_ivl_6", 0 0, L_0x55ab20eed730; 1 drivers
+v0x55ab20e231d0_0 .net *"_ivl_7", 0 0, L_0x55ab20eed7d0; 1 drivers
+L_0x55ab20eed730 .part L_0x55ab20ee8010, 24, 1;
+S_0x55ab20e21720 .scope generate, "genblk9[13]" "genblk9[13]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20e1fdc0 .param/l "i" 0 2 171, +C4<01101>;
+L_0x55ab20eee560 .functor XOR 1, L_0x55ab20eed8e0, L_0x55ab20eedd90, C4<0>, C4<0>;
+L_0x55ab20eee710 .functor XOR 1, L_0x55ab20eee560, L_0x55ab20eee670, C4<0>, C4<0>;
+v0x55ab20e1e380_0 .net *"_ivl_0", 0 0, L_0x55ab20eed8e0; 1 drivers
+v0x55ab20e1e460_0 .net *"_ivl_1", 0 0, L_0x55ab20eedd90; 1 drivers
+v0x55ab20e1c9b0_0 .net *"_ivl_2", 0 0, L_0x55ab20eee560; 1 drivers
+v0x55ab20e1ca70_0 .net *"_ivl_6", 0 0, L_0x55ab20eee670; 1 drivers
+v0x55ab20e1afe0_0 .net *"_ivl_7", 0 0, L_0x55ab20eee710; 1 drivers
+L_0x55ab20eee670 .part L_0x55ab20ee8010, 26, 1;
+S_0x55ab20e19610 .scope generate, "genblk9[14]" "genblk9[14]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20e1b110 .param/l "i" 0 2 171, +C4<01110>;
+L_0x55ab20eeec90 .functor XOR 1, L_0x55ab20eee820, L_0x55ab20eee8c0, C4<0>, C4<0>;
+L_0x55ab20eeee40 .functor XOR 1, L_0x55ab20eeec90, L_0x55ab20eeeda0, C4<0>, C4<0>;
+v0x55ab20e17c40_0 .net *"_ivl_0", 0 0, L_0x55ab20eee820; 1 drivers
+v0x55ab20e17d40_0 .net *"_ivl_1", 0 0, L_0x55ab20eee8c0; 1 drivers
+v0x55ab20e16270_0 .net *"_ivl_2", 0 0, L_0x55ab20eeec90; 1 drivers
+v0x55ab20e16330_0 .net *"_ivl_6", 0 0, L_0x55ab20eeeda0; 1 drivers
+v0x55ab20e148a0_0 .net *"_ivl_7", 0 0, L_0x55ab20eeee40; 1 drivers
+L_0x55ab20eeeda0 .part L_0x55ab20ee8010, 28, 1;
+S_0x55ab20cfcc20 .scope generate, "genblk9[15]" "genblk9[15]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20e149d0 .param/l "i" 0 2 171, +C4<01111>;
+L_0x55ab20eef3d0 .functor XOR 1, L_0x55ab20eeef50, L_0x55ab20eeeff0, C4<0>, C4<0>;
+L_0x55ab20eef580 .functor XOR 1, L_0x55ab20eef3d0, L_0x55ab20eef4e0, C4<0>, C4<0>;
+v0x55ab20cfe5c0_0 .net *"_ivl_0", 0 0, L_0x55ab20eeef50; 1 drivers
+v0x55ab20cfe6a0_0 .net *"_ivl_1", 0 0, L_0x55ab20eeeff0; 1 drivers
+v0x55ab20d1acc0_0 .net *"_ivl_2", 0 0, L_0x55ab20eef3d0; 1 drivers
+v0x55ab20d1ad80_0 .net *"_ivl_6", 0 0, L_0x55ab20eef4e0; 1 drivers
+v0x55ab20d1ae60_0 .net *"_ivl_7", 0 0, L_0x55ab20eef580; 1 drivers
+L_0x55ab20eef4e0 .part L_0x55ab20ee8010, 30, 1;
+S_0x55ab20d1ea90 .scope generate, "genblk9[16]" "genblk9[16]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20d22970 .param/l "i" 0 2 171, +C4<010000>;
+L_0x55ab20eefb20 .functor XOR 1, L_0x55ab20eef690, L_0x55ab20eef730, C4<0>, C4<0>;
+L_0x55ab20eefd00 .functor XOR 1, L_0x55ab20eefb20, L_0x55ab20eefc60, C4<0>, C4<0>;
+v0x55ab20d26630_0 .net *"_ivl_0", 0 0, L_0x55ab20eef690; 1 drivers
+v0x55ab20d26710_0 .net *"_ivl_1", 0 0, L_0x55ab20eef730; 1 drivers
+v0x55ab20d2a400_0 .net *"_ivl_2", 0 0, L_0x55ab20eefb20; 1 drivers
+v0x55ab20d2a4c0_0 .net *"_ivl_6", 0 0, L_0x55ab20eefc60; 1 drivers
+v0x55ab20d2a5a0_0 .net *"_ivl_7", 0 0, L_0x55ab20eefd00; 1 drivers
+L_0x55ab20eefc60 .part L_0x55ab20ee8010, 32, 1;
+S_0x55ab20d2e1d0 .scope generate, "genblk9[17]" "genblk9[17]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20d1ec70 .param/l "i" 0 2 171, +C4<010001>;
+L_0x55ab20ef02b0 .functor XOR 1, L_0x55ab20eefe10, L_0x55ab20eefeb0, C4<0>, C4<0>;
+L_0x55ab20ef0490 .functor XOR 1, L_0x55ab20ef02b0, L_0x55ab20ef03f0, C4<0>, C4<0>;
+v0x55ab20d31fa0_0 .net *"_ivl_0", 0 0, L_0x55ab20eefe10; 1 drivers
+v0x55ab20d32080_0 .net *"_ivl_1", 0 0, L_0x55ab20eefeb0; 1 drivers
+v0x55ab20d35d70_0 .net *"_ivl_2", 0 0, L_0x55ab20ef02b0; 1 drivers
+v0x55ab20d35e30_0 .net *"_ivl_6", 0 0, L_0x55ab20ef03f0; 1 drivers
+v0x55ab20d35f10_0 .net *"_ivl_7", 0 0, L_0x55ab20ef0490; 1 drivers
+L_0x55ab20ef03f0 .part L_0x55ab20ee8010, 34, 1;
+S_0x55ab20d39b10 .scope generate, "genblk9[18]" "genblk9[18]" 2 171, 2 171 0, S_0x55ab20e31180;
+ .timescale 0 0;
+P_0x55ab20d3d870 .param/l "i" 0 2 171, +C4<010010>;
+L_0x55ab20ef1140 .functor XOR 1, L_0x55ab20ef0c90, L_0x55ab20ef10a0, C4<0>, C4<0>;
+L_0x55ab20ef12f0 .functor XOR 1, L_0x55ab20ef1140, L_0x55ab20ef1250, C4<0>, C4<0>;
+v0x55ab20d3d930_0 .net *"_ivl_0", 0 0, L_0x55ab20ef0c90; 1 drivers
+v0x55ab20d3da10_0 .net *"_ivl_1", 0 0, L_0x55ab20ef10a0; 1 drivers
+v0x55ab20d41630_0 .net *"_ivl_2", 0 0, L_0x55ab20ef1140; 1 drivers
+v0x55ab20d416f0_0 .net *"_ivl_6", 0 0, L_0x55ab20ef1250; 1 drivers
+v0x55ab20d45370_0 .net *"_ivl_7", 0 0, L_0x55ab20ef12f0; 1 drivers
+L_0x55ab20ef1250 .part L_0x55ab20ee8010, 36, 1;
+S_0x55ab20d490f0 .scope generate, "ha_fa" "ha_fa" 2 149, 2 149 0, S_0x55ab20d54e20;
+ .timescale 0 0;
+S_0x55ab20d4ce70 .scope generate, "genblk2[1]" "genblk2[1]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20d417d0 .param/l "i" 0 2 150, +C4<01>;
+v0x55ab20da15c0_0 .net *"_ivl_0", 0 0, L_0x55ab20e9a780; 1 drivers
+v0x55ab20da1680_0 .net *"_ivl_1", 0 0, L_0x55ab20e9a820; 1 drivers
+L_0x55ab20e9a8f0 .concat [ 1 1 0 0], L_0x55ab20e9a820, L_0x55ab20e9a780;
+S_0x55ab20d50bf0 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d4ce70;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9a3b0 .functor XOR 1, L_0x55ab20e9a220, L_0x55ab20e9a2c0, C4<0>, C4<0>;
+L_0x55ab20e9a6c0 .functor AND 1, L_0x55ab20e9a4c0, L_0x55ab20e9a560, C4<1>, C4<1>;
+v0x55ab20d54970_0 .net *"_ivl_1", 0 0, L_0x55ab20e9a220; 1 drivers
+v0x55ab20d54a70_0 .net *"_ivl_3", 0 0, L_0x55ab20e9a2c0; 1 drivers
+v0x55ab20d58700_0 .net *"_ivl_7", 0 0, L_0x55ab20e9a4c0; 1 drivers
+v0x55ab20d587c0_0 .net *"_ivl_9", 0 0, L_0x55ab20e9a560; 1 drivers
+v0x55ab20d588a0_0 .net "carry", 0 0, L_0x55ab20e9a6c0; 1 drivers
+v0x55ab20d5c470_0 .net "sum", 0 0, L_0x55ab20e9a3b0; 1 drivers
+v0x55ab20d5c530_0 .net "x", 1 0, L_0x55ab20e9a8f0; 1 drivers
+L_0x55ab20e9a220 .part L_0x55ab20e9a8f0, 1, 1;
+L_0x55ab20e9a2c0 .part L_0x55ab20e9a8f0, 0, 1;
+L_0x55ab20e9a4c0 .part L_0x55ab20e9a8f0, 1, 1;
+L_0x55ab20e9a560 .part L_0x55ab20e9a8f0, 0, 1;
+S_0x55ab20da5240 .scope generate, "genblk2[2]" "genblk2[2]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20da1760 .param/l "i" 0 2 150, +C4<010>;
+v0x55ab20db8570_0 .net *"_ivl_0", 0 0, L_0x55ab20e9afc0; 1 drivers
+v0x55ab20db8630_0 .net *"_ivl_1", 0 0, L_0x55ab20e9b0b0; 1 drivers
+L_0x55ab20e9b1d0 .concat [ 1 1 0 0], L_0x55ab20e9b0b0, L_0x55ab20e9afc0;
+S_0x55ab20da8fb0 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20da5240;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9abf0 .functor XOR 1, L_0x55ab20e9aa30, L_0x55ab20e9aad0, C4<0>, C4<0>;
+L_0x55ab20e9af00 .functor AND 1, L_0x55ab20e9ad00, L_0x55ab20e9ada0, C4<1>, C4<1>;
+v0x55ab20dacd70_0 .net *"_ivl_1", 0 0, L_0x55ab20e9aa30; 1 drivers
+v0x55ab20dace70_0 .net *"_ivl_3", 0 0, L_0x55ab20e9aad0; 1 drivers
+v0x55ab20db0a90_0 .net *"_ivl_7", 0 0, L_0x55ab20e9ad00; 1 drivers
+v0x55ab20db0b50_0 .net *"_ivl_9", 0 0, L_0x55ab20e9ada0; 1 drivers
+v0x55ab20db0c30_0 .net "carry", 0 0, L_0x55ab20e9af00; 1 drivers
+v0x55ab20db4870_0 .net "sum", 0 0, L_0x55ab20e9abf0; 1 drivers
+v0x55ab20db4930_0 .net "x", 1 0, L_0x55ab20e9b1d0; 1 drivers
+L_0x55ab20e9aa30 .part L_0x55ab20e9b1d0, 1, 1;
+L_0x55ab20e9aad0 .part L_0x55ab20e9b1d0, 0, 1;
+L_0x55ab20e9ad00 .part L_0x55ab20e9b1d0, 1, 1;
+L_0x55ab20e9ada0 .part L_0x55ab20e9b1d0, 0, 1;
+S_0x55ab20dbc2e0 .scope generate, "genblk2[3]" "genblk2[3]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20db8710 .param/l "i" 0 2 150, +C4<011>;
+v0x55ab20dcf610_0 .net *"_ivl_0", 0 0, L_0x55ab20e9b870; 1 drivers
+v0x55ab20dcf6f0_0 .net *"_ivl_1", 0 0, L_0x55ab20e9b910; 1 drivers
+L_0x55ab20e9b9f0 .concat [ 1 1 0 0], L_0x55ab20e9b910, L_0x55ab20e9b870;
+S_0x55ab20dc0050 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20dbc2e0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9b4a0 .functor XOR 1, L_0x55ab20e9b310, L_0x55ab20e9b3b0, C4<0>, C4<0>;
+L_0x55ab20e9b7b0 .functor AND 1, L_0x55ab20e9b5b0, L_0x55ab20e9b650, C4<1>, C4<1>;
+v0x55ab20dc3dc0_0 .net *"_ivl_1", 0 0, L_0x55ab20e9b310; 1 drivers
+v0x55ab20dc3ec0_0 .net *"_ivl_3", 0 0, L_0x55ab20e9b3b0; 1 drivers
+v0x55ab20dc7b30_0 .net *"_ivl_7", 0 0, L_0x55ab20e9b5b0; 1 drivers
+v0x55ab20dc7bf0_0 .net *"_ivl_9", 0 0, L_0x55ab20e9b650; 1 drivers
+v0x55ab20dc7cd0_0 .net "carry", 0 0, L_0x55ab20e9b7b0; 1 drivers
+v0x55ab20dcb8a0_0 .net "sum", 0 0, L_0x55ab20e9b4a0; 1 drivers
+v0x55ab20dcb940_0 .net "x", 1 0, L_0x55ab20e9b9f0; 1 drivers
+L_0x55ab20e9b310 .part L_0x55ab20e9b9f0, 1, 1;
+L_0x55ab20e9b3b0 .part L_0x55ab20e9b9f0, 0, 1;
+L_0x55ab20e9b5b0 .part L_0x55ab20e9b9f0, 1, 1;
+L_0x55ab20e9b650 .part L_0x55ab20e9b9f0, 0, 1;
+S_0x55ab20dd3380 .scope generate, "genblk2[4]" "genblk2[4]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20dcf7d0 .param/l "i" 0 2 150, +C4<0100>;
+v0x55ab20de65b0_0 .net *"_ivl_0", 0 0, L_0x55ab20e9c0c0; 1 drivers
+v0x55ab20de6670_0 .net *"_ivl_1", 0 0, L_0x55ab20e9c1f0; 1 drivers
+L_0x55ab20e9c370 .concat [ 1 1 0 0], L_0x55ab20e9c1f0, L_0x55ab20e9c0c0;
+S_0x55ab20dd7180 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20dd3380;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9bcc0 .functor XOR 1, L_0x55ab20e9bb30, L_0x55ab20e9bbd0, C4<0>, C4<0>;
+L_0x55ab20e9bfd0 .functor AND 1, L_0x55ab20e9bdd0, L_0x55ab20e9be70, C4<1>, C4<1>;
+v0x55ab20ddaef0_0 .net *"_ivl_1", 0 0, L_0x55ab20e9bb30; 1 drivers
+v0x55ab20ddaff0_0 .net *"_ivl_3", 0 0, L_0x55ab20e9bbd0; 1 drivers
+v0x55ab20ddead0_0 .net *"_ivl_7", 0 0, L_0x55ab20e9bdd0; 1 drivers
+v0x55ab20ddeb90_0 .net *"_ivl_9", 0 0, L_0x55ab20e9be70; 1 drivers
+v0x55ab20ddec70_0 .net "carry", 0 0, L_0x55ab20e9bfd0; 1 drivers
+v0x55ab20de28b0_0 .net "sum", 0 0, L_0x55ab20e9bcc0; 1 drivers
+v0x55ab20de2970_0 .net "x", 1 0, L_0x55ab20e9c370; 1 drivers
+L_0x55ab20e9bb30 .part L_0x55ab20e9c370, 1, 1;
+L_0x55ab20e9bbd0 .part L_0x55ab20e9c370, 0, 1;
+L_0x55ab20e9bdd0 .part L_0x55ab20e9c370, 1, 1;
+L_0x55ab20e9be70 .part L_0x55ab20e9c370, 0, 1;
+S_0x55ab20dea320 .scope generate, "genblk2[5]" "genblk2[5]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20de67a0 .param/l "i" 0 2 150, +C4<0101>;
+v0x55ab20dfd6b0_0 .net *"_ivl_0", 0 0, L_0x55ab20e9c9d0; 1 drivers
+v0x55ab20dfd790_0 .net *"_ivl_1", 0 0, L_0x55ab20e9ca70; 1 drivers
+L_0x55ab20e9cb70 .concat [ 1 1 0 0], L_0x55ab20e9ca70, L_0x55ab20e9c9d0;
+S_0x55ab20dee120 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20dea320;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9c5d0 .functor XOR 1, L_0x55ab20e9c410, L_0x55ab20e9c4b0, C4<0>, C4<0>;
+L_0x55ab20e9c8e0 .functor AND 1, L_0x55ab20e9c6e0, L_0x55ab20e9c780, C4<1>, C4<1>;
+v0x55ab20df1ea0_0 .net *"_ivl_1", 0 0, L_0x55ab20e9c410; 1 drivers
+v0x55ab20df1fa0_0 .net *"_ivl_3", 0 0, L_0x55ab20e9c4b0; 1 drivers
+v0x55ab20df5b70_0 .net *"_ivl_7", 0 0, L_0x55ab20e9c6e0; 1 drivers
+v0x55ab20df5c30_0 .net *"_ivl_9", 0 0, L_0x55ab20e9c780; 1 drivers
+v0x55ab20df5d10_0 .net "carry", 0 0, L_0x55ab20e9c8e0; 1 drivers
+v0x55ab20df9950_0 .net "sum", 0 0, L_0x55ab20e9c5d0; 1 drivers
+v0x55ab20df9a10_0 .net "x", 1 0, L_0x55ab20e9cb70; 1 drivers
+L_0x55ab20e9c410 .part L_0x55ab20e9cb70, 1, 1;
+L_0x55ab20e9c4b0 .part L_0x55ab20e9cb70, 0, 1;
+L_0x55ab20e9c6e0 .part L_0x55ab20e9cb70, 1, 1;
+L_0x55ab20e9c780 .part L_0x55ab20e9cb70, 0, 1;
+S_0x55ab20e013c0 .scope generate, "genblk2[6]" "genblk2[6]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20e015a0 .param/l "i" 0 2 150, +C4<0110>;
+v0x55ab20e0d320_0 .net *"_ivl_0", 0 0, L_0x55ab20e9d220; 1 drivers
+v0x55ab20d9dcb0_0 .net *"_ivl_1", 0 0, L_0x55ab20e9d2c0; 1 drivers
+L_0x55ab20e9d3d0 .concat [ 1 1 0 0], L_0x55ab20e9d2c0, L_0x55ab20e9d220;
+S_0x55ab20dd7a90 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20e013c0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9ce20 .functor XOR 1, L_0x55ab20e9cc60, L_0x55ab20e9cd00, C4<0>, C4<0>;
+L_0x55ab20e9d130 .functor AND 1, L_0x55ab20e9cf30, L_0x55ab20e9cfd0, C4<1>, C4<1>;
+v0x55ab20e091f0_0 .net *"_ivl_1", 0 0, L_0x55ab20e9cc60; 1 drivers
+v0x55ab20e092f0_0 .net *"_ivl_3", 0 0, L_0x55ab20e9cd00; 1 drivers
+v0x55ab20e09430_0 .net *"_ivl_7", 0 0, L_0x55ab20e9cf30; 1 drivers
+v0x55ab20e094f0_0 .net *"_ivl_9", 0 0, L_0x55ab20e9cfd0; 1 drivers
+v0x55ab20e0cf20_0 .net "carry", 0 0, L_0x55ab20e9d130; 1 drivers
+v0x55ab20e0d030_0 .net "sum", 0 0, L_0x55ab20e9ce20; 1 drivers
+v0x55ab20e0d1c0_0 .net "x", 1 0, L_0x55ab20e9d3d0; 1 drivers
+L_0x55ab20e9cc60 .part L_0x55ab20e9d3d0, 1, 1;
+L_0x55ab20e9cd00 .part L_0x55ab20e9d3d0, 0, 1;
+L_0x55ab20e9cf30 .part L_0x55ab20e9d3d0, 1, 1;
+L_0x55ab20e9cfd0 .part L_0x55ab20e9d3d0, 0, 1;
+S_0x55ab20d99fe0 .scope generate, "genblk2[7]" "genblk2[7]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20e095d0 .param/l "i" 0 2 150, +C4<0111>;
+v0x55ab20d8ab10_0 .net *"_ivl_0", 0 0, L_0x55ab20e9daa0; 1 drivers
+v0x55ab20d86c40_0 .net *"_ivl_1", 0 0, L_0x55ab20e9db40; 1 drivers
+L_0x55ab20e9dc60 .concat [ 1 1 0 0], L_0x55ab20e9db40, L_0x55ab20e9daa0;
+S_0x55ab20d96270 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d99fe0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9d6d0 .functor XOR 1, L_0x55ab20e9d510, L_0x55ab20e9d5b0, C4<0>, C4<0>;
+L_0x55ab20e9d9e0 .functor AND 1, L_0x55ab20e9d7e0, L_0x55ab20e9d880, C4<1>, C4<1>;
+v0x55ab20d9dd90_0 .net *"_ivl_1", 0 0, L_0x55ab20e9d510; 1 drivers
+v0x55ab20d92490_0 .net *"_ivl_3", 0 0, L_0x55ab20e9d5b0; 1 drivers
+v0x55ab20d92570_0 .net *"_ivl_7", 0 0, L_0x55ab20e9d7e0; 1 drivers
+v0x55ab20d92630_0 .net *"_ivl_9", 0 0, L_0x55ab20e9d880; 1 drivers
+v0x55ab20d8e720_0 .net "carry", 0 0, L_0x55ab20e9d9e0; 1 drivers
+v0x55ab20d8e830_0 .net "sum", 0 0, L_0x55ab20e9d6d0; 1 drivers
+v0x55ab20d8a9b0_0 .net "x", 1 0, L_0x55ab20e9dc60; 1 drivers
+L_0x55ab20e9d510 .part L_0x55ab20e9dc60, 1, 1;
+L_0x55ab20e9d5b0 .part L_0x55ab20e9dc60, 0, 1;
+L_0x55ab20e9d7e0 .part L_0x55ab20e9dc60, 1, 1;
+L_0x55ab20e9d880 .part L_0x55ab20e9dc60, 0, 1;
+S_0x55ab20d86d00 .scope generate, "genblk2[8]" "genblk2[8]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20d8e8f0 .param/l "i" 0 2 150, +C4<01000>;
+v0x55ab20d73980_0 .net *"_ivl_0", 0 0, L_0x55ab20e9e2f0; 1 drivers
+v0x55ab20d73a40_0 .net *"_ivl_1", 0 0, L_0x55ab20e9e4a0; 1 drivers
+L_0x55ab20e9e6e0 .concat [ 1 1 0 0], L_0x55ab20e9e4a0, L_0x55ab20e9e2f0;
+S_0x55ab20d82f60 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d86d00;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9d360 .functor XOR 1, L_0x55ab20e9dda0, L_0x55ab20e9de40, C4<0>, C4<0>;
+L_0x55ab20e9e200 .functor AND 1, L_0x55ab20e9e000, L_0x55ab20e9e0a0, C4<1>, C4<1>;
+v0x55ab20d7f220_0 .net *"_ivl_1", 0 0, L_0x55ab20e9dda0; 1 drivers
+v0x55ab20d7f320_0 .net *"_ivl_3", 0 0, L_0x55ab20e9de40; 1 drivers
+v0x55ab20d7b3f0_0 .net *"_ivl_7", 0 0, L_0x55ab20e9e000; 1 drivers
+v0x55ab20d7b4b0_0 .net *"_ivl_9", 0 0, L_0x55ab20e9e0a0; 1 drivers
+v0x55ab20d7b590_0 .net "carry", 0 0, L_0x55ab20e9e200; 1 drivers
+v0x55ab20d776d0_0 .net "sum", 0 0, L_0x55ab20e9d360; 1 drivers
+v0x55ab20d77790_0 .net "x", 1 0, L_0x55ab20e9e6e0; 1 drivers
+L_0x55ab20e9dda0 .part L_0x55ab20e9e6e0, 1, 1;
+L_0x55ab20e9de40 .part L_0x55ab20e9e6e0, 0, 1;
+L_0x55ab20e9e000 .part L_0x55ab20e9e6e0, 1, 1;
+L_0x55ab20e9e0a0 .part L_0x55ab20e9e6e0, 0, 1;
+S_0x55ab20d6fc10 .scope generate, "genblk2[9]" "genblk2[9]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20de6750 .param/l "i" 0 2 150, +C4<01001>;
+v0x55ab20d5cb70_0 .net *"_ivl_0", 0 0, L_0x55ab20e9ed50; 1 drivers
+v0x55ab20d5cc50_0 .net *"_ivl_1", 0 0, L_0x55ab20e9edf0; 1 drivers
+L_0x55ab20e9ef30 .concat [ 1 1 0 0], L_0x55ab20e9edf0, L_0x55ab20e9ed50;
+S_0x55ab20d6bea0 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d6fc10;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9e9e0 .functor XOR 1, L_0x55ab20e9e820, L_0x55ab20e9e8c0, C4<0>, C4<0>;
+L_0x55ab20e9ec60 .functor AND 1, L_0x55ab20e9eaf0, L_0x55ab20e9eb90, C4<1>, C4<1>;
+v0x55ab20d68130_0 .net *"_ivl_1", 0 0, L_0x55ab20e9e820; 1 drivers
+v0x55ab20d68230_0 .net *"_ivl_3", 0 0, L_0x55ab20e9e8c0; 1 drivers
+v0x55ab20d643c0_0 .net *"_ivl_7", 0 0, L_0x55ab20e9eaf0; 1 drivers
+v0x55ab20d64480_0 .net *"_ivl_9", 0 0, L_0x55ab20e9eb90; 1 drivers
+v0x55ab20d64560_0 .net "carry", 0 0, L_0x55ab20e9ec60; 1 drivers
+v0x55ab20d60790_0 .net "sum", 0 0, L_0x55ab20e9e9e0; 1 drivers
+v0x55ab20d60850_0 .net "x", 1 0, L_0x55ab20e9ef30; 1 drivers
+L_0x55ab20e9e820 .part L_0x55ab20e9ef30, 1, 1;
+L_0x55ab20e9e8c0 .part L_0x55ab20e9ef30, 0, 1;
+L_0x55ab20e9eaf0 .part L_0x55ab20e9ef30, 1, 1;
+L_0x55ab20e9eb90 .part L_0x55ab20e9ef30, 0, 1;
+S_0x55ab20d58e00 .scope generate, "genblk2[10]" "genblk2[10]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20d59000 .param/l "i" 0 2 150, +C4<01010>;
+v0x55ab20d41ce0_0 .net *"_ivl_0", 0 0, L_0x55ab20e9f5a0; 1 drivers
+v0x55ab20d41dc0_0 .net *"_ivl_1", 0 0, L_0x55ab20e9f640; 1 drivers
+L_0x55ab20e9ee90 .concat [ 1 1 0 0], L_0x55ab20e9f640, L_0x55ab20e9f5a0;
+S_0x55ab20d512e0 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d58e00;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9f230 .functor XOR 1, L_0x55ab20e9f070, L_0x55ab20e9f110, C4<0>, C4<0>;
+L_0x55ab20e9f4b0 .functor AND 1, L_0x55ab20e9f340, L_0x55ab20e9f3e0, C4<1>, C4<1>;
+v0x55ab20d4d560_0 .net *"_ivl_1", 0 0, L_0x55ab20e9f070; 1 drivers
+v0x55ab20d4d660_0 .net *"_ivl_3", 0 0, L_0x55ab20e9f110; 1 drivers
+v0x55ab20d497e0_0 .net *"_ivl_7", 0 0, L_0x55ab20e9f340; 1 drivers
+v0x55ab20d498a0_0 .net *"_ivl_9", 0 0, L_0x55ab20e9f3e0; 1 drivers
+v0x55ab20d49980_0 .net "carry", 0 0, L_0x55ab20e9f4b0; 1 drivers
+v0x55ab20d45a60_0 .net "sum", 0 0, L_0x55ab20e9f230; 1 drivers
+v0x55ab20d45b20_0 .net "x", 1 0, L_0x55ab20e9ee90; 1 drivers
+L_0x55ab20e9f070 .part L_0x55ab20e9ee90, 1, 1;
+L_0x55ab20e9f110 .part L_0x55ab20e9ee90, 0, 1;
+L_0x55ab20e9f340 .part L_0x55ab20e9ee90, 1, 1;
+L_0x55ab20e9f3e0 .part L_0x55ab20e9ee90, 0, 1;
+S_0x55ab20d3df60 .scope generate, "genblk2[11]" "genblk2[11]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20d3e160 .param/l "i" 0 2 150, +C4<01011>;
+v0x55ab20d2acd0_0 .net *"_ivl_0", 0 0, L_0x55ab20e9fd60; 1 drivers
+v0x55ab20d26da0_0 .net *"_ivl_1", 0 0, L_0x55ab20e9fe00; 1 drivers
+L_0x55ab20e9ff60 .concat [ 1 1 0 0], L_0x55ab20e9fe00, L_0x55ab20e9fd60;
+S_0x55ab20d3a1e0 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d3df60;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20e9f9f0 .functor XOR 1, L_0x55ab20e9f830, L_0x55ab20e9f8d0, C4<0>, C4<0>;
+L_0x55ab20e9fc70 .functor AND 1, L_0x55ab20e9fb00, L_0x55ab20e9fba0, C4<1>, C4<1>;
+v0x55ab20d41ea0_0 .net *"_ivl_1", 0 0, L_0x55ab20e9f830; 1 drivers
+v0x55ab20d36460_0 .net *"_ivl_3", 0 0, L_0x55ab20e9f8d0; 1 drivers
+v0x55ab20d36520_0 .net *"_ivl_7", 0 0, L_0x55ab20e9fb00; 1 drivers
+v0x55ab20d365e0_0 .net *"_ivl_9", 0 0, L_0x55ab20e9fba0; 1 drivers
+v0x55ab20d2e940_0 .net "carry", 0 0, L_0x55ab20e9fc70; 1 drivers
+v0x55ab20d2ea50_0 .net "sum", 0 0, L_0x55ab20e9f9f0; 1 drivers
+v0x55ab20d2ab70_0 .net "x", 1 0, L_0x55ab20e9ff60; 1 drivers
+L_0x55ab20e9f830 .part L_0x55ab20e9ff60, 1, 1;
+L_0x55ab20e9f8d0 .part L_0x55ab20e9ff60, 0, 1;
+L_0x55ab20e9fb00 .part L_0x55ab20e9ff60, 1, 1;
+L_0x55ab20e9fba0 .part L_0x55ab20e9ff60, 0, 1;
+S_0x55ab20d26e60 .scope generate, "genblk2[12]" "genblk2[12]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20d22fd0 .param/l "i" 0 2 150, +C4<01100>;
+v0x55ab20d168c0_0 .net *"_ivl_0", 0 0, L_0x55ab20ea0660; 1 drivers
+v0x55ab20d169a0_0 .net *"_ivl_1", 0 0, L_0x55ab20ea0700; 1 drivers
+L_0x55ab20ea0870 .concat [ 1 1 0 0], L_0x55ab20ea0700, L_0x55ab20ea0660;
+S_0x55ab20d23090 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d26e60;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20ea0260 .functor XOR 1, L_0x55ab20ea00a0, L_0x55ab20ea0140, C4<0>, C4<0>;
+L_0x55ab20ea0570 .functor AND 1, L_0x55ab20ea0370, L_0x55ab20ea0410, C4<1>, C4<1>;
+v0x55ab20d1f2c0_0 .net *"_ivl_1", 0 0, L_0x55ab20ea00a0; 1 drivers
+v0x55ab20d1f3c0_0 .net *"_ivl_3", 0 0, L_0x55ab20ea0140; 1 drivers
+v0x55ab20d1b470_0 .net *"_ivl_7", 0 0, L_0x55ab20ea0370; 1 drivers
+v0x55ab20d1b530_0 .net *"_ivl_9", 0 0, L_0x55ab20ea0410; 1 drivers
+v0x55ab20d550d0_0 .net "carry", 0 0, L_0x55ab20ea0570; 1 drivers
+v0x55ab20d551e0_0 .net "sum", 0 0, L_0x55ab20ea0260; 1 drivers
+v0x55ab20d552a0_0 .net "x", 1 0, L_0x55ab20ea0870; 1 drivers
+L_0x55ab20ea00a0 .part L_0x55ab20ea0870, 1, 1;
+L_0x55ab20ea0140 .part L_0x55ab20ea0870, 0, 1;
+L_0x55ab20ea0370 .part L_0x55ab20ea0870, 1, 1;
+L_0x55ab20ea0410 .part L_0x55ab20ea0870, 0, 1;
+S_0x55ab20d15050 .scope generate, "genblk2[13]" "genblk2[13]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20d15250 .param/l "i" 0 2 150, +C4<01101>;
+v0x55ab20d0d730_0 .net *"_ivl_0", 0 0, L_0x55ab20ea0f70; 1 drivers
+v0x55ab20d0d810_0 .net *"_ivl_1", 0 0, L_0x55ab20ea1010; 1 drivers
+L_0x55ab20ea1190 .concat [ 1 1 0 0], L_0x55ab20ea1010, L_0x55ab20ea0f70;
+S_0x55ab20d13820 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d15050;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20ea0b70 .functor XOR 1, L_0x55ab20ea09b0, L_0x55ab20ea0a50, C4<0>, C4<0>;
+L_0x55ab20ea0e80 .functor AND 1, L_0x55ab20ea0c80, L_0x55ab20ea0d20, C4<1>, C4<1>;
+v0x55ab20d11fc0_0 .net *"_ivl_1", 0 0, L_0x55ab20ea09b0; 1 drivers
+v0x55ab20d120c0_0 .net *"_ivl_3", 0 0, L_0x55ab20ea0a50; 1 drivers
+v0x55ab20d121a0_0 .net *"_ivl_7", 0 0, L_0x55ab20ea0c80; 1 drivers
+v0x55ab20d107b0_0 .net *"_ivl_9", 0 0, L_0x55ab20ea0d20; 1 drivers
+v0x55ab20d10890_0 .net "carry", 0 0, L_0x55ab20ea0e80; 1 drivers
+v0x55ab20d0ef60_0 .net "sum", 0 0, L_0x55ab20ea0b70; 1 drivers
+v0x55ab20d0f020_0 .net "x", 1 0, L_0x55ab20ea1190; 1 drivers
+L_0x55ab20ea09b0 .part L_0x55ab20ea1190, 1, 1;
+L_0x55ab20ea0a50 .part L_0x55ab20ea1190, 0, 1;
+L_0x55ab20ea0c80 .part L_0x55ab20ea1190, 1, 1;
+L_0x55ab20ea0d20 .part L_0x55ab20ea1190, 0, 1;
+S_0x55ab20d0bf00 .scope generate, "genblk2[14]" "genblk2[14]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20d0c100 .param/l "i" 0 2 150, +C4<01110>;
+v0x55ab20d05ee0_0 .net *"_ivl_0", 0 0, L_0x55ab20ea1890; 1 drivers
+v0x55ab20d05fc0_0 .net *"_ivl_1", 0 0, L_0x55ab20ea1930; 1 drivers
+L_0x55ab20ea1ac0 .concat [ 1 1 0 0], L_0x55ab20ea1930, L_0x55ab20ea1890;
+S_0x55ab20d0a6d0 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d0bf00;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20ea1490 .functor XOR 1, L_0x55ab20ea12d0, L_0x55ab20ea1370, C4<0>, C4<0>;
+L_0x55ab20ea17a0 .functor AND 1, L_0x55ab20ea15a0, L_0x55ab20ea1640, C4<1>, C4<1>;
+v0x55ab20d0d8f0_0 .net *"_ivl_1", 0 0, L_0x55ab20ea12d0; 1 drivers
+v0x55ab20d08ea0_0 .net *"_ivl_3", 0 0, L_0x55ab20ea1370; 1 drivers
+v0x55ab20d08f60_0 .net *"_ivl_7", 0 0, L_0x55ab20ea15a0; 1 drivers
+v0x55ab20d09020_0 .net *"_ivl_9", 0 0, L_0x55ab20ea1640; 1 drivers
+v0x55ab20d07670_0 .net "carry", 0 0, L_0x55ab20ea17a0; 1 drivers
+v0x55ab20d07760_0 .net "sum", 0 0, L_0x55ab20ea1490; 1 drivers
+v0x55ab20d07820_0 .net "x", 1 0, L_0x55ab20ea1ac0; 1 drivers
+L_0x55ab20ea12d0 .part L_0x55ab20ea1ac0, 1, 1;
+L_0x55ab20ea1370 .part L_0x55ab20ea1ac0, 0, 1;
+L_0x55ab20ea15a0 .part L_0x55ab20ea1ac0, 1, 1;
+L_0x55ab20ea1640 .part L_0x55ab20ea1ac0, 0, 1;
+S_0x55ab20d04610 .scope generate, "genblk2[15]" "genblk2[15]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20d047f0 .param/l "i" 0 2 150, +C4<01111>;
+v0x55ab20d32910_0 .net *"_ivl_0", 0 0, L_0x55ab20ea21c0; 1 drivers
+v0x55ab20d602e0_0 .net *"_ivl_1", 0 0, L_0x55ab20ea2260; 1 drivers
+L_0x55ab20ea2400 .concat [ 1 1 0 0], L_0x55ab20ea2260, L_0x55ab20ea21c0;
+S_0x55ab20d02e20 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d04610;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20ea1dc0 .functor XOR 1, L_0x55ab20ea1c00, L_0x55ab20ea1ca0, C4<0>, C4<0>;
+L_0x55ab20ea20d0 .functor AND 1, L_0x55ab20ea1ed0, L_0x55ab20ea1f70, C4<1>, C4<1>;
+v0x55ab20d01600_0 .net *"_ivl_1", 0 0, L_0x55ab20ea1c00; 1 drivers
+v0x55ab20d01700_0 .net *"_ivl_3", 0 0, L_0x55ab20ea1ca0; 1 drivers
+v0x55ab20cffd80_0 .net *"_ivl_7", 0 0, L_0x55ab20ea1ed0; 1 drivers
+v0x55ab20cffe40_0 .net *"_ivl_9", 0 0, L_0x55ab20ea1f70; 1 drivers
+v0x55ab20cfff20_0 .net "carry", 0 0, L_0x55ab20ea20d0; 1 drivers
+v0x55ab20d32710_0 .net "sum", 0 0, L_0x55ab20ea1dc0; 1 drivers
+v0x55ab20d327b0_0 .net "x", 1 0, L_0x55ab20ea2400; 1 drivers
+L_0x55ab20ea1c00 .part L_0x55ab20ea2400, 1, 1;
+L_0x55ab20ea1ca0 .part L_0x55ab20ea2400, 0, 1;
+L_0x55ab20ea1ed0 .part L_0x55ab20ea2400, 1, 1;
+L_0x55ab20ea1f70 .part L_0x55ab20ea2400, 0, 1;
+S_0x55ab20d603c0 .scope generate, "genblk2[16]" "genblk2[16]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20d605c0 .param/l "i" 0 2 150, +C4<010000>;
+v0x55ab20d6f760_0 .net *"_ivl_0", 0 0, L_0x55ab20ea2ad0; 1 drivers
+v0x55ab20d6f840_0 .net *"_ivl_1", 0 0, L_0x55ab20ea2d80; 1 drivers
+L_0x55ab20ea3140 .concat [ 1 1 0 0], L_0x55ab20ea2d80, L_0x55ab20ea2ad0;
+S_0x55ab20d63fa0 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d603c0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20ea2700 .functor XOR 1, L_0x55ab20ea2540, L_0x55ab20ea25e0, C4<0>, C4<0>;
+L_0x55ab20ea2a10 .functor AND 1, L_0x55ab20ea2810, L_0x55ab20ea28b0, C4<1>, C4<1>;
+v0x55ab20d67c80_0 .net *"_ivl_1", 0 0, L_0x55ab20ea2540; 1 drivers
+v0x55ab20d67d80_0 .net *"_ivl_3", 0 0, L_0x55ab20ea25e0; 1 drivers
+v0x55ab20d67e60_0 .net *"_ivl_7", 0 0, L_0x55ab20ea2810; 1 drivers
+v0x55ab20d67f20_0 .net *"_ivl_9", 0 0, L_0x55ab20ea28b0; 1 drivers
+v0x55ab20d6b9f0_0 .net "carry", 0 0, L_0x55ab20ea2a10; 1 drivers
+v0x55ab20d6bb00_0 .net "sum", 0 0, L_0x55ab20ea2700; 1 drivers
+v0x55ab20d6bbc0_0 .net "x", 1 0, L_0x55ab20ea3140; 1 drivers
+L_0x55ab20ea2540 .part L_0x55ab20ea3140, 1, 1;
+L_0x55ab20ea25e0 .part L_0x55ab20ea3140, 0, 1;
+L_0x55ab20ea2810 .part L_0x55ab20ea3140, 1, 1;
+L_0x55ab20ea28b0 .part L_0x55ab20ea3140, 0, 1;
+S_0x55ab20d6f920 .scope generate, "genblk2[17]" "genblk2[17]" 2 150, 2 150 0, S_0x55ab20d490f0;
+ .timescale 0 0;
+P_0x55ab20d735e0 .param/l "i" 0 2 150, +C4<010001>;
+v0x55ab20da1a00_0 .net *"_ivl_0", 0 0, L_0x55ab20ea37e0; 1 drivers
+v0x55ab20da1ae0_0 .net *"_ivl_1", 0 0, L_0x55ab20ea3880; 1 drivers
+L_0x55ab20ea3a40 .concat [ 1 1 0 0], L_0x55ab20ea3880, L_0x55ab20ea37e0;
+S_0x55ab20d95dc0 .scope module, "t0" "halfadd" 2 151, 2 214 0, S_0x55ab20d6f920;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "x";
+ .port_info 1 /OUTPUT 1 "sum";
+ .port_info 2 /OUTPUT 1 "carry";
+L_0x55ab20ea3410 .functor XOR 1, L_0x55ab20ea3280, L_0x55ab20ea3320, C4<0>, C4<0>;
+L_0x55ab20ea3720 .functor AND 1, L_0x55ab20ea3520, L_0x55ab20ea35c0, C4<1>, C4<1>;
+v0x55ab20d96010_0 .net *"_ivl_1", 0 0, L_0x55ab20ea3280; 1 drivers
+v0x55ab20d736c0_0 .net *"_ivl_3", 0 0, L_0x55ab20ea3320; 1 drivers
+v0x55ab20d99b30_0 .net *"_ivl_7", 0 0, L_0x55ab20ea3520; 1 drivers
+v0x55ab20d99bf0_0 .net *"_ivl_9", 0 0, L_0x55ab20ea35c0; 1 drivers
+v0x55ab20d99cd0_0 .net "carry", 0 0, L_0x55ab20ea3720; 1 drivers
+v0x55ab20d99de0_0 .net "sum", 0 0, L_0x55ab20ea3410; 1 drivers
+v0x55ab20da18a0_0 .net "x", 1 0, L_0x55ab20ea3a40; 1 drivers
+L_0x55ab20ea3280 .part L_0x55ab20ea3a40, 1, 1;
+L_0x55ab20ea3320 .part L_0x55ab20ea3a40, 0, 1;
+L_0x55ab20ea3520 .part L_0x55ab20ea3a40, 1, 1;
+L_0x55ab20ea35c0 .part L_0x55ab20ea3a40, 0, 1;
+S_0x55ab20da5520 .scope generate, "kgp_gen" "kgp_gen" 2 155, 2 155 0, S_0x55ab20d54e20;
+ .timescale 0 0;
+S_0x55ab20da9290 .scope generate, "genblk4[0]" "genblk4[0]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20da9490 .param/l "i" 0 2 156, +C4<00>;
+S_0x55ab20dad000 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20da9290;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea3b80 .functor OR 1, L_0x55ab20ea3e70, L_0x55ab20ea3f10, C4<0>, C4<0>;
+L_0x55ab20ea3d10 .functor AND 1, L_0x55ab20ea3e70, L_0x55ab20ea3f10, C4<1>, C4<1>;
+v0x55ab20dad250_0 .net *"_ivl_2", 0 0, L_0x55ab20ea3b80; 1 drivers
+v0x55ab20da5700_0 .net *"_ivl_7", 0 0, L_0x55ab20ea3d10; 1 drivers
+v0x55ab20da57e0_0 .net "a", 0 0, L_0x55ab20ea3e70; 1 drivers
+v0x55ab20db0d70_0 .net "b", 0 0, L_0x55ab20ea3f10; 1 drivers
+v0x55ab20db0e30_0 .net "y", 1 0, L_0x55ab20ea3bf0; 1 drivers
+L_0x55ab20ea3bf0 .concat8 [ 1 1 0 0], L_0x55ab20ea3b80, L_0x55ab20ea3d10;
+S_0x55ab20db4ae0 .scope generate, "genblk4[1]" "genblk4[1]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20db4ce0 .param/l "i" 0 2 156, +C4<01>;
+S_0x55ab20db8850 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20db4ae0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea3920 .functor OR 1, L_0x55ab20ea4330, L_0x55ab20ea4420, C4<0>, C4<0>;
+L_0x55ab20ea41d0 .functor AND 1, L_0x55ab20ea4330, L_0x55ab20ea4420, C4<1>, C4<1>;
+v0x55ab20db4da0_0 .net *"_ivl_2", 0 0, L_0x55ab20ea3920; 1 drivers
+v0x55ab20db8b00_0 .net *"_ivl_7", 0 0, L_0x55ab20ea41d0; 1 drivers
+v0x55ab20db0fe0_0 .net "a", 0 0, L_0x55ab20ea4330; 1 drivers
+v0x55ab20dbc5c0_0 .net "b", 0 0, L_0x55ab20ea4420; 1 drivers
+v0x55ab20dbc680_0 .net "y", 1 0, L_0x55ab20ea40e0; 1 drivers
+L_0x55ab20ea40e0 .concat8 [ 1 1 0 0], L_0x55ab20ea3920, L_0x55ab20ea41d0;
+S_0x55ab20dc40a0 .scope generate, "genblk4[2]" "genblk4[2]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20dc4280 .param/l "i" 0 2 156, +C4<010>;
+S_0x55ab20dc7e10 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20dc40a0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea4650 .functor OR 1, L_0x55ab20ea4910, L_0x55ab20ea49b0, C4<0>, C4<0>;
+L_0x55ab20ea47b0 .functor AND 1, L_0x55ab20ea4910, L_0x55ab20ea49b0, C4<1>, C4<1>;
+v0x55ab20dc8060_0 .net *"_ivl_2", 0 0, L_0x55ab20ea4650; 1 drivers
+v0x55ab20dc4340_0 .net *"_ivl_7", 0 0, L_0x55ab20ea47b0; 1 drivers
+v0x55ab20dbc7e0_0 .net "a", 0 0, L_0x55ab20ea4910; 1 drivers
+v0x55ab20dbc880_0 .net "b", 0 0, L_0x55ab20ea49b0; 1 drivers
+v0x55ab20dcbb80_0 .net "y", 1 0, L_0x55ab20ea46c0; 1 drivers
+L_0x55ab20ea46c0 .concat8 [ 1 1 0 0], L_0x55ab20ea4650, L_0x55ab20ea47b0;
+S_0x55ab20dcbd30 .scope generate, "genblk4[3]" "genblk4[3]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20dcf8f0 .param/l "i" 0 2 156, +C4<011>;
+S_0x55ab20dcf9b0 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20dcbd30;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea4ba0 .functor OR 1, L_0x55ab20ea4e60, L_0x55ab20ea4f90, C4<0>, C4<0>;
+L_0x55ab20ea4d00 .functor AND 1, L_0x55ab20ea4e60, L_0x55ab20ea4f90, C4<1>, C4<1>;
+v0x55ab20dd3660_0 .net *"_ivl_2", 0 0, L_0x55ab20ea4ba0; 1 drivers
+v0x55ab20dd3760_0 .net *"_ivl_7", 0 0, L_0x55ab20ea4d00; 1 drivers
+v0x55ab20dd3840_0 .net "a", 0 0, L_0x55ab20ea4e60; 1 drivers
+v0x55ab20dd38e0_0 .net "b", 0 0, L_0x55ab20ea4f90; 1 drivers
+v0x55ab20dd73d0_0 .net "y", 1 0, L_0x55ab20ea4c10; 1 drivers
+L_0x55ab20ea4c10 .concat8 [ 1 1 0 0], L_0x55ab20ea4ba0, L_0x55ab20ea4d00;
+S_0x55ab20dd7510 .scope generate, "genblk4[4]" "genblk4[4]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20ddb180 .param/l "i" 0 2 156, +C4<0100>;
+S_0x55ab20ddb260 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20dd7510;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea5220 .functor OR 1, L_0x55ab20ea5440, L_0x55ab20ea54e0, C4<0>, C4<0>;
+L_0x55ab20ea5330 .functor AND 1, L_0x55ab20ea5440, L_0x55ab20ea54e0, C4<1>, C4<1>;
+v0x55ab20ddee00_0 .net *"_ivl_2", 0 0, L_0x55ab20ea5220; 1 drivers
+v0x55ab20ddef00_0 .net *"_ivl_7", 0 0, L_0x55ab20ea5330; 1 drivers
+v0x55ab20ddefe0_0 .net "a", 0 0, L_0x55ab20ea5440; 1 drivers
+v0x55ab20de2b20_0 .net "b", 0 0, L_0x55ab20ea54e0; 1 drivers
+v0x55ab20de2be0_0 .net "y", 1 0, L_0x55ab20ea5290; 1 drivers
+L_0x55ab20ea5290 .concat8 [ 1 1 0 0], L_0x55ab20ea5220, L_0x55ab20ea5330;
+S_0x55ab20de6890 .scope generate, "genblk4[5]" "genblk4[5]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20de6a70 .param/l "i" 0 2 156, +C4<0101>;
+S_0x55ab20dea600 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20de6890;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea56f0 .functor OR 1, L_0x55ab20ea59e0, L_0x55ab20ea5a80, C4<0>, C4<0>;
+L_0x55ab20ea5880 .functor AND 1, L_0x55ab20ea59e0, L_0x55ab20ea5a80, C4<1>, C4<1>;
+v0x55ab20de6b50_0 .net *"_ivl_2", 0 0, L_0x55ab20ea56f0; 1 drivers
+v0x55ab20dea8b0_0 .net *"_ivl_7", 0 0, L_0x55ab20ea5880; 1 drivers
+v0x55ab20de2d90_0 .net "a", 0 0, L_0x55ab20ea59e0; 1 drivers
+v0x55ab20dee370_0 .net "b", 0 0, L_0x55ab20ea5a80; 1 drivers
+v0x55ab20dee430_0 .net "y", 1 0, L_0x55ab20ea5760; 1 drivers
+L_0x55ab20ea5760 .concat8 [ 1 1 0 0], L_0x55ab20ea56f0, L_0x55ab20ea5880;
+S_0x55ab20df20e0 .scope generate, "genblk4[6]" "genblk4[6]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20df22c0 .param/l "i" 0 2 156, +C4<0110>;
+S_0x55ab20df5e50 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20df20e0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea5ca0 .functor OR 1, L_0x55ab20ea5f90, L_0x55ab20ea6030, C4<0>, C4<0>;
+L_0x55ab20ea5e30 .functor AND 1, L_0x55ab20ea5f90, L_0x55ab20ea6030, C4<1>, C4<1>;
+v0x55ab20df23a0_0 .net *"_ivl_2", 0 0, L_0x55ab20ea5ca0; 1 drivers
+v0x55ab20df6100_0 .net *"_ivl_7", 0 0, L_0x55ab20ea5e30; 1 drivers
+v0x55ab20dee590_0 .net "a", 0 0, L_0x55ab20ea5f90; 1 drivers
+v0x55ab20dee630_0 .net "b", 0 0, L_0x55ab20ea6030; 1 drivers
+v0x55ab20df9bc0_0 .net "y", 1 0, L_0x55ab20ea5d10; 1 drivers
+L_0x55ab20ea5d10 .concat8 [ 1 1 0 0], L_0x55ab20ea5ca0, L_0x55ab20ea5e30;
+S_0x55ab20df9d50 .scope generate, "genblk4[7]" "genblk4[7]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20dfd930 .param/l "i" 0 2 156, +C4<0111>;
+S_0x55ab20dfda10 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20df9d50;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea6260 .functor OR 1, L_0x55ab20ea6520, L_0x55ab20ea65c0, C4<0>, C4<0>;
+L_0x55ab20ea63c0 .functor AND 1, L_0x55ab20ea6520, L_0x55ab20ea65c0, C4<1>, C4<1>;
+v0x55ab20e016a0_0 .net *"_ivl_2", 0 0, L_0x55ab20ea6260; 1 drivers
+v0x55ab20e017a0_0 .net *"_ivl_7", 0 0, L_0x55ab20ea63c0; 1 drivers
+v0x55ab20e01880_0 .net "a", 0 0, L_0x55ab20ea6520; 1 drivers
+v0x55ab20e01920_0 .net "b", 0 0, L_0x55ab20ea65c0; 1 drivers
+v0x55ab20d92050_0 .net "y", 1 0, L_0x55ab20ea62d0; 1 drivers
+L_0x55ab20ea62d0 .concat8 [ 1 1 0 0], L_0x55ab20ea6260, L_0x55ab20ea63c0;
+S_0x55ab20d92200 .scope generate, "genblk4[8]" "genblk4[8]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20ddb130 .param/l "i" 0 2 156, +C4<01000>;
+S_0x55ab20d8e370 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20d92200;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea6800 .functor OR 1, L_0x55ab20ea6af0, L_0x55ab20ea6b90, C4<0>, C4<0>;
+L_0x55ab20ea6990 .functor AND 1, L_0x55ab20ea6af0, L_0x55ab20ea6b90, C4<1>, C4<1>;
+v0x55ab20d8e5c0_0 .net *"_ivl_2", 0 0, L_0x55ab20ea6800; 1 drivers
+v0x55ab20d8a570_0 .net *"_ivl_7", 0 0, L_0x55ab20ea6990; 1 drivers
+v0x55ab20d8a630_0 .net "a", 0 0, L_0x55ab20ea6af0; 1 drivers
+v0x55ab20d8a6d0_0 .net "b", 0 0, L_0x55ab20ea6b90; 1 drivers
+v0x55ab20d8a790_0 .net "y", 1 0, L_0x55ab20ea6870; 1 drivers
+L_0x55ab20ea6870 .concat8 [ 1 1 0 0], L_0x55ab20ea6800, L_0x55ab20ea6990;
+S_0x55ab20d86800 .scope generate, "genblk4[9]" "genblk4[9]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20d869e0 .param/l "i" 0 2 156, +C4<01001>;
+S_0x55ab20d82a90 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20d86800;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea6660 .functor OR 1, L_0x55ab20ea6f40, L_0x55ab20ea6fe0, C4<0>, C4<0>;
+L_0x55ab20ea6de0 .functor AND 1, L_0x55ab20ea6f40, L_0x55ab20ea6fe0, C4<1>, C4<1>;
+v0x55ab20d82ce0_0 .net *"_ivl_2", 0 0, L_0x55ab20ea6660; 1 drivers
+v0x55ab20d86ac0_0 .net *"_ivl_7", 0 0, L_0x55ab20ea6de0; 1 drivers
+v0x55ab20d7ed20_0 .net "a", 0 0, L_0x55ab20ea6f40; 1 drivers
+v0x55ab20d7edc0_0 .net "b", 0 0, L_0x55ab20ea6fe0; 1 drivers
+v0x55ab20d7ee80_0 .net "y", 1 0, L_0x55ab20ea66d0; 1 drivers
+L_0x55ab20ea66d0 .concat8 [ 1 1 0 0], L_0x55ab20ea6660, L_0x55ab20ea6de0;
+S_0x55ab20d7afb0 .scope generate, "genblk4[10]" "genblk4[10]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20d7b190 .param/l "i" 0 2 156, +C4<01010>;
+S_0x55ab20d77240 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20d7afb0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea7240 .functor OR 1, L_0x55ab20ea7530, L_0x55ab20ea75d0, C4<0>, C4<0>;
+L_0x55ab20ea73d0 .functor AND 1, L_0x55ab20ea7530, L_0x55ab20ea75d0, C4<1>, C4<1>;
+v0x55ab20d77490_0 .net *"_ivl_2", 0 0, L_0x55ab20ea7240; 1 drivers
+v0x55ab20d7b270_0 .net *"_ivl_7", 0 0, L_0x55ab20ea73d0; 1 drivers
+v0x55ab20dc0330_0 .net "a", 0 0, L_0x55ab20ea7530; 1 drivers
+v0x55ab20dc03d0_0 .net "b", 0 0, L_0x55ab20ea75d0; 1 drivers
+v0x55ab20dc0490_0 .net "y", 1 0, L_0x55ab20ea72b0; 1 drivers
+L_0x55ab20ea72b0 .concat8 [ 1 1 0 0], L_0x55ab20ea7240, L_0x55ab20ea73d0;
+S_0x55ab20c50f00 .scope generate, "genblk4[11]" "genblk4[11]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20c510e0 .param/l "i" 0 2 156, +C4<01011>;
+S_0x55ab20e054f0 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20c50f00;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea7840 .functor OR 1, L_0x55ab20ea7b30, L_0x55ab20ea7bd0, C4<0>, C4<0>;
+L_0x55ab20ea79d0 .functor AND 1, L_0x55ab20ea7b30, L_0x55ab20ea7bd0, C4<1>, C4<1>;
+v0x55ab20e05740_0 .net *"_ivl_2", 0 0, L_0x55ab20ea7840; 1 drivers
+v0x55ab20e05840_0 .net *"_ivl_7", 0 0, L_0x55ab20ea79d0; 1 drivers
+v0x55ab20dc0640_0 .net "a", 0 0, L_0x55ab20ea7b30; 1 drivers
+v0x55ab20c511c0_0 .net "b", 0 0, L_0x55ab20ea7bd0; 1 drivers
+v0x55ab20c51280_0 .net "y", 1 0, L_0x55ab20ea78b0; 1 drivers
+L_0x55ab20ea78b0 .concat8 [ 1 1 0 0], L_0x55ab20ea7840, L_0x55ab20ea79d0;
+S_0x55ab20c4f8b0 .scope generate, "genblk4[12]" "genblk4[12]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20c4fa90 .param/l "i" 0 2 156, +C4<01100>;
+S_0x55ab20c4fb70 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20c4f8b0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea7e50 .functor OR 1, L_0x55ab20ea8140, L_0x55ab20ea81e0, C4<0>, C4<0>;
+L_0x55ab20ea7fe0 .functor AND 1, L_0x55ab20ea8140, L_0x55ab20ea81e0, C4<1>, C4<1>;
+v0x55ab20c4b2f0_0 .net *"_ivl_2", 0 0, L_0x55ab20ea7e50; 1 drivers
+v0x55ab20c4b3f0_0 .net *"_ivl_7", 0 0, L_0x55ab20ea7fe0; 1 drivers
+v0x55ab20c4b4d0_0 .net "a", 0 0, L_0x55ab20ea8140; 1 drivers
+v0x55ab20c4b570_0 .net "b", 0 0, L_0x55ab20ea81e0; 1 drivers
+v0x55ab20c4b630_0 .net "y", 1 0, L_0x55ab20ea7ec0; 1 drivers
+L_0x55ab20ea7ec0 .concat8 [ 1 1 0 0], L_0x55ab20ea7e50, L_0x55ab20ea7fe0;
+S_0x55ab20c4c8b0 .scope generate, "genblk4[13]" "genblk4[13]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20c4ca90 .param/l "i" 0 2 156, +C4<01101>;
+S_0x55ab20bffcf0 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20c4c8b0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea8470 .functor OR 1, L_0x55ab20ea8760, L_0x55ab20ea8800, C4<0>, C4<0>;
+L_0x55ab20ea8600 .functor AND 1, L_0x55ab20ea8760, L_0x55ab20ea8800, C4<1>, C4<1>;
+v0x55ab20bfff40_0 .net *"_ivl_2", 0 0, L_0x55ab20ea8470; 1 drivers
+v0x55ab20c00040_0 .net *"_ivl_7", 0 0, L_0x55ab20ea8600; 1 drivers
+v0x55ab20c4cb70_0 .net "a", 0 0, L_0x55ab20ea8760; 1 drivers
+v0x55ab20c3d5c0_0 .net "b", 0 0, L_0x55ab20ea8800; 1 drivers
+v0x55ab20c3d680_0 .net "y", 1 0, L_0x55ab20ea84e0; 1 drivers
+L_0x55ab20ea84e0 .concat8 [ 1 1 0 0], L_0x55ab20ea8470, L_0x55ab20ea8600;
+S_0x55ab20c3d830 .scope generate, "genblk4[14]" "genblk4[14]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20c4cc10 .param/l "i" 0 2 156, +C4<01110>;
+S_0x55ab20e32cf0 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20c3d830;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea8aa0 .functor OR 1, L_0x55ab20ea8d90, L_0x55ab20ea8e30, C4<0>, C4<0>;
+L_0x55ab20ea8c30 .functor AND 1, L_0x55ab20ea8d90, L_0x55ab20ea8e30, C4<1>, C4<1>;
+v0x55ab20e32ed0_0 .net *"_ivl_2", 0 0, L_0x55ab20ea8aa0; 1 drivers
+v0x55ab20e32f90_0 .net *"_ivl_7", 0 0, L_0x55ab20ea8c30; 1 drivers
+v0x55ab20e33070_0 .net "a", 0 0, L_0x55ab20ea8d90; 1 drivers
+v0x55ab20e33110_0 .net "b", 0 0, L_0x55ab20ea8e30; 1 drivers
+v0x55ab20e331d0_0 .net "y", 1 0, L_0x55ab20ea8b10; 1 drivers
+L_0x55ab20ea8b10 .concat8 [ 1 1 0 0], L_0x55ab20ea8aa0, L_0x55ab20ea8c30;
+S_0x55ab20e33380 .scope generate, "genblk4[15]" "genblk4[15]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20e33580 .param/l "i" 0 2 156, +C4<01111>;
+S_0x55ab20e33660 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20e33380;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea90e0 .functor OR 1, L_0x55ab20ea93d0, L_0x55ab20ea9680, C4<0>, C4<0>;
+L_0x55ab20ea9270 .functor AND 1, L_0x55ab20ea93d0, L_0x55ab20ea9680, C4<1>, C4<1>;
+v0x55ab20e338b0_0 .net *"_ivl_2", 0 0, L_0x55ab20ea90e0; 1 drivers
+v0x55ab20e339b0_0 .net *"_ivl_7", 0 0, L_0x55ab20ea9270; 1 drivers
+v0x55ab20e33a90_0 .net "a", 0 0, L_0x55ab20ea93d0; 1 drivers
+v0x55ab20e33b30_0 .net "b", 0 0, L_0x55ab20ea9680; 1 drivers
+v0x55ab20e33bf0_0 .net "y", 1 0, L_0x55ab20ea9150; 1 drivers
+L_0x55ab20ea9150 .concat8 [ 1 1 0 0], L_0x55ab20ea90e0, L_0x55ab20ea9270;
+S_0x55ab20e33da0 .scope generate, "genblk4[16]" "genblk4[16]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20e34090 .param/l "i" 0 2 156, +C4<010000>;
+S_0x55ab20e34170 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20e33da0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ea9b50 .functor OR 1, L_0x55ab20ea9e40, L_0x55ab20ea9ee0, C4<0>, C4<0>;
+L_0x55ab20ea9ce0 .functor AND 1, L_0x55ab20ea9e40, L_0x55ab20ea9ee0, C4<1>, C4<1>;
+v0x55ab20e343c0_0 .net *"_ivl_2", 0 0, L_0x55ab20ea9b50; 1 drivers
+v0x55ab20e344c0_0 .net *"_ivl_7", 0 0, L_0x55ab20ea9ce0; 1 drivers
+v0x55ab20e345a0_0 .net "a", 0 0, L_0x55ab20ea9e40; 1 drivers
+v0x55ab20e34640_0 .net "b", 0 0, L_0x55ab20ea9ee0; 1 drivers
+v0x55ab20e34700_0 .net "y", 1 0, L_0x55ab20ea9bc0; 1 drivers
+L_0x55ab20ea9bc0 .concat8 [ 1 1 0 0], L_0x55ab20ea9b50, L_0x55ab20ea9ce0;
+S_0x55ab20e348b0 .scope generate, "genblk4[17]" "genblk4[17]" 2 156, 2 156 0, S_0x55ab20da5520;
+ .timescale 0 0;
+P_0x55ab20e34a90 .param/l "i" 0 2 156, +C4<010001>;
+S_0x55ab20e34b70 .scope module, "t" "kgp" 2 157, 2 186 0, S_0x55ab20e348b0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "a";
+ .port_info 1 /INPUT 1 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eaa1b0 .functor OR 1, L_0x55ab20eaa470, L_0x55ab20eaa510, C4<0>, C4<0>;
+L_0x55ab20eaa310 .functor AND 1, L_0x55ab20eaa470, L_0x55ab20eaa510, C4<1>, C4<1>;
+v0x55ab20e34dc0_0 .net *"_ivl_2", 0 0, L_0x55ab20eaa1b0; 1 drivers
+v0x55ab20e34ec0_0 .net *"_ivl_7", 0 0, L_0x55ab20eaa310; 1 drivers
+v0x55ab20e34fa0_0 .net "a", 0 0, L_0x55ab20eaa470; 1 drivers
+v0x55ab20e35040_0 .net "b", 0 0, L_0x55ab20eaa510; 1 drivers
+v0x55ab20e35100_0 .net "y", 1 0, L_0x55ab20eaa220; 1 drivers
+L_0x55ab20eaa220 .concat8 [ 1 1 0 0], L_0x55ab20eaa1b0, L_0x55ab20eaa310;
+S_0x55ab20e352b0 .scope generate, "recursiveStg" "recursiveStg" 2 160, 2 160 0, S_0x55ab20d54e20;
+ .timescale 0 0;
+S_0x55ab20e35490 .scope generate, "genblk6[0]" "genblk6[0]" 2 161, 2 161 0, S_0x55ab20e352b0;
+ .timescale 0 0;
+P_0x55ab20e35690 .param/l "i" 0 2 161, +C4<00>;
+v0x55ab20e4b6f0_0 .net *"_ivl_5", 1 0, L_0x55ab20eaa7f0; 1 drivers
+L_0x55ab20eaa7f0 .part L_0x55ab20ef5480, 0, 2;
+S_0x55ab20e35770 .scope generate, "genblk7[2]" "genblk7[2]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e35970 .param/l "j" 0 2 164, +C4<010>;
+L_0x55ab20eab6a0 .part L_0x55ab20ef5480, 0, 2;
+L_0x55ab20eab790 .part L_0x55ab20ef5480, 2, 2;
+S_0x55ab20e35a50 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e35770;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eaa890 .functor NOT 1, L_0x55ab20eaa900, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eaa9f0 .functor AND 1, L_0x55ab20eaaaf0, L_0x55ab20eaac30, C4<1>, C4<1>;
+L_0x55ab20eaad20 .functor AND 1, L_0x55ab20eaa890, L_0x55ab20eaade0, L_0x55ab20eaaf00, C4<1>;
+L_0x55ab20eaafa0 .functor AND 1, L_0x55ab20eaa890, L_0x55ab20eab0d0, L_0x55ab20eab200, C4<1>;
+L_0x55ab20eab340 .functor OR 1, L_0x55ab20eaa9f0, L_0x55ab20eaad20, C4<0>, C4<0>;
+L_0x55ab20eab590 .functor OR 1, L_0x55ab20eaa9f0, L_0x55ab20eaafa0, C4<0>, C4<0>;
+v0x55ab20e35ca0_0 .net *"_ivl_1", 0 0, L_0x55ab20eaa900; 1 drivers
+v0x55ab20e35da0_0 .net *"_ivl_11", 0 0, L_0x55ab20eab0d0; 1 drivers
+v0x55ab20e35e80_0 .net *"_ivl_13", 0 0, L_0x55ab20eab200; 1 drivers
+v0x55ab20e35f40_0 .net *"_ivl_14", 0 0, L_0x55ab20eab340; 1 drivers
+v0x55ab20e36020_0 .net *"_ivl_16", 0 0, L_0x55ab20eab590; 1 drivers
+v0x55ab20e36150_0 .net *"_ivl_3", 0 0, L_0x55ab20eaaaf0; 1 drivers
+v0x55ab20e36230_0 .net *"_ivl_5", 0 0, L_0x55ab20eaac30; 1 drivers
+v0x55ab20e36310_0 .net *"_ivl_7", 0 0, L_0x55ab20eaade0; 1 drivers
+v0x55ab20e363f0_0 .net *"_ivl_9", 0 0, L_0x55ab20eaaf00; 1 drivers
+v0x55ab20e364d0_0 .net "a", 1 0, L_0x55ab20eab6a0; 1 drivers
+v0x55ab20e365b0_0 .net "b", 1 0, L_0x55ab20eab790; 1 drivers
+v0x55ab20e36690_0 .net "b0", 0 0, L_0x55ab20eaa890; 1 drivers
+v0x55ab20e36750_0 .net "f", 0 0, L_0x55ab20eaa9f0; 1 drivers
+v0x55ab20e36810_0 .net "g0", 0 0, L_0x55ab20eaad20; 1 drivers
+v0x55ab20e368d0_0 .net "g1", 0 0, L_0x55ab20eaafa0; 1 drivers
+v0x55ab20e36990_0 .net "y", 1 0, L_0x55ab20eab450; 1 drivers
+L_0x55ab20eaa900 .part L_0x55ab20eab790, 1, 1;
+L_0x55ab20eaaaf0 .part L_0x55ab20eab790, 0, 1;
+L_0x55ab20eaac30 .part L_0x55ab20eab790, 1, 1;
+L_0x55ab20eaade0 .part L_0x55ab20eab790, 0, 1;
+L_0x55ab20eaaf00 .part L_0x55ab20eab6a0, 0, 1;
+L_0x55ab20eab0d0 .part L_0x55ab20eab790, 0, 1;
+L_0x55ab20eab200 .part L_0x55ab20eab6a0, 1, 1;
+L_0x55ab20eab450 .concat8 [ 1 1 0 0], L_0x55ab20eab340, L_0x55ab20eab590;
+S_0x55ab20e36af0 .scope generate, "genblk7[4]" "genblk7[4]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e36ca0 .param/l "j" 0 2 164, +C4<0100>;
+L_0x55ab20eac520 .part L_0x55ab20ef5480, 2, 2;
+L_0x55ab20eac650 .part L_0x55ab20ef5480, 4, 2;
+S_0x55ab20e36d60 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e36af0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eab830 .functor NOT 1, L_0x55ab20eab8a0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eab990 .functor AND 1, L_0x55ab20eaba00, L_0x55ab20eabb40, C4<1>, C4<1>;
+L_0x55ab20eabc30 .functor AND 1, L_0x55ab20eab830, L_0x55ab20eabcf0, L_0x55ab20eabde0, C4<1>;
+L_0x55ab20eabe80 .functor AND 1, L_0x55ab20eab830, L_0x55ab20eabf50, L_0x55ab20eac080, C4<1>;
+L_0x55ab20eac1c0 .functor OR 1, L_0x55ab20eab990, L_0x55ab20eabc30, C4<0>, C4<0>;
+L_0x55ab20eac410 .functor OR 1, L_0x55ab20eab990, L_0x55ab20eabe80, C4<0>, C4<0>;
+v0x55ab20e36fb0_0 .net *"_ivl_1", 0 0, L_0x55ab20eab8a0; 1 drivers
+v0x55ab20e370b0_0 .net *"_ivl_11", 0 0, L_0x55ab20eabf50; 1 drivers
+v0x55ab20e37190_0 .net *"_ivl_13", 0 0, L_0x55ab20eac080; 1 drivers
+v0x55ab20e37250_0 .net *"_ivl_14", 0 0, L_0x55ab20eac1c0; 1 drivers
+v0x55ab20e37330_0 .net *"_ivl_16", 0 0, L_0x55ab20eac410; 1 drivers
+v0x55ab20e37460_0 .net *"_ivl_3", 0 0, L_0x55ab20eaba00; 1 drivers
+v0x55ab20e37540_0 .net *"_ivl_5", 0 0, L_0x55ab20eabb40; 1 drivers
+v0x55ab20e37620_0 .net *"_ivl_7", 0 0, L_0x55ab20eabcf0; 1 drivers
+v0x55ab20e37700_0 .net *"_ivl_9", 0 0, L_0x55ab20eabde0; 1 drivers
+v0x55ab20e377e0_0 .net "a", 1 0, L_0x55ab20eac520; 1 drivers
+v0x55ab20e378c0_0 .net "b", 1 0, L_0x55ab20eac650; 1 drivers
+v0x55ab20e379a0_0 .net "b0", 0 0, L_0x55ab20eab830; 1 drivers
+v0x55ab20e37a60_0 .net "f", 0 0, L_0x55ab20eab990; 1 drivers
+v0x55ab20e37b20_0 .net "g0", 0 0, L_0x55ab20eabc30; 1 drivers
+v0x55ab20e37be0_0 .net "g1", 0 0, L_0x55ab20eabe80; 1 drivers
+v0x55ab20e37ca0_0 .net "y", 1 0, L_0x55ab20eac2d0; 1 drivers
+L_0x55ab20eab8a0 .part L_0x55ab20eac650, 1, 1;
+L_0x55ab20eaba00 .part L_0x55ab20eac650, 0, 1;
+L_0x55ab20eabb40 .part L_0x55ab20eac650, 1, 1;
+L_0x55ab20eabcf0 .part L_0x55ab20eac650, 0, 1;
+L_0x55ab20eabde0 .part L_0x55ab20eac520, 0, 1;
+L_0x55ab20eabf50 .part L_0x55ab20eac650, 0, 1;
+L_0x55ab20eac080 .part L_0x55ab20eac520, 1, 1;
+L_0x55ab20eac2d0 .concat8 [ 1 1 0 0], L_0x55ab20eac1c0, L_0x55ab20eac410;
+S_0x55ab20e37e00 .scope generate, "genblk7[6]" "genblk7[6]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e37f90 .param/l "j" 0 2 164, +C4<0110>;
+L_0x55ab20ead450 .part L_0x55ab20ef5480, 4, 2;
+L_0x55ab20ead4f0 .part L_0x55ab20ef5480, 6, 2;
+S_0x55ab20e38050 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e37e00;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eac6f0 .functor NOT 1, L_0x55ab20eac760, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eac800 .functor AND 1, L_0x55ab20eac870, L_0x55ab20eac9b0, C4<1>, C4<1>;
+L_0x55ab20eacaa0 .functor AND 1, L_0x55ab20eac6f0, L_0x55ab20eacb60, L_0x55ab20eacd10, C4<1>;
+L_0x55ab20eacdb0 .functor AND 1, L_0x55ab20eac6f0, L_0x55ab20eace80, L_0x55ab20eacfb0, C4<1>;
+L_0x55ab20ead0f0 .functor OR 1, L_0x55ab20eac800, L_0x55ab20eacaa0, C4<0>, C4<0>;
+L_0x55ab20ead340 .functor OR 1, L_0x55ab20eac800, L_0x55ab20eacdb0, C4<0>, C4<0>;
+v0x55ab20e382a0_0 .net *"_ivl_1", 0 0, L_0x55ab20eac760; 1 drivers
+v0x55ab20e383a0_0 .net *"_ivl_11", 0 0, L_0x55ab20eace80; 1 drivers
+v0x55ab20e38480_0 .net *"_ivl_13", 0 0, L_0x55ab20eacfb0; 1 drivers
+v0x55ab20e38540_0 .net *"_ivl_14", 0 0, L_0x55ab20ead0f0; 1 drivers
+v0x55ab20e38620_0 .net *"_ivl_16", 0 0, L_0x55ab20ead340; 1 drivers
+v0x55ab20e38750_0 .net *"_ivl_3", 0 0, L_0x55ab20eac870; 1 drivers
+v0x55ab20e38830_0 .net *"_ivl_5", 0 0, L_0x55ab20eac9b0; 1 drivers
+v0x55ab20e38910_0 .net *"_ivl_7", 0 0, L_0x55ab20eacb60; 1 drivers
+v0x55ab20e389f0_0 .net *"_ivl_9", 0 0, L_0x55ab20eacd10; 1 drivers
+v0x55ab20e38ad0_0 .net "a", 1 0, L_0x55ab20ead450; 1 drivers
+v0x55ab20e38bb0_0 .net "b", 1 0, L_0x55ab20ead4f0; 1 drivers
+v0x55ab20e38c90_0 .net "b0", 0 0, L_0x55ab20eac6f0; 1 drivers
+v0x55ab20e38d50_0 .net "f", 0 0, L_0x55ab20eac800; 1 drivers
+v0x55ab20e38e10_0 .net "g0", 0 0, L_0x55ab20eacaa0; 1 drivers
+v0x55ab20e38ed0_0 .net "g1", 0 0, L_0x55ab20eacdb0; 1 drivers
+v0x55ab20e38f90_0 .net "y", 1 0, L_0x55ab20ead200; 1 drivers
+L_0x55ab20eac760 .part L_0x55ab20ead4f0, 1, 1;
+L_0x55ab20eac870 .part L_0x55ab20ead4f0, 0, 1;
+L_0x55ab20eac9b0 .part L_0x55ab20ead4f0, 1, 1;
+L_0x55ab20eacb60 .part L_0x55ab20ead4f0, 0, 1;
+L_0x55ab20eacd10 .part L_0x55ab20ead450, 0, 1;
+L_0x55ab20eace80 .part L_0x55ab20ead4f0, 0, 1;
+L_0x55ab20eacfb0 .part L_0x55ab20ead450, 1, 1;
+L_0x55ab20ead200 .concat8 [ 1 1 0 0], L_0x55ab20ead0f0, L_0x55ab20ead340;
+S_0x55ab20e390f0 .scope generate, "genblk7[8]" "genblk7[8]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e39280 .param/l "j" 0 2 164, +C4<01000>;
+L_0x55ab20eae340 .part L_0x55ab20ef5480, 6, 2;
+L_0x55ab20eae3e0 .part L_0x55ab20ef5480, 8, 2;
+S_0x55ab20e39360 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e390f0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ead590 .functor NOT 1, L_0x55ab20ead600, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ead6f0 .functor AND 1, L_0x55ab20ead760, L_0x55ab20ead8a0, C4<1>, C4<1>;
+L_0x55ab20ead990 .functor AND 1, L_0x55ab20ead590, L_0x55ab20eada50, L_0x55ab20eadc00, C4<1>;
+L_0x55ab20eadca0 .functor AND 1, L_0x55ab20ead590, L_0x55ab20eadd70, L_0x55ab20eadea0, C4<1>;
+L_0x55ab20eadfe0 .functor OR 1, L_0x55ab20ead6f0, L_0x55ab20ead990, C4<0>, C4<0>;
+L_0x55ab20eae230 .functor OR 1, L_0x55ab20ead6f0, L_0x55ab20eadca0, C4<0>, C4<0>;
+v0x55ab20e395b0_0 .net *"_ivl_1", 0 0, L_0x55ab20ead600; 1 drivers
+v0x55ab20e396b0_0 .net *"_ivl_11", 0 0, L_0x55ab20eadd70; 1 drivers
+v0x55ab20e39790_0 .net *"_ivl_13", 0 0, L_0x55ab20eadea0; 1 drivers
+v0x55ab20e39850_0 .net *"_ivl_14", 0 0, L_0x55ab20eadfe0; 1 drivers
+v0x55ab20e39930_0 .net *"_ivl_16", 0 0, L_0x55ab20eae230; 1 drivers
+v0x55ab20e39a60_0 .net *"_ivl_3", 0 0, L_0x55ab20ead760; 1 drivers
+v0x55ab20e39b40_0 .net *"_ivl_5", 0 0, L_0x55ab20ead8a0; 1 drivers
+v0x55ab20e39c20_0 .net *"_ivl_7", 0 0, L_0x55ab20eada50; 1 drivers
+v0x55ab20e39d00_0 .net *"_ivl_9", 0 0, L_0x55ab20eadc00; 1 drivers
+v0x55ab20e39de0_0 .net "a", 1 0, L_0x55ab20eae340; 1 drivers
+v0x55ab20e39ec0_0 .net "b", 1 0, L_0x55ab20eae3e0; 1 drivers
+v0x55ab20e39fa0_0 .net "b0", 0 0, L_0x55ab20ead590; 1 drivers
+v0x55ab20e3a060_0 .net "f", 0 0, L_0x55ab20ead6f0; 1 drivers
+v0x55ab20e3a120_0 .net "g0", 0 0, L_0x55ab20ead990; 1 drivers
+v0x55ab20e3a1e0_0 .net "g1", 0 0, L_0x55ab20eadca0; 1 drivers
+v0x55ab20e3a2a0_0 .net "y", 1 0, L_0x55ab20eae0f0; 1 drivers
+L_0x55ab20ead600 .part L_0x55ab20eae3e0, 1, 1;
+L_0x55ab20ead760 .part L_0x55ab20eae3e0, 0, 1;
+L_0x55ab20ead8a0 .part L_0x55ab20eae3e0, 1, 1;
+L_0x55ab20eada50 .part L_0x55ab20eae3e0, 0, 1;
+L_0x55ab20eadc00 .part L_0x55ab20eae340, 0, 1;
+L_0x55ab20eadd70 .part L_0x55ab20eae3e0, 0, 1;
+L_0x55ab20eadea0 .part L_0x55ab20eae340, 1, 1;
+L_0x55ab20eae0f0 .concat8 [ 1 1 0 0], L_0x55ab20eadfe0, L_0x55ab20eae230;
+S_0x55ab20e3a400 .scope generate, "genblk7[10]" "genblk7[10]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e3a5e0 .param/l "j" 0 2 164, +C4<01010>;
+L_0x55ab20eaf1a0 .part L_0x55ab20ef5480, 8, 2;
+L_0x55ab20eaf240 .part L_0x55ab20ef5480, 10, 2;
+S_0x55ab20e3a6c0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e3a400;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eae480 .functor NOT 1, L_0x55ab20eae4f0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eae5e0 .functor AND 1, L_0x55ab20eae650, L_0x55ab20eae790, C4<1>, C4<1>;
+L_0x55ab20eae880 .functor AND 1, L_0x55ab20eae480, L_0x55ab20eae940, L_0x55ab20eaea60, C4<1>;
+L_0x55ab20eaeb00 .functor AND 1, L_0x55ab20eae480, L_0x55ab20eaebd0, L_0x55ab20eaed00, C4<1>;
+L_0x55ab20eaee40 .functor OR 1, L_0x55ab20eae5e0, L_0x55ab20eae880, C4<0>, C4<0>;
+L_0x55ab20eaf090 .functor OR 1, L_0x55ab20eae5e0, L_0x55ab20eaeb00, C4<0>, C4<0>;
+v0x55ab20e3a910_0 .net *"_ivl_1", 0 0, L_0x55ab20eae4f0; 1 drivers
+v0x55ab20e3aa10_0 .net *"_ivl_11", 0 0, L_0x55ab20eaebd0; 1 drivers
+v0x55ab20e3aaf0_0 .net *"_ivl_13", 0 0, L_0x55ab20eaed00; 1 drivers
+v0x55ab20e3abb0_0 .net *"_ivl_14", 0 0, L_0x55ab20eaee40; 1 drivers
+v0x55ab20e3ac90_0 .net *"_ivl_16", 0 0, L_0x55ab20eaf090; 1 drivers
+v0x55ab20e3adc0_0 .net *"_ivl_3", 0 0, L_0x55ab20eae650; 1 drivers
+v0x55ab20e3aea0_0 .net *"_ivl_5", 0 0, L_0x55ab20eae790; 1 drivers
+v0x55ab20e3af80_0 .net *"_ivl_7", 0 0, L_0x55ab20eae940; 1 drivers
+v0x55ab20e3b060_0 .net *"_ivl_9", 0 0, L_0x55ab20eaea60; 1 drivers
+v0x55ab20e3b1d0_0 .net "a", 1 0, L_0x55ab20eaf1a0; 1 drivers
+v0x55ab20e3b2b0_0 .net "b", 1 0, L_0x55ab20eaf240; 1 drivers
+v0x55ab20e3b390_0 .net "b0", 0 0, L_0x55ab20eae480; 1 drivers
+v0x55ab20e3b450_0 .net "f", 0 0, L_0x55ab20eae5e0; 1 drivers
+v0x55ab20e3b510_0 .net "g0", 0 0, L_0x55ab20eae880; 1 drivers
+v0x55ab20e3b5d0_0 .net "g1", 0 0, L_0x55ab20eaeb00; 1 drivers
+v0x55ab20e3b690_0 .net "y", 1 0, L_0x55ab20eaef50; 1 drivers
+L_0x55ab20eae4f0 .part L_0x55ab20eaf240, 1, 1;
+L_0x55ab20eae650 .part L_0x55ab20eaf240, 0, 1;
+L_0x55ab20eae790 .part L_0x55ab20eaf240, 1, 1;
+L_0x55ab20eae940 .part L_0x55ab20eaf240, 0, 1;
+L_0x55ab20eaea60 .part L_0x55ab20eaf1a0, 0, 1;
+L_0x55ab20eaebd0 .part L_0x55ab20eaf240, 0, 1;
+L_0x55ab20eaed00 .part L_0x55ab20eaf1a0, 1, 1;
+L_0x55ab20eaef50 .concat8 [ 1 1 0 0], L_0x55ab20eaee40, L_0x55ab20eaf090;
+S_0x55ab20e3b7f0 .scope generate, "genblk7[12]" "genblk7[12]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e3b980 .param/l "j" 0 2 164, +C4<01100>;
+L_0x55ab20eb0090 .part L_0x55ab20ef5480, 10, 2;
+L_0x55ab20eb0130 .part L_0x55ab20ef5480, 12, 2;
+S_0x55ab20e3ba60 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e3b7f0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eaf2e0 .functor NOT 1, L_0x55ab20eaf350, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eaf440 .functor AND 1, L_0x55ab20eaf4b0, L_0x55ab20eaf5f0, C4<1>, C4<1>;
+L_0x55ab20eaf6e0 .functor AND 1, L_0x55ab20eaf2e0, L_0x55ab20eaf7a0, L_0x55ab20eaf950, C4<1>;
+L_0x55ab20eaf9f0 .functor AND 1, L_0x55ab20eaf2e0, L_0x55ab20eafac0, L_0x55ab20eafbf0, C4<1>;
+L_0x55ab20eafd30 .functor OR 1, L_0x55ab20eaf440, L_0x55ab20eaf6e0, C4<0>, C4<0>;
+L_0x55ab20eaff80 .functor OR 1, L_0x55ab20eaf440, L_0x55ab20eaf9f0, C4<0>, C4<0>;
+v0x55ab20e3bcb0_0 .net *"_ivl_1", 0 0, L_0x55ab20eaf350; 1 drivers
+v0x55ab20e3bdb0_0 .net *"_ivl_11", 0 0, L_0x55ab20eafac0; 1 drivers
+v0x55ab20e3be90_0 .net *"_ivl_13", 0 0, L_0x55ab20eafbf0; 1 drivers
+v0x55ab20e3bf50_0 .net *"_ivl_14", 0 0, L_0x55ab20eafd30; 1 drivers
+v0x55ab20e3c030_0 .net *"_ivl_16", 0 0, L_0x55ab20eaff80; 1 drivers
+v0x55ab20e3c160_0 .net *"_ivl_3", 0 0, L_0x55ab20eaf4b0; 1 drivers
+v0x55ab20e3c240_0 .net *"_ivl_5", 0 0, L_0x55ab20eaf5f0; 1 drivers
+v0x55ab20e3c320_0 .net *"_ivl_7", 0 0, L_0x55ab20eaf7a0; 1 drivers
+v0x55ab20e3c400_0 .net *"_ivl_9", 0 0, L_0x55ab20eaf950; 1 drivers
+v0x55ab20e3c570_0 .net "a", 1 0, L_0x55ab20eb0090; 1 drivers
+v0x55ab20e3c650_0 .net "b", 1 0, L_0x55ab20eb0130; 1 drivers
+v0x55ab20e3c730_0 .net "b0", 0 0, L_0x55ab20eaf2e0; 1 drivers
+v0x55ab20e3c7f0_0 .net "f", 0 0, L_0x55ab20eaf440; 1 drivers
+v0x55ab20e3c8b0_0 .net "g0", 0 0, L_0x55ab20eaf6e0; 1 drivers
+v0x55ab20e3c970_0 .net "g1", 0 0, L_0x55ab20eaf9f0; 1 drivers
+v0x55ab20e3ca30_0 .net "y", 1 0, L_0x55ab20eafe40; 1 drivers
+L_0x55ab20eaf350 .part L_0x55ab20eb0130, 1, 1;
+L_0x55ab20eaf4b0 .part L_0x55ab20eb0130, 0, 1;
+L_0x55ab20eaf5f0 .part L_0x55ab20eb0130, 1, 1;
+L_0x55ab20eaf7a0 .part L_0x55ab20eb0130, 0, 1;
+L_0x55ab20eaf950 .part L_0x55ab20eb0090, 0, 1;
+L_0x55ab20eafac0 .part L_0x55ab20eb0130, 0, 1;
+L_0x55ab20eafbf0 .part L_0x55ab20eb0090, 1, 1;
+L_0x55ab20eafe40 .concat8 [ 1 1 0 0], L_0x55ab20eafd30, L_0x55ab20eaff80;
+S_0x55ab20e3cb90 .scope generate, "genblk7[14]" "genblk7[14]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e3cd20 .param/l "j" 0 2 164, +C4<01110>;
+L_0x55ab20eb0f80 .part L_0x55ab20ef5480, 12, 2;
+L_0x55ab20eb1020 .part L_0x55ab20ef5480, 14, 2;
+S_0x55ab20e3ce00 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e3cb90;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb01d0 .functor NOT 1, L_0x55ab20eb0240, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb0330 .functor AND 1, L_0x55ab20eb03a0, L_0x55ab20eb04e0, C4<1>, C4<1>;
+L_0x55ab20eb05d0 .functor AND 1, L_0x55ab20eb01d0, L_0x55ab20eb0690, L_0x55ab20eb0840, C4<1>;
+L_0x55ab20eb08e0 .functor AND 1, L_0x55ab20eb01d0, L_0x55ab20eb09b0, L_0x55ab20eb0ae0, C4<1>;
+L_0x55ab20eb0c20 .functor OR 1, L_0x55ab20eb0330, L_0x55ab20eb05d0, C4<0>, C4<0>;
+L_0x55ab20eb0e70 .functor OR 1, L_0x55ab20eb0330, L_0x55ab20eb08e0, C4<0>, C4<0>;
+v0x55ab20e3d050_0 .net *"_ivl_1", 0 0, L_0x55ab20eb0240; 1 drivers
+v0x55ab20e3d150_0 .net *"_ivl_11", 0 0, L_0x55ab20eb09b0; 1 drivers
+v0x55ab20e3d230_0 .net *"_ivl_13", 0 0, L_0x55ab20eb0ae0; 1 drivers
+v0x55ab20e3d2f0_0 .net *"_ivl_14", 0 0, L_0x55ab20eb0c20; 1 drivers
+v0x55ab20e3d3d0_0 .net *"_ivl_16", 0 0, L_0x55ab20eb0e70; 1 drivers
+v0x55ab20e3d500_0 .net *"_ivl_3", 0 0, L_0x55ab20eb03a0; 1 drivers
+v0x55ab20e3d5e0_0 .net *"_ivl_5", 0 0, L_0x55ab20eb04e0; 1 drivers
+v0x55ab20e3d6c0_0 .net *"_ivl_7", 0 0, L_0x55ab20eb0690; 1 drivers
+v0x55ab20e3d7a0_0 .net *"_ivl_9", 0 0, L_0x55ab20eb0840; 1 drivers
+v0x55ab20e3d910_0 .net "a", 1 0, L_0x55ab20eb0f80; 1 drivers
+v0x55ab20e3d9f0_0 .net "b", 1 0, L_0x55ab20eb1020; 1 drivers
+v0x55ab20e3dad0_0 .net "b0", 0 0, L_0x55ab20eb01d0; 1 drivers
+v0x55ab20e3db90_0 .net "f", 0 0, L_0x55ab20eb0330; 1 drivers
+v0x55ab20e3dc50_0 .net "g0", 0 0, L_0x55ab20eb05d0; 1 drivers
+v0x55ab20e3dd10_0 .net "g1", 0 0, L_0x55ab20eb08e0; 1 drivers
+v0x55ab20e3ddd0_0 .net "y", 1 0, L_0x55ab20eb0d30; 1 drivers
+L_0x55ab20eb0240 .part L_0x55ab20eb1020, 1, 1;
+L_0x55ab20eb03a0 .part L_0x55ab20eb1020, 0, 1;
+L_0x55ab20eb04e0 .part L_0x55ab20eb1020, 1, 1;
+L_0x55ab20eb0690 .part L_0x55ab20eb1020, 0, 1;
+L_0x55ab20eb0840 .part L_0x55ab20eb0f80, 0, 1;
+L_0x55ab20eb09b0 .part L_0x55ab20eb1020, 0, 1;
+L_0x55ab20eb0ae0 .part L_0x55ab20eb0f80, 1, 1;
+L_0x55ab20eb0d30 .concat8 [ 1 1 0 0], L_0x55ab20eb0c20, L_0x55ab20eb0e70;
+S_0x55ab20e3df30 .scope generate, "genblk7[16]" "genblk7[16]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e3e0c0 .param/l "j" 0 2 164, +C4<010000>;
+L_0x55ab20eb1e70 .part L_0x55ab20ef5480, 14, 2;
+L_0x55ab20eb1f10 .part L_0x55ab20ef5480, 16, 2;
+S_0x55ab20e3e1a0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e3df30;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb10c0 .functor NOT 1, L_0x55ab20eb1130, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb1220 .functor AND 1, L_0x55ab20eb1290, L_0x55ab20eb13d0, C4<1>, C4<1>;
+L_0x55ab20eb14c0 .functor AND 1, L_0x55ab20eb10c0, L_0x55ab20eb1580, L_0x55ab20eb1730, C4<1>;
+L_0x55ab20eb17d0 .functor AND 1, L_0x55ab20eb10c0, L_0x55ab20eb18a0, L_0x55ab20eb19d0, C4<1>;
+L_0x55ab20eb1b10 .functor OR 1, L_0x55ab20eb1220, L_0x55ab20eb14c0, C4<0>, C4<0>;
+L_0x55ab20eb1d60 .functor OR 1, L_0x55ab20eb1220, L_0x55ab20eb17d0, C4<0>, C4<0>;
+v0x55ab20e3e3f0_0 .net *"_ivl_1", 0 0, L_0x55ab20eb1130; 1 drivers
+v0x55ab20e3e4f0_0 .net *"_ivl_11", 0 0, L_0x55ab20eb18a0; 1 drivers
+v0x55ab20e3e5d0_0 .net *"_ivl_13", 0 0, L_0x55ab20eb19d0; 1 drivers
+v0x55ab20e3e690_0 .net *"_ivl_14", 0 0, L_0x55ab20eb1b10; 1 drivers
+v0x55ab20e3e770_0 .net *"_ivl_16", 0 0, L_0x55ab20eb1d60; 1 drivers
+v0x55ab20e3e8a0_0 .net *"_ivl_3", 0 0, L_0x55ab20eb1290; 1 drivers
+v0x55ab20e3e980_0 .net *"_ivl_5", 0 0, L_0x55ab20eb13d0; 1 drivers
+v0x55ab20e3ea60_0 .net *"_ivl_7", 0 0, L_0x55ab20eb1580; 1 drivers
+v0x55ab20e3eb40_0 .net *"_ivl_9", 0 0, L_0x55ab20eb1730; 1 drivers
+v0x55ab20e3ecb0_0 .net "a", 1 0, L_0x55ab20eb1e70; 1 drivers
+v0x55ab20e3ed90_0 .net "b", 1 0, L_0x55ab20eb1f10; 1 drivers
+v0x55ab20e3ee70_0 .net "b0", 0 0, L_0x55ab20eb10c0; 1 drivers
+v0x55ab20e3ef30_0 .net "f", 0 0, L_0x55ab20eb1220; 1 drivers
+v0x55ab20e3eff0_0 .net "g0", 0 0, L_0x55ab20eb14c0; 1 drivers
+v0x55ab20e3f0b0_0 .net "g1", 0 0, L_0x55ab20eb17d0; 1 drivers
+v0x55ab20e3f170_0 .net "y", 1 0, L_0x55ab20eb1c20; 1 drivers
+L_0x55ab20eb1130 .part L_0x55ab20eb1f10, 1, 1;
+L_0x55ab20eb1290 .part L_0x55ab20eb1f10, 0, 1;
+L_0x55ab20eb13d0 .part L_0x55ab20eb1f10, 1, 1;
+L_0x55ab20eb1580 .part L_0x55ab20eb1f10, 0, 1;
+L_0x55ab20eb1730 .part L_0x55ab20eb1e70, 0, 1;
+L_0x55ab20eb18a0 .part L_0x55ab20eb1f10, 0, 1;
+L_0x55ab20eb19d0 .part L_0x55ab20eb1e70, 1, 1;
+L_0x55ab20eb1c20 .concat8 [ 1 1 0 0], L_0x55ab20eb1b10, L_0x55ab20eb1d60;
+S_0x55ab20e3f2d0 .scope generate, "genblk7[18]" "genblk7[18]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e3a590 .param/l "j" 0 2 164, +C4<010010>;
+L_0x55ab20eb2d60 .part L_0x55ab20ef5480, 16, 2;
+L_0x55ab20eb2e00 .part L_0x55ab20ef5480, 18, 2;
+S_0x55ab20e3f580 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e3f2d0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb1fb0 .functor NOT 1, L_0x55ab20eb2020, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb2110 .functor AND 1, L_0x55ab20eb2180, L_0x55ab20eb22c0, C4<1>, C4<1>;
+L_0x55ab20eb23b0 .functor AND 1, L_0x55ab20eb1fb0, L_0x55ab20eb2470, L_0x55ab20eb2620, C4<1>;
+L_0x55ab20eb26c0 .functor AND 1, L_0x55ab20eb1fb0, L_0x55ab20eb2790, L_0x55ab20eb28c0, C4<1>;
+L_0x55ab20eb2a00 .functor OR 1, L_0x55ab20eb2110, L_0x55ab20eb23b0, C4<0>, C4<0>;
+L_0x55ab20eb2c50 .functor OR 1, L_0x55ab20eb2110, L_0x55ab20eb26c0, C4<0>, C4<0>;
+v0x55ab20e3f7d0_0 .net *"_ivl_1", 0 0, L_0x55ab20eb2020; 1 drivers
+v0x55ab20e3f8d0_0 .net *"_ivl_11", 0 0, L_0x55ab20eb2790; 1 drivers
+v0x55ab20e3f9b0_0 .net *"_ivl_13", 0 0, L_0x55ab20eb28c0; 1 drivers
+v0x55ab20e3fa70_0 .net *"_ivl_14", 0 0, L_0x55ab20eb2a00; 1 drivers
+v0x55ab20e3fb50_0 .net *"_ivl_16", 0 0, L_0x55ab20eb2c50; 1 drivers
+v0x55ab20e3fc80_0 .net *"_ivl_3", 0 0, L_0x55ab20eb2180; 1 drivers
+v0x55ab20e3fd60_0 .net *"_ivl_5", 0 0, L_0x55ab20eb22c0; 1 drivers
+v0x55ab20e3fe40_0 .net *"_ivl_7", 0 0, L_0x55ab20eb2470; 1 drivers
+v0x55ab20e3ff20_0 .net *"_ivl_9", 0 0, L_0x55ab20eb2620; 1 drivers
+v0x55ab20e40090_0 .net "a", 1 0, L_0x55ab20eb2d60; 1 drivers
+v0x55ab20e40170_0 .net "b", 1 0, L_0x55ab20eb2e00; 1 drivers
+v0x55ab20e40250_0 .net "b0", 0 0, L_0x55ab20eb1fb0; 1 drivers
+v0x55ab20e40310_0 .net "f", 0 0, L_0x55ab20eb2110; 1 drivers
+v0x55ab20e403d0_0 .net "g0", 0 0, L_0x55ab20eb23b0; 1 drivers
+v0x55ab20e40490_0 .net "g1", 0 0, L_0x55ab20eb26c0; 1 drivers
+v0x55ab20e40550_0 .net "y", 1 0, L_0x55ab20eb2b10; 1 drivers
+L_0x55ab20eb2020 .part L_0x55ab20eb2e00, 1, 1;
+L_0x55ab20eb2180 .part L_0x55ab20eb2e00, 0, 1;
+L_0x55ab20eb22c0 .part L_0x55ab20eb2e00, 1, 1;
+L_0x55ab20eb2470 .part L_0x55ab20eb2e00, 0, 1;
+L_0x55ab20eb2620 .part L_0x55ab20eb2d60, 0, 1;
+L_0x55ab20eb2790 .part L_0x55ab20eb2e00, 0, 1;
+L_0x55ab20eb28c0 .part L_0x55ab20eb2d60, 1, 1;
+L_0x55ab20eb2b10 .concat8 [ 1 1 0 0], L_0x55ab20eb2a00, L_0x55ab20eb2c50;
+S_0x55ab20e406b0 .scope generate, "genblk7[20]" "genblk7[20]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e40840 .param/l "j" 0 2 164, +C4<010100>;
+L_0x55ab20eb3c50 .part L_0x55ab20ef5480, 18, 2;
+L_0x55ab20eb3cf0 .part L_0x55ab20ef5480, 20, 2;
+S_0x55ab20e40920 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e406b0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb2ea0 .functor NOT 1, L_0x55ab20eb2f10, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb3000 .functor AND 1, L_0x55ab20eb3070, L_0x55ab20eb31b0, C4<1>, C4<1>;
+L_0x55ab20eb32a0 .functor AND 1, L_0x55ab20eb2ea0, L_0x55ab20eb3360, L_0x55ab20eb3510, C4<1>;
+L_0x55ab20eb35b0 .functor AND 1, L_0x55ab20eb2ea0, L_0x55ab20eb3680, L_0x55ab20eb37b0, C4<1>;
+L_0x55ab20eb38f0 .functor OR 1, L_0x55ab20eb3000, L_0x55ab20eb32a0, C4<0>, C4<0>;
+L_0x55ab20eb3b40 .functor OR 1, L_0x55ab20eb3000, L_0x55ab20eb35b0, C4<0>, C4<0>;
+v0x55ab20e40b70_0 .net *"_ivl_1", 0 0, L_0x55ab20eb2f10; 1 drivers
+v0x55ab20e40c70_0 .net *"_ivl_11", 0 0, L_0x55ab20eb3680; 1 drivers
+v0x55ab20e40d50_0 .net *"_ivl_13", 0 0, L_0x55ab20eb37b0; 1 drivers
+v0x55ab20e40e10_0 .net *"_ivl_14", 0 0, L_0x55ab20eb38f0; 1 drivers
+v0x55ab20e40ef0_0 .net *"_ivl_16", 0 0, L_0x55ab20eb3b40; 1 drivers
+v0x55ab20e41020_0 .net *"_ivl_3", 0 0, L_0x55ab20eb3070; 1 drivers
+v0x55ab20e41100_0 .net *"_ivl_5", 0 0, L_0x55ab20eb31b0; 1 drivers
+v0x55ab20e411e0_0 .net *"_ivl_7", 0 0, L_0x55ab20eb3360; 1 drivers
+v0x55ab20e412c0_0 .net *"_ivl_9", 0 0, L_0x55ab20eb3510; 1 drivers
+v0x55ab20e41430_0 .net "a", 1 0, L_0x55ab20eb3c50; 1 drivers
+v0x55ab20e41510_0 .net "b", 1 0, L_0x55ab20eb3cf0; 1 drivers
+v0x55ab20e415f0_0 .net "b0", 0 0, L_0x55ab20eb2ea0; 1 drivers
+v0x55ab20e416b0_0 .net "f", 0 0, L_0x55ab20eb3000; 1 drivers
+v0x55ab20e41770_0 .net "g0", 0 0, L_0x55ab20eb32a0; 1 drivers
+v0x55ab20e41830_0 .net "g1", 0 0, L_0x55ab20eb35b0; 1 drivers
+v0x55ab20e418f0_0 .net "y", 1 0, L_0x55ab20eb3a00; 1 drivers
+L_0x55ab20eb2f10 .part L_0x55ab20eb3cf0, 1, 1;
+L_0x55ab20eb3070 .part L_0x55ab20eb3cf0, 0, 1;
+L_0x55ab20eb31b0 .part L_0x55ab20eb3cf0, 1, 1;
+L_0x55ab20eb3360 .part L_0x55ab20eb3cf0, 0, 1;
+L_0x55ab20eb3510 .part L_0x55ab20eb3c50, 0, 1;
+L_0x55ab20eb3680 .part L_0x55ab20eb3cf0, 0, 1;
+L_0x55ab20eb37b0 .part L_0x55ab20eb3c50, 1, 1;
+L_0x55ab20eb3a00 .concat8 [ 1 1 0 0], L_0x55ab20eb38f0, L_0x55ab20eb3b40;
+S_0x55ab20e41a50 .scope generate, "genblk7[22]" "genblk7[22]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e41be0 .param/l "j" 0 2 164, +C4<010110>;
+L_0x55ab20eb4b40 .part L_0x55ab20ef5480, 20, 2;
+L_0x55ab20eb4be0 .part L_0x55ab20ef5480, 22, 2;
+S_0x55ab20e41cc0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e41a50;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb3d90 .functor NOT 1, L_0x55ab20eb3e00, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb3ef0 .functor AND 1, L_0x55ab20eb3f60, L_0x55ab20eb40a0, C4<1>, C4<1>;
+L_0x55ab20eb4190 .functor AND 1, L_0x55ab20eb3d90, L_0x55ab20eb4250, L_0x55ab20eb4400, C4<1>;
+L_0x55ab20eb44a0 .functor AND 1, L_0x55ab20eb3d90, L_0x55ab20eb4570, L_0x55ab20eb46a0, C4<1>;
+L_0x55ab20eb47e0 .functor OR 1, L_0x55ab20eb3ef0, L_0x55ab20eb4190, C4<0>, C4<0>;
+L_0x55ab20eb4a30 .functor OR 1, L_0x55ab20eb3ef0, L_0x55ab20eb44a0, C4<0>, C4<0>;
+v0x55ab20e41f10_0 .net *"_ivl_1", 0 0, L_0x55ab20eb3e00; 1 drivers
+v0x55ab20e42010_0 .net *"_ivl_11", 0 0, L_0x55ab20eb4570; 1 drivers
+v0x55ab20e420f0_0 .net *"_ivl_13", 0 0, L_0x55ab20eb46a0; 1 drivers
+v0x55ab20e421b0_0 .net *"_ivl_14", 0 0, L_0x55ab20eb47e0; 1 drivers
+v0x55ab20e42290_0 .net *"_ivl_16", 0 0, L_0x55ab20eb4a30; 1 drivers
+v0x55ab20e423c0_0 .net *"_ivl_3", 0 0, L_0x55ab20eb3f60; 1 drivers
+v0x55ab20e424a0_0 .net *"_ivl_5", 0 0, L_0x55ab20eb40a0; 1 drivers
+v0x55ab20e42580_0 .net *"_ivl_7", 0 0, L_0x55ab20eb4250; 1 drivers
+v0x55ab20e42660_0 .net *"_ivl_9", 0 0, L_0x55ab20eb4400; 1 drivers
+v0x55ab20e427d0_0 .net "a", 1 0, L_0x55ab20eb4b40; 1 drivers
+v0x55ab20e428b0_0 .net "b", 1 0, L_0x55ab20eb4be0; 1 drivers
+v0x55ab20e42990_0 .net "b0", 0 0, L_0x55ab20eb3d90; 1 drivers
+v0x55ab20e42a50_0 .net "f", 0 0, L_0x55ab20eb3ef0; 1 drivers
+v0x55ab20e42b10_0 .net "g0", 0 0, L_0x55ab20eb4190; 1 drivers
+v0x55ab20e42bd0_0 .net "g1", 0 0, L_0x55ab20eb44a0; 1 drivers
+v0x55ab20e42c90_0 .net "y", 1 0, L_0x55ab20eb48f0; 1 drivers
+L_0x55ab20eb3e00 .part L_0x55ab20eb4be0, 1, 1;
+L_0x55ab20eb3f60 .part L_0x55ab20eb4be0, 0, 1;
+L_0x55ab20eb40a0 .part L_0x55ab20eb4be0, 1, 1;
+L_0x55ab20eb4250 .part L_0x55ab20eb4be0, 0, 1;
+L_0x55ab20eb4400 .part L_0x55ab20eb4b40, 0, 1;
+L_0x55ab20eb4570 .part L_0x55ab20eb4be0, 0, 1;
+L_0x55ab20eb46a0 .part L_0x55ab20eb4b40, 1, 1;
+L_0x55ab20eb48f0 .concat8 [ 1 1 0 0], L_0x55ab20eb47e0, L_0x55ab20eb4a30;
+S_0x55ab20e42df0 .scope generate, "genblk7[24]" "genblk7[24]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e42f80 .param/l "j" 0 2 164, +C4<011000>;
+L_0x55ab20eb5a30 .part L_0x55ab20ef5480, 22, 2;
+L_0x55ab20eb5ad0 .part L_0x55ab20ef5480, 24, 2;
+S_0x55ab20e43060 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e42df0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb4c80 .functor NOT 1, L_0x55ab20eb4cf0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb4de0 .functor AND 1, L_0x55ab20eb4e50, L_0x55ab20eb4f90, C4<1>, C4<1>;
+L_0x55ab20eb5080 .functor AND 1, L_0x55ab20eb4c80, L_0x55ab20eb5140, L_0x55ab20eb52f0, C4<1>;
+L_0x55ab20eb5390 .functor AND 1, L_0x55ab20eb4c80, L_0x55ab20eb5460, L_0x55ab20eb5590, C4<1>;
+L_0x55ab20eb56d0 .functor OR 1, L_0x55ab20eb4de0, L_0x55ab20eb5080, C4<0>, C4<0>;
+L_0x55ab20eb5920 .functor OR 1, L_0x55ab20eb4de0, L_0x55ab20eb5390, C4<0>, C4<0>;
+v0x55ab20e432b0_0 .net *"_ivl_1", 0 0, L_0x55ab20eb4cf0; 1 drivers
+v0x55ab20e433b0_0 .net *"_ivl_11", 0 0, L_0x55ab20eb5460; 1 drivers
+v0x55ab20e43490_0 .net *"_ivl_13", 0 0, L_0x55ab20eb5590; 1 drivers
+v0x55ab20e43550_0 .net *"_ivl_14", 0 0, L_0x55ab20eb56d0; 1 drivers
+v0x55ab20e43630_0 .net *"_ivl_16", 0 0, L_0x55ab20eb5920; 1 drivers
+v0x55ab20e43760_0 .net *"_ivl_3", 0 0, L_0x55ab20eb4e50; 1 drivers
+v0x55ab20e43840_0 .net *"_ivl_5", 0 0, L_0x55ab20eb4f90; 1 drivers
+v0x55ab20e43920_0 .net *"_ivl_7", 0 0, L_0x55ab20eb5140; 1 drivers
+v0x55ab20e43a00_0 .net *"_ivl_9", 0 0, L_0x55ab20eb52f0; 1 drivers
+v0x55ab20e43b70_0 .net "a", 1 0, L_0x55ab20eb5a30; 1 drivers
+v0x55ab20e43c50_0 .net "b", 1 0, L_0x55ab20eb5ad0; 1 drivers
+v0x55ab20e43d30_0 .net "b0", 0 0, L_0x55ab20eb4c80; 1 drivers
+v0x55ab20e43df0_0 .net "f", 0 0, L_0x55ab20eb4de0; 1 drivers
+v0x55ab20e43eb0_0 .net "g0", 0 0, L_0x55ab20eb5080; 1 drivers
+v0x55ab20e43f70_0 .net "g1", 0 0, L_0x55ab20eb5390; 1 drivers
+v0x55ab20e44030_0 .net "y", 1 0, L_0x55ab20eb57e0; 1 drivers
+L_0x55ab20eb4cf0 .part L_0x55ab20eb5ad0, 1, 1;
+L_0x55ab20eb4e50 .part L_0x55ab20eb5ad0, 0, 1;
+L_0x55ab20eb4f90 .part L_0x55ab20eb5ad0, 1, 1;
+L_0x55ab20eb5140 .part L_0x55ab20eb5ad0, 0, 1;
+L_0x55ab20eb52f0 .part L_0x55ab20eb5a30, 0, 1;
+L_0x55ab20eb5460 .part L_0x55ab20eb5ad0, 0, 1;
+L_0x55ab20eb5590 .part L_0x55ab20eb5a30, 1, 1;
+L_0x55ab20eb57e0 .concat8 [ 1 1 0 0], L_0x55ab20eb56d0, L_0x55ab20eb5920;
+S_0x55ab20e44190 .scope generate, "genblk7[26]" "genblk7[26]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e44320 .param/l "j" 0 2 164, +C4<011010>;
+L_0x55ab20eb6920 .part L_0x55ab20ef5480, 24, 2;
+L_0x55ab20eb69c0 .part L_0x55ab20ef5480, 26, 2;
+S_0x55ab20e44400 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e44190;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb5b70 .functor NOT 1, L_0x55ab20eb5be0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb5cd0 .functor AND 1, L_0x55ab20eb5d40, L_0x55ab20eb5e80, C4<1>, C4<1>;
+L_0x55ab20eb5f70 .functor AND 1, L_0x55ab20eb5b70, L_0x55ab20eb6030, L_0x55ab20eb61e0, C4<1>;
+L_0x55ab20eb6280 .functor AND 1, L_0x55ab20eb5b70, L_0x55ab20eb6350, L_0x55ab20eb6480, C4<1>;
+L_0x55ab20eb65c0 .functor OR 1, L_0x55ab20eb5cd0, L_0x55ab20eb5f70, C4<0>, C4<0>;
+L_0x55ab20eb6810 .functor OR 1, L_0x55ab20eb5cd0, L_0x55ab20eb6280, C4<0>, C4<0>;
+v0x55ab20e44650_0 .net *"_ivl_1", 0 0, L_0x55ab20eb5be0; 1 drivers
+v0x55ab20e44750_0 .net *"_ivl_11", 0 0, L_0x55ab20eb6350; 1 drivers
+v0x55ab20e44830_0 .net *"_ivl_13", 0 0, L_0x55ab20eb6480; 1 drivers
+v0x55ab20e448f0_0 .net *"_ivl_14", 0 0, L_0x55ab20eb65c0; 1 drivers
+v0x55ab20e449d0_0 .net *"_ivl_16", 0 0, L_0x55ab20eb6810; 1 drivers
+v0x55ab20e44b00_0 .net *"_ivl_3", 0 0, L_0x55ab20eb5d40; 1 drivers
+v0x55ab20e44be0_0 .net *"_ivl_5", 0 0, L_0x55ab20eb5e80; 1 drivers
+v0x55ab20e44cc0_0 .net *"_ivl_7", 0 0, L_0x55ab20eb6030; 1 drivers
+v0x55ab20e44da0_0 .net *"_ivl_9", 0 0, L_0x55ab20eb61e0; 1 drivers
+v0x55ab20e44f10_0 .net "a", 1 0, L_0x55ab20eb6920; 1 drivers
+v0x55ab20e44ff0_0 .net "b", 1 0, L_0x55ab20eb69c0; 1 drivers
+v0x55ab20e450d0_0 .net "b0", 0 0, L_0x55ab20eb5b70; 1 drivers
+v0x55ab20e45190_0 .net "f", 0 0, L_0x55ab20eb5cd0; 1 drivers
+v0x55ab20e45250_0 .net "g0", 0 0, L_0x55ab20eb5f70; 1 drivers
+v0x55ab20e45310_0 .net "g1", 0 0, L_0x55ab20eb6280; 1 drivers
+v0x55ab20e453d0_0 .net "y", 1 0, L_0x55ab20eb66d0; 1 drivers
+L_0x55ab20eb5be0 .part L_0x55ab20eb69c0, 1, 1;
+L_0x55ab20eb5d40 .part L_0x55ab20eb69c0, 0, 1;
+L_0x55ab20eb5e80 .part L_0x55ab20eb69c0, 1, 1;
+L_0x55ab20eb6030 .part L_0x55ab20eb69c0, 0, 1;
+L_0x55ab20eb61e0 .part L_0x55ab20eb6920, 0, 1;
+L_0x55ab20eb6350 .part L_0x55ab20eb69c0, 0, 1;
+L_0x55ab20eb6480 .part L_0x55ab20eb6920, 1, 1;
+L_0x55ab20eb66d0 .concat8 [ 1 1 0 0], L_0x55ab20eb65c0, L_0x55ab20eb6810;
+S_0x55ab20e45530 .scope generate, "genblk7[28]" "genblk7[28]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e456c0 .param/l "j" 0 2 164, +C4<011100>;
+L_0x55ab20eb7810 .part L_0x55ab20ef5480, 26, 2;
+L_0x55ab20eb78b0 .part L_0x55ab20ef5480, 28, 2;
+S_0x55ab20e457a0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e45530;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb6a60 .functor NOT 1, L_0x55ab20eb6ad0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb6bc0 .functor AND 1, L_0x55ab20eb6c30, L_0x55ab20eb6d70, C4<1>, C4<1>;
+L_0x55ab20eb6e60 .functor AND 1, L_0x55ab20eb6a60, L_0x55ab20eb6f20, L_0x55ab20eb70d0, C4<1>;
+L_0x55ab20eb7170 .functor AND 1, L_0x55ab20eb6a60, L_0x55ab20eb7240, L_0x55ab20eb7370, C4<1>;
+L_0x55ab20eb74b0 .functor OR 1, L_0x55ab20eb6bc0, L_0x55ab20eb6e60, C4<0>, C4<0>;
+L_0x55ab20eb7700 .functor OR 1, L_0x55ab20eb6bc0, L_0x55ab20eb7170, C4<0>, C4<0>;
+v0x55ab20e459f0_0 .net *"_ivl_1", 0 0, L_0x55ab20eb6ad0; 1 drivers
+v0x55ab20e45af0_0 .net *"_ivl_11", 0 0, L_0x55ab20eb7240; 1 drivers
+v0x55ab20e45bd0_0 .net *"_ivl_13", 0 0, L_0x55ab20eb7370; 1 drivers
+v0x55ab20e45c90_0 .net *"_ivl_14", 0 0, L_0x55ab20eb74b0; 1 drivers
+v0x55ab20e45d70_0 .net *"_ivl_16", 0 0, L_0x55ab20eb7700; 1 drivers
+v0x55ab20e45ea0_0 .net *"_ivl_3", 0 0, L_0x55ab20eb6c30; 1 drivers
+v0x55ab20e45f80_0 .net *"_ivl_5", 0 0, L_0x55ab20eb6d70; 1 drivers
+v0x55ab20e46060_0 .net *"_ivl_7", 0 0, L_0x55ab20eb6f20; 1 drivers
+v0x55ab20e46140_0 .net *"_ivl_9", 0 0, L_0x55ab20eb70d0; 1 drivers
+v0x55ab20e462b0_0 .net "a", 1 0, L_0x55ab20eb7810; 1 drivers
+v0x55ab20e46390_0 .net "b", 1 0, L_0x55ab20eb78b0; 1 drivers
+v0x55ab20e46470_0 .net "b0", 0 0, L_0x55ab20eb6a60; 1 drivers
+v0x55ab20e46530_0 .net "f", 0 0, L_0x55ab20eb6bc0; 1 drivers
+v0x55ab20e465f0_0 .net "g0", 0 0, L_0x55ab20eb6e60; 1 drivers
+v0x55ab20e466b0_0 .net "g1", 0 0, L_0x55ab20eb7170; 1 drivers
+v0x55ab20e46770_0 .net "y", 1 0, L_0x55ab20eb75c0; 1 drivers
+L_0x55ab20eb6ad0 .part L_0x55ab20eb78b0, 1, 1;
+L_0x55ab20eb6c30 .part L_0x55ab20eb78b0, 0, 1;
+L_0x55ab20eb6d70 .part L_0x55ab20eb78b0, 1, 1;
+L_0x55ab20eb6f20 .part L_0x55ab20eb78b0, 0, 1;
+L_0x55ab20eb70d0 .part L_0x55ab20eb7810, 0, 1;
+L_0x55ab20eb7240 .part L_0x55ab20eb78b0, 0, 1;
+L_0x55ab20eb7370 .part L_0x55ab20eb7810, 1, 1;
+L_0x55ab20eb75c0 .concat8 [ 1 1 0 0], L_0x55ab20eb74b0, L_0x55ab20eb7700;
+S_0x55ab20e468d0 .scope generate, "genblk7[30]" "genblk7[30]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e46a60 .param/l "j" 0 2 164, +C4<011110>;
+L_0x55ab20eb86d0 .part L_0x55ab20ef5480, 28, 2;
+L_0x55ab20eb8770 .part L_0x55ab20ef5480, 30, 2;
+S_0x55ab20e46b40 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e468d0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb7950 .functor NOT 1, L_0x55ab20eb79c0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb7ab0 .functor AND 1, L_0x55ab20eb7b20, L_0x55ab20eb7c60, C4<1>, C4<1>;
+L_0x55ab20eb7d50 .functor AND 1, L_0x55ab20eb7950, L_0x55ab20eb7e10, L_0x55ab20eb7fc0, C4<1>;
+L_0x55ab20eb8060 .functor AND 1, L_0x55ab20eb7950, L_0x55ab20eb8100, L_0x55ab20eb8230, C4<1>;
+L_0x55ab20eb8370 .functor OR 1, L_0x55ab20eb7ab0, L_0x55ab20eb7d50, C4<0>, C4<0>;
+L_0x55ab20eb85c0 .functor OR 1, L_0x55ab20eb7ab0, L_0x55ab20eb8060, C4<0>, C4<0>;
+v0x55ab20e46d90_0 .net *"_ivl_1", 0 0, L_0x55ab20eb79c0; 1 drivers
+v0x55ab20e46e90_0 .net *"_ivl_11", 0 0, L_0x55ab20eb8100; 1 drivers
+v0x55ab20e46f70_0 .net *"_ivl_13", 0 0, L_0x55ab20eb8230; 1 drivers
+v0x55ab20e47010_0 .net *"_ivl_14", 0 0, L_0x55ab20eb8370; 1 drivers
+v0x55ab20e470b0_0 .net *"_ivl_16", 0 0, L_0x55ab20eb85c0; 1 drivers
+v0x55ab20e471a0_0 .net *"_ivl_3", 0 0, L_0x55ab20eb7b20; 1 drivers
+v0x55ab20e47240_0 .net *"_ivl_5", 0 0, L_0x55ab20eb7c60; 1 drivers
+v0x55ab20e47320_0 .net *"_ivl_7", 0 0, L_0x55ab20eb7e10; 1 drivers
+v0x55ab20e47400_0 .net *"_ivl_9", 0 0, L_0x55ab20eb7fc0; 1 drivers
+v0x55ab20e47570_0 .net "a", 1 0, L_0x55ab20eb86d0; 1 drivers
+v0x55ab20e47650_0 .net "b", 1 0, L_0x55ab20eb8770; 1 drivers
+v0x55ab20e47730_0 .net "b0", 0 0, L_0x55ab20eb7950; 1 drivers
+v0x55ab20e477f0_0 .net "f", 0 0, L_0x55ab20eb7ab0; 1 drivers
+v0x55ab20e478b0_0 .net "g0", 0 0, L_0x55ab20eb7d50; 1 drivers
+v0x55ab20e47970_0 .net "g1", 0 0, L_0x55ab20eb8060; 1 drivers
+v0x55ab20e47a30_0 .net "y", 1 0, L_0x55ab20eb8480; 1 drivers
+L_0x55ab20eb79c0 .part L_0x55ab20eb8770, 1, 1;
+L_0x55ab20eb7b20 .part L_0x55ab20eb8770, 0, 1;
+L_0x55ab20eb7c60 .part L_0x55ab20eb8770, 1, 1;
+L_0x55ab20eb7e10 .part L_0x55ab20eb8770, 0, 1;
+L_0x55ab20eb7fc0 .part L_0x55ab20eb86d0, 0, 1;
+L_0x55ab20eb8100 .part L_0x55ab20eb8770, 0, 1;
+L_0x55ab20eb8230 .part L_0x55ab20eb86d0, 1, 1;
+L_0x55ab20eb8480 .concat8 [ 1 1 0 0], L_0x55ab20eb8370, L_0x55ab20eb85c0;
+S_0x55ab20e47b90 .scope generate, "genblk7[32]" "genblk7[32]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e47d20 .param/l "j" 0 2 164, +C4<0100000>;
+L_0x55ab20eb9560 .part L_0x55ab20ef5480, 30, 2;
+L_0x55ab20eb9a10 .part L_0x55ab20ef5480, 32, 2;
+S_0x55ab20e47de0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e47b90;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb8810 .functor NOT 1, L_0x55ab20eb8880, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb8970 .functor AND 1, L_0x55ab20eb89e0, L_0x55ab20eb8b20, C4<1>, C4<1>;
+L_0x55ab20eb8c10 .functor AND 1, L_0x55ab20eb8810, L_0x55ab20eb8cd0, L_0x55ab20eb8e50, C4<1>;
+L_0x55ab20eb8ef0 .functor AND 1, L_0x55ab20eb8810, L_0x55ab20eb8f90, L_0x55ab20eb90c0, C4<1>;
+L_0x55ab20eb9200 .functor OR 1, L_0x55ab20eb8970, L_0x55ab20eb8c10, C4<0>, C4<0>;
+L_0x55ab20eb9450 .functor OR 1, L_0x55ab20eb8970, L_0x55ab20eb8ef0, C4<0>, C4<0>;
+v0x55ab20e48050_0 .net *"_ivl_1", 0 0, L_0x55ab20eb8880; 1 drivers
+v0x55ab20e48150_0 .net *"_ivl_11", 0 0, L_0x55ab20eb8f90; 1 drivers
+v0x55ab20e48230_0 .net *"_ivl_13", 0 0, L_0x55ab20eb90c0; 1 drivers
+v0x55ab20e482f0_0 .net *"_ivl_14", 0 0, L_0x55ab20eb9200; 1 drivers
+v0x55ab20e483d0_0 .net *"_ivl_16", 0 0, L_0x55ab20eb9450; 1 drivers
+v0x55ab20e48500_0 .net *"_ivl_3", 0 0, L_0x55ab20eb89e0; 1 drivers
+v0x55ab20e485e0_0 .net *"_ivl_5", 0 0, L_0x55ab20eb8b20; 1 drivers
+v0x55ab20e486c0_0 .net *"_ivl_7", 0 0, L_0x55ab20eb8cd0; 1 drivers
+v0x55ab20e487a0_0 .net *"_ivl_9", 0 0, L_0x55ab20eb8e50; 1 drivers
+v0x55ab20e48910_0 .net "a", 1 0, L_0x55ab20eb9560; 1 drivers
+v0x55ab20e489f0_0 .net "b", 1 0, L_0x55ab20eb9a10; 1 drivers
+v0x55ab20e48ad0_0 .net "b0", 0 0, L_0x55ab20eb8810; 1 drivers
+v0x55ab20e48b90_0 .net "f", 0 0, L_0x55ab20eb8970; 1 drivers
+v0x55ab20e48c50_0 .net "g0", 0 0, L_0x55ab20eb8c10; 1 drivers
+v0x55ab20e48d10_0 .net "g1", 0 0, L_0x55ab20eb8ef0; 1 drivers
+v0x55ab20e48dd0_0 .net "y", 1 0, L_0x55ab20eb9310; 1 drivers
+L_0x55ab20eb8880 .part L_0x55ab20eb9a10, 1, 1;
+L_0x55ab20eb89e0 .part L_0x55ab20eb9a10, 0, 1;
+L_0x55ab20eb8b20 .part L_0x55ab20eb9a10, 1, 1;
+L_0x55ab20eb8cd0 .part L_0x55ab20eb9a10, 0, 1;
+L_0x55ab20eb8e50 .part L_0x55ab20eb9560, 0, 1;
+L_0x55ab20eb8f90 .part L_0x55ab20eb9a10, 0, 1;
+L_0x55ab20eb90c0 .part L_0x55ab20eb9560, 1, 1;
+L_0x55ab20eb9310 .concat8 [ 1 1 0 0], L_0x55ab20eb9200, L_0x55ab20eb9450;
+S_0x55ab20e48f30 .scope generate, "genblk7[34]" "genblk7[34]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e491d0 .param/l "j" 0 2 164, +C4<0100010>;
+L_0x55ab20eba830 .part L_0x55ab20ef5480, 32, 2;
+L_0x55ab20eba8d0 .part L_0x55ab20ef5480, 34, 2;
+S_0x55ab20e49290 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e48f30;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eb9ab0 .functor NOT 1, L_0x55ab20eb9b20, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eb9c10 .functor AND 1, L_0x55ab20eb9c80, L_0x55ab20eb9dc0, C4<1>, C4<1>;
+L_0x55ab20eb9eb0 .functor AND 1, L_0x55ab20eb9ab0, L_0x55ab20eb9f70, L_0x55ab20eba0f0, C4<1>;
+L_0x55ab20eba190 .functor AND 1, L_0x55ab20eb9ab0, L_0x55ab20eba260, L_0x55ab20eba390, C4<1>;
+L_0x55ab20eba4d0 .functor OR 1, L_0x55ab20eb9c10, L_0x55ab20eb9eb0, C4<0>, C4<0>;
+L_0x55ab20eba720 .functor OR 1, L_0x55ab20eb9c10, L_0x55ab20eba190, C4<0>, C4<0>;
+v0x55ab20e49500_0 .net *"_ivl_1", 0 0, L_0x55ab20eb9b20; 1 drivers
+v0x55ab20e49600_0 .net *"_ivl_11", 0 0, L_0x55ab20eba260; 1 drivers
+v0x55ab20e496e0_0 .net *"_ivl_13", 0 0, L_0x55ab20eba390; 1 drivers
+v0x55ab20e497a0_0 .net *"_ivl_14", 0 0, L_0x55ab20eba4d0; 1 drivers
+v0x55ab20e49880_0 .net *"_ivl_16", 0 0, L_0x55ab20eba720; 1 drivers
+v0x55ab20e499b0_0 .net *"_ivl_3", 0 0, L_0x55ab20eb9c80; 1 drivers
+v0x55ab20e49a90_0 .net *"_ivl_5", 0 0, L_0x55ab20eb9dc0; 1 drivers
+v0x55ab20e49b70_0 .net *"_ivl_7", 0 0, L_0x55ab20eb9f70; 1 drivers
+v0x55ab20e49c50_0 .net *"_ivl_9", 0 0, L_0x55ab20eba0f0; 1 drivers
+v0x55ab20e49d30_0 .net "a", 1 0, L_0x55ab20eba830; 1 drivers
+v0x55ab20e49e10_0 .net "b", 1 0, L_0x55ab20eba8d0; 1 drivers
+v0x55ab20e49ef0_0 .net "b0", 0 0, L_0x55ab20eb9ab0; 1 drivers
+v0x55ab20e49fb0_0 .net "f", 0 0, L_0x55ab20eb9c10; 1 drivers
+v0x55ab20e4a070_0 .net "g0", 0 0, L_0x55ab20eb9eb0; 1 drivers
+v0x55ab20e4a130_0 .net "g1", 0 0, L_0x55ab20eba190; 1 drivers
+v0x55ab20e4a1f0_0 .net "y", 1 0, L_0x55ab20eba5e0; 1 drivers
+L_0x55ab20eb9b20 .part L_0x55ab20eba8d0, 1, 1;
+L_0x55ab20eb9c80 .part L_0x55ab20eba8d0, 0, 1;
+L_0x55ab20eb9dc0 .part L_0x55ab20eba8d0, 1, 1;
+L_0x55ab20eb9f70 .part L_0x55ab20eba8d0, 0, 1;
+L_0x55ab20eba0f0 .part L_0x55ab20eba830, 0, 1;
+L_0x55ab20eba260 .part L_0x55ab20eba8d0, 0, 1;
+L_0x55ab20eba390 .part L_0x55ab20eba830, 1, 1;
+L_0x55ab20eba5e0 .concat8 [ 1 1 0 0], L_0x55ab20eba4d0, L_0x55ab20eba720;
+S_0x55ab20e4a350 .scope generate, "genblk7[36]" "genblk7[36]" 2 164, 2 164 0, S_0x55ab20e35490;
+ .timescale 0 0;
+P_0x55ab20e4a4e0 .param/l "j" 0 2 164, +C4<0100100>;
+L_0x55ab20ebb720 .part L_0x55ab20ef5480, 34, 2;
+L_0x55ab20ebb7c0 .part L_0x55ab20ef5480, 36, 2;
+LS_0x55ab20ebb860_0_0 .concat8 [ 2 2 2 2], L_0x55ab20eaa7f0, L_0x55ab20eab450, L_0x55ab20eac2d0, L_0x55ab20ead200;
+LS_0x55ab20ebb860_0_4 .concat8 [ 2 2 2 2], L_0x55ab20eae0f0, L_0x55ab20eaef50, L_0x55ab20eafe40, L_0x55ab20eb0d30;
+LS_0x55ab20ebb860_0_8 .concat8 [ 2 2 2 2], L_0x55ab20eb1c20, L_0x55ab20eb2b10, L_0x55ab20eb3a00, L_0x55ab20eb48f0;
+LS_0x55ab20ebb860_0_12 .concat8 [ 2 2 2 2], L_0x55ab20eb57e0, L_0x55ab20eb66d0, L_0x55ab20eb75c0, L_0x55ab20eb8480;
+LS_0x55ab20ebb860_0_16 .concat8 [ 2 2 2 0], L_0x55ab20eb9310, L_0x55ab20eba5e0, L_0x55ab20ebb4d0;
+LS_0x55ab20ebb860_1_0 .concat8 [ 8 8 8 8], LS_0x55ab20ebb860_0_0, LS_0x55ab20ebb860_0_4, LS_0x55ab20ebb860_0_8, LS_0x55ab20ebb860_0_12;
+LS_0x55ab20ebb860_1_4 .concat8 [ 6 0 0 0], LS_0x55ab20ebb860_0_16;
+L_0x55ab20ebb860 .concat8 [ 32 6 0 0], LS_0x55ab20ebb860_1_0, LS_0x55ab20ebb860_1_4;
+S_0x55ab20e4a5a0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e4a350;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eba970 .functor NOT 1, L_0x55ab20eba9e0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ebaad0 .functor AND 1, L_0x55ab20ebab40, L_0x55ab20ebac80, C4<1>, C4<1>;
+L_0x55ab20ebad70 .functor AND 1, L_0x55ab20eba970, L_0x55ab20ebae30, L_0x55ab20ebafe0, C4<1>;
+L_0x55ab20ebb080 .functor AND 1, L_0x55ab20eba970, L_0x55ab20ebb150, L_0x55ab20ebb280, C4<1>;
+L_0x55ab20ebb3c0 .functor OR 1, L_0x55ab20ebaad0, L_0x55ab20ebad70, C4<0>, C4<0>;
+L_0x55ab20ebb610 .functor OR 1, L_0x55ab20ebaad0, L_0x55ab20ebb080, C4<0>, C4<0>;
+v0x55ab20e4a810_0 .net *"_ivl_1", 0 0, L_0x55ab20eba9e0; 1 drivers
+v0x55ab20e4a910_0 .net *"_ivl_11", 0 0, L_0x55ab20ebb150; 1 drivers
+v0x55ab20e4a9f0_0 .net *"_ivl_13", 0 0, L_0x55ab20ebb280; 1 drivers
+v0x55ab20e4aab0_0 .net *"_ivl_14", 0 0, L_0x55ab20ebb3c0; 1 drivers
+v0x55ab20e4ab90_0 .net *"_ivl_16", 0 0, L_0x55ab20ebb610; 1 drivers
+v0x55ab20e4acc0_0 .net *"_ivl_3", 0 0, L_0x55ab20ebab40; 1 drivers
+v0x55ab20e4ada0_0 .net *"_ivl_5", 0 0, L_0x55ab20ebac80; 1 drivers
+v0x55ab20e4ae80_0 .net *"_ivl_7", 0 0, L_0x55ab20ebae30; 1 drivers
+v0x55ab20e4af60_0 .net *"_ivl_9", 0 0, L_0x55ab20ebafe0; 1 drivers
+v0x55ab20e4b0d0_0 .net "a", 1 0, L_0x55ab20ebb720; 1 drivers
+v0x55ab20e4b1b0_0 .net "b", 1 0, L_0x55ab20ebb7c0; 1 drivers
+v0x55ab20e4b290_0 .net "b0", 0 0, L_0x55ab20eba970; 1 drivers
+v0x55ab20e4b350_0 .net "f", 0 0, L_0x55ab20ebaad0; 1 drivers
+v0x55ab20e4b410_0 .net "g0", 0 0, L_0x55ab20ebad70; 1 drivers
+v0x55ab20e4b4d0_0 .net "g1", 0 0, L_0x55ab20ebb080; 1 drivers
+v0x55ab20e4b590_0 .net "y", 1 0, L_0x55ab20ebb4d0; 1 drivers
+L_0x55ab20eba9e0 .part L_0x55ab20ebb7c0, 1, 1;
+L_0x55ab20ebab40 .part L_0x55ab20ebb7c0, 0, 1;
+L_0x55ab20ebac80 .part L_0x55ab20ebb7c0, 1, 1;
+L_0x55ab20ebae30 .part L_0x55ab20ebb7c0, 0, 1;
+L_0x55ab20ebafe0 .part L_0x55ab20ebb720, 0, 1;
+L_0x55ab20ebb150 .part L_0x55ab20ebb7c0, 0, 1;
+L_0x55ab20ebb280 .part L_0x55ab20ebb720, 1, 1;
+L_0x55ab20ebb4d0 .concat8 [ 1 1 0 0], L_0x55ab20ebb3c0, L_0x55ab20ebb610;
+S_0x55ab20e4b7d0 .scope generate, "genblk6[1]" "genblk6[1]" 2 161, 2 161 0, S_0x55ab20e352b0;
+ .timescale 0 0;
+P_0x55ab20e4b9a0 .param/l "i" 0 2 161, +C4<01>;
+v0x55ab20e60960_0 .net *"_ivl_5", 3 0, L_0x55ab20ebbef0; 1 drivers
+L_0x55ab20ebbef0 .part L_0x55ab20ebb860, 0, 4;
+S_0x55ab20e4ba60 .scope generate, "genblk7[4]" "genblk7[4]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e4bc60 .param/l "j" 0 2 164, +C4<0100>;
+L_0x55ab20ebcd00 .part L_0x55ab20ebb860, 0, 2;
+L_0x55ab20ebcda0 .part L_0x55ab20ebb860, 4, 2;
+S_0x55ab20e4bd40 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e4ba60;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ebbfe0 .functor NOT 1, L_0x55ab20ebc050, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ebc140 .functor AND 1, L_0x55ab20ebc1b0, L_0x55ab20ebc2f0, C4<1>, C4<1>;
+L_0x55ab20ebc3e0 .functor AND 1, L_0x55ab20ebbfe0, L_0x55ab20ebc4a0, L_0x55ab20ebc620, C4<1>;
+L_0x55ab20ebc6c0 .functor AND 1, L_0x55ab20ebbfe0, L_0x55ab20ebc730, L_0x55ab20ebc860, C4<1>;
+L_0x55ab20ebc9a0 .functor OR 1, L_0x55ab20ebc140, L_0x55ab20ebc3e0, C4<0>, C4<0>;
+L_0x55ab20ebcbf0 .functor OR 1, L_0x55ab20ebc140, L_0x55ab20ebc6c0, C4<0>, C4<0>;
+v0x55ab20e4bf90_0 .net *"_ivl_1", 0 0, L_0x55ab20ebc050; 1 drivers
+v0x55ab20e4c090_0 .net *"_ivl_11", 0 0, L_0x55ab20ebc730; 1 drivers
+v0x55ab20e4c170_0 .net *"_ivl_13", 0 0, L_0x55ab20ebc860; 1 drivers
+v0x55ab20e4c230_0 .net *"_ivl_14", 0 0, L_0x55ab20ebc9a0; 1 drivers
+v0x55ab20e4c310_0 .net *"_ivl_16", 0 0, L_0x55ab20ebcbf0; 1 drivers
+v0x55ab20e4c440_0 .net *"_ivl_3", 0 0, L_0x55ab20ebc1b0; 1 drivers
+v0x55ab20e4c520_0 .net *"_ivl_5", 0 0, L_0x55ab20ebc2f0; 1 drivers
+v0x55ab20e4c600_0 .net *"_ivl_7", 0 0, L_0x55ab20ebc4a0; 1 drivers
+v0x55ab20e4c6e0_0 .net *"_ivl_9", 0 0, L_0x55ab20ebc620; 1 drivers
+v0x55ab20e4c850_0 .net "a", 1 0, L_0x55ab20ebcd00; 1 drivers
+v0x55ab20e4c930_0 .net "b", 1 0, L_0x55ab20ebcda0; 1 drivers
+v0x55ab20e4ca10_0 .net "b0", 0 0, L_0x55ab20ebbfe0; 1 drivers
+v0x55ab20e4cad0_0 .net "f", 0 0, L_0x55ab20ebc140; 1 drivers
+v0x55ab20e4cb90_0 .net "g0", 0 0, L_0x55ab20ebc3e0; 1 drivers
+v0x55ab20e4cc50_0 .net "g1", 0 0, L_0x55ab20ebc6c0; 1 drivers
+v0x55ab20e4cd10_0 .net "y", 1 0, L_0x55ab20ebcab0; 1 drivers
+L_0x55ab20ebc050 .part L_0x55ab20ebcda0, 1, 1;
+L_0x55ab20ebc1b0 .part L_0x55ab20ebcda0, 0, 1;
+L_0x55ab20ebc2f0 .part L_0x55ab20ebcda0, 1, 1;
+L_0x55ab20ebc4a0 .part L_0x55ab20ebcda0, 0, 1;
+L_0x55ab20ebc620 .part L_0x55ab20ebcd00, 0, 1;
+L_0x55ab20ebc730 .part L_0x55ab20ebcda0, 0, 1;
+L_0x55ab20ebc860 .part L_0x55ab20ebcd00, 1, 1;
+L_0x55ab20ebcab0 .concat8 [ 1 1 0 0], L_0x55ab20ebc9a0, L_0x55ab20ebcbf0;
+S_0x55ab20e4ce70 .scope generate, "genblk7[6]" "genblk7[6]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e4d020 .param/l "j" 0 2 164, +C4<0110>;
+L_0x55ab20ebdba0 .part L_0x55ab20ebb860, 2, 2;
+L_0x55ab20ebdc40 .part L_0x55ab20ebb860, 6, 2;
+S_0x55ab20e4d0e0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e4ce70;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ebced0 .functor NOT 1, L_0x55ab20ebcf40, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ebcfe0 .functor AND 1, L_0x55ab20ebd050, L_0x55ab20ebd190, C4<1>, C4<1>;
+L_0x55ab20ebd280 .functor AND 1, L_0x55ab20ebced0, L_0x55ab20ebd340, L_0x55ab20ebd4c0, C4<1>;
+L_0x55ab20ebd560 .functor AND 1, L_0x55ab20ebced0, L_0x55ab20ebd5d0, L_0x55ab20ebd700, C4<1>;
+L_0x55ab20ebd840 .functor OR 1, L_0x55ab20ebcfe0, L_0x55ab20ebd280, C4<0>, C4<0>;
+L_0x55ab20ebda90 .functor OR 1, L_0x55ab20ebcfe0, L_0x55ab20ebd560, C4<0>, C4<0>;
+v0x55ab20e4d330_0 .net *"_ivl_1", 0 0, L_0x55ab20ebcf40; 1 drivers
+v0x55ab20e4d430_0 .net *"_ivl_11", 0 0, L_0x55ab20ebd5d0; 1 drivers
+v0x55ab20e4d510_0 .net *"_ivl_13", 0 0, L_0x55ab20ebd700; 1 drivers
+v0x55ab20e4d5d0_0 .net *"_ivl_14", 0 0, L_0x55ab20ebd840; 1 drivers
+v0x55ab20e4d6b0_0 .net *"_ivl_16", 0 0, L_0x55ab20ebda90; 1 drivers
+v0x55ab20e4d7e0_0 .net *"_ivl_3", 0 0, L_0x55ab20ebd050; 1 drivers
+v0x55ab20e4d8c0_0 .net *"_ivl_5", 0 0, L_0x55ab20ebd190; 1 drivers
+v0x55ab20e4d9a0_0 .net *"_ivl_7", 0 0, L_0x55ab20ebd340; 1 drivers
+v0x55ab20e4da80_0 .net *"_ivl_9", 0 0, L_0x55ab20ebd4c0; 1 drivers
+v0x55ab20e4dbf0_0 .net "a", 1 0, L_0x55ab20ebdba0; 1 drivers
+v0x55ab20e4dcd0_0 .net "b", 1 0, L_0x55ab20ebdc40; 1 drivers
+v0x55ab20e4ddb0_0 .net "b0", 0 0, L_0x55ab20ebced0; 1 drivers
+v0x55ab20e4de70_0 .net "f", 0 0, L_0x55ab20ebcfe0; 1 drivers
+v0x55ab20e4df30_0 .net "g0", 0 0, L_0x55ab20ebd280; 1 drivers
+v0x55ab20e4dff0_0 .net "g1", 0 0, L_0x55ab20ebd560; 1 drivers
+v0x55ab20e4e0b0_0 .net "y", 1 0, L_0x55ab20ebd950; 1 drivers
+L_0x55ab20ebcf40 .part L_0x55ab20ebdc40, 1, 1;
+L_0x55ab20ebd050 .part L_0x55ab20ebdc40, 0, 1;
+L_0x55ab20ebd190 .part L_0x55ab20ebdc40, 1, 1;
+L_0x55ab20ebd340 .part L_0x55ab20ebdc40, 0, 1;
+L_0x55ab20ebd4c0 .part L_0x55ab20ebdba0, 0, 1;
+L_0x55ab20ebd5d0 .part L_0x55ab20ebdc40, 0, 1;
+L_0x55ab20ebd700 .part L_0x55ab20ebdba0, 1, 1;
+L_0x55ab20ebd950 .concat8 [ 1 1 0 0], L_0x55ab20ebd840, L_0x55ab20ebda90;
+S_0x55ab20e4e210 .scope generate, "genblk7[8]" "genblk7[8]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e4e3a0 .param/l "j" 0 2 164, +C4<01000>;
+L_0x55ab20ebea00 .part L_0x55ab20ebb860, 4, 2;
+L_0x55ab20ebeaa0 .part L_0x55ab20ebb860, 8, 2;
+S_0x55ab20e4e460 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e4e210;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ebdce0 .functor NOT 1, L_0x55ab20ebdd50, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ebde40 .functor AND 1, L_0x55ab20ebdeb0, L_0x55ab20ebdff0, C4<1>, C4<1>;
+L_0x55ab20ebe0e0 .functor AND 1, L_0x55ab20ebdce0, L_0x55ab20ebe1a0, L_0x55ab20ebe320, C4<1>;
+L_0x55ab20ebe3c0 .functor AND 1, L_0x55ab20ebdce0, L_0x55ab20ebe430, L_0x55ab20ebe560, C4<1>;
+L_0x55ab20ebe6a0 .functor OR 1, L_0x55ab20ebde40, L_0x55ab20ebe0e0, C4<0>, C4<0>;
+L_0x55ab20ebe8f0 .functor OR 1, L_0x55ab20ebde40, L_0x55ab20ebe3c0, C4<0>, C4<0>;
+v0x55ab20e4e6b0_0 .net *"_ivl_1", 0 0, L_0x55ab20ebdd50; 1 drivers
+v0x55ab20e4e7b0_0 .net *"_ivl_11", 0 0, L_0x55ab20ebe430; 1 drivers
+v0x55ab20e4e890_0 .net *"_ivl_13", 0 0, L_0x55ab20ebe560; 1 drivers
+v0x55ab20e4e950_0 .net *"_ivl_14", 0 0, L_0x55ab20ebe6a0; 1 drivers
+v0x55ab20e4ea30_0 .net *"_ivl_16", 0 0, L_0x55ab20ebe8f0; 1 drivers
+v0x55ab20e4eb60_0 .net *"_ivl_3", 0 0, L_0x55ab20ebdeb0; 1 drivers
+v0x55ab20e4ec40_0 .net *"_ivl_5", 0 0, L_0x55ab20ebdff0; 1 drivers
+v0x55ab20e4ed20_0 .net *"_ivl_7", 0 0, L_0x55ab20ebe1a0; 1 drivers
+v0x55ab20e4ee00_0 .net *"_ivl_9", 0 0, L_0x55ab20ebe320; 1 drivers
+v0x55ab20e4ef70_0 .net "a", 1 0, L_0x55ab20ebea00; 1 drivers
+v0x55ab20e4f050_0 .net "b", 1 0, L_0x55ab20ebeaa0; 1 drivers
+v0x55ab20e4f130_0 .net "b0", 0 0, L_0x55ab20ebdce0; 1 drivers
+v0x55ab20e4f1f0_0 .net "f", 0 0, L_0x55ab20ebde40; 1 drivers
+v0x55ab20e4f2b0_0 .net "g0", 0 0, L_0x55ab20ebe0e0; 1 drivers
+v0x55ab20e4f370_0 .net "g1", 0 0, L_0x55ab20ebe3c0; 1 drivers
+v0x55ab20e4f430_0 .net "y", 1 0, L_0x55ab20ebe7b0; 1 drivers
+L_0x55ab20ebdd50 .part L_0x55ab20ebeaa0, 1, 1;
+L_0x55ab20ebdeb0 .part L_0x55ab20ebeaa0, 0, 1;
+L_0x55ab20ebdff0 .part L_0x55ab20ebeaa0, 1, 1;
+L_0x55ab20ebe1a0 .part L_0x55ab20ebeaa0, 0, 1;
+L_0x55ab20ebe320 .part L_0x55ab20ebea00, 0, 1;
+L_0x55ab20ebe430 .part L_0x55ab20ebeaa0, 0, 1;
+L_0x55ab20ebe560 .part L_0x55ab20ebea00, 1, 1;
+L_0x55ab20ebe7b0 .concat8 [ 1 1 0 0], L_0x55ab20ebe6a0, L_0x55ab20ebe8f0;
+S_0x55ab20e4f590 .scope generate, "genblk7[10]" "genblk7[10]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e4f720 .param/l "j" 0 2 164, +C4<01010>;
+L_0x55ab20ebf7d0 .part L_0x55ab20ebb860, 6, 2;
+L_0x55ab20ebf870 .part L_0x55ab20ebb860, 10, 2;
+S_0x55ab20e4f800 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e4f590;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ebeb40 .functor NOT 1, L_0x55ab20ebebb0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ebeca0 .functor AND 1, L_0x55ab20ebed10, L_0x55ab20ebee50, C4<1>, C4<1>;
+L_0x55ab20ebef40 .functor AND 1, L_0x55ab20ebeb40, L_0x55ab20ebf000, L_0x55ab20ebf0f0, C4<1>;
+L_0x55ab20ebf190 .functor AND 1, L_0x55ab20ebeb40, L_0x55ab20ebf200, L_0x55ab20ebf330, C4<1>;
+L_0x55ab20ebf470 .functor OR 1, L_0x55ab20ebeca0, L_0x55ab20ebef40, C4<0>, C4<0>;
+L_0x55ab20ebf6c0 .functor OR 1, L_0x55ab20ebeca0, L_0x55ab20ebf190, C4<0>, C4<0>;
+v0x55ab20e4fa50_0 .net *"_ivl_1", 0 0, L_0x55ab20ebebb0; 1 drivers
+v0x55ab20e4fb50_0 .net *"_ivl_11", 0 0, L_0x55ab20ebf200; 1 drivers
+v0x55ab20e4fc30_0 .net *"_ivl_13", 0 0, L_0x55ab20ebf330; 1 drivers
+v0x55ab20e4fcf0_0 .net *"_ivl_14", 0 0, L_0x55ab20ebf470; 1 drivers
+v0x55ab20e4fdd0_0 .net *"_ivl_16", 0 0, L_0x55ab20ebf6c0; 1 drivers
+v0x55ab20e4ff00_0 .net *"_ivl_3", 0 0, L_0x55ab20ebed10; 1 drivers
+v0x55ab20e4ffe0_0 .net *"_ivl_5", 0 0, L_0x55ab20ebee50; 1 drivers
+v0x55ab20e500c0_0 .net *"_ivl_7", 0 0, L_0x55ab20ebf000; 1 drivers
+v0x55ab20e501a0_0 .net *"_ivl_9", 0 0, L_0x55ab20ebf0f0; 1 drivers
+v0x55ab20e50310_0 .net "a", 1 0, L_0x55ab20ebf7d0; 1 drivers
+v0x55ab20e503f0_0 .net "b", 1 0, L_0x55ab20ebf870; 1 drivers
+v0x55ab20e504d0_0 .net "b0", 0 0, L_0x55ab20ebeb40; 1 drivers
+v0x55ab20e50590_0 .net "f", 0 0, L_0x55ab20ebeca0; 1 drivers
+v0x55ab20e50650_0 .net "g0", 0 0, L_0x55ab20ebef40; 1 drivers
+v0x55ab20e50710_0 .net "g1", 0 0, L_0x55ab20ebf190; 1 drivers
+v0x55ab20e507d0_0 .net "y", 1 0, L_0x55ab20ebf580; 1 drivers
+L_0x55ab20ebebb0 .part L_0x55ab20ebf870, 1, 1;
+L_0x55ab20ebed10 .part L_0x55ab20ebf870, 0, 1;
+L_0x55ab20ebee50 .part L_0x55ab20ebf870, 1, 1;
+L_0x55ab20ebf000 .part L_0x55ab20ebf870, 0, 1;
+L_0x55ab20ebf0f0 .part L_0x55ab20ebf7d0, 0, 1;
+L_0x55ab20ebf200 .part L_0x55ab20ebf870, 0, 1;
+L_0x55ab20ebf330 .part L_0x55ab20ebf7d0, 1, 1;
+L_0x55ab20ebf580 .concat8 [ 1 1 0 0], L_0x55ab20ebf470, L_0x55ab20ebf6c0;
+S_0x55ab20e50930 .scope generate, "genblk7[12]" "genblk7[12]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e50b10 .param/l "j" 0 2 164, +C4<01100>;
+L_0x55ab20ec0630 .part L_0x55ab20ebb860, 8, 2;
+L_0x55ab20ec06d0 .part L_0x55ab20ebb860, 12, 2;
+S_0x55ab20e50bf0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e50930;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ebf910 .functor NOT 1, L_0x55ab20ebf980, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ebfa70 .functor AND 1, L_0x55ab20ebfae0, L_0x55ab20ebfc20, C4<1>, C4<1>;
+L_0x55ab20ebfd10 .functor AND 1, L_0x55ab20ebf910, L_0x55ab20ebfdd0, L_0x55ab20ebff50, C4<1>;
+L_0x55ab20ebfff0 .functor AND 1, L_0x55ab20ebf910, L_0x55ab20ec0060, L_0x55ab20ec0190, C4<1>;
+L_0x55ab20ec02d0 .functor OR 1, L_0x55ab20ebfa70, L_0x55ab20ebfd10, C4<0>, C4<0>;
+L_0x55ab20ec0520 .functor OR 1, L_0x55ab20ebfa70, L_0x55ab20ebfff0, C4<0>, C4<0>;
+v0x55ab20e50e40_0 .net *"_ivl_1", 0 0, L_0x55ab20ebf980; 1 drivers
+v0x55ab20e50f40_0 .net *"_ivl_11", 0 0, L_0x55ab20ec0060; 1 drivers
+v0x55ab20e51020_0 .net *"_ivl_13", 0 0, L_0x55ab20ec0190; 1 drivers
+v0x55ab20e510e0_0 .net *"_ivl_14", 0 0, L_0x55ab20ec02d0; 1 drivers
+v0x55ab20e511c0_0 .net *"_ivl_16", 0 0, L_0x55ab20ec0520; 1 drivers
+v0x55ab20e512f0_0 .net *"_ivl_3", 0 0, L_0x55ab20ebfae0; 1 drivers
+v0x55ab20e513d0_0 .net *"_ivl_5", 0 0, L_0x55ab20ebfc20; 1 drivers
+v0x55ab20e514b0_0 .net *"_ivl_7", 0 0, L_0x55ab20ebfdd0; 1 drivers
+v0x55ab20e51590_0 .net *"_ivl_9", 0 0, L_0x55ab20ebff50; 1 drivers
+v0x55ab20e51700_0 .net "a", 1 0, L_0x55ab20ec0630; 1 drivers
+v0x55ab20e517e0_0 .net "b", 1 0, L_0x55ab20ec06d0; 1 drivers
+v0x55ab20e518c0_0 .net "b0", 0 0, L_0x55ab20ebf910; 1 drivers
+v0x55ab20e51980_0 .net "f", 0 0, L_0x55ab20ebfa70; 1 drivers
+v0x55ab20e51a40_0 .net "g0", 0 0, L_0x55ab20ebfd10; 1 drivers
+v0x55ab20e51b00_0 .net "g1", 0 0, L_0x55ab20ebfff0; 1 drivers
+v0x55ab20e51bc0_0 .net "y", 1 0, L_0x55ab20ec03e0; 1 drivers
+L_0x55ab20ebf980 .part L_0x55ab20ec06d0, 1, 1;
+L_0x55ab20ebfae0 .part L_0x55ab20ec06d0, 0, 1;
+L_0x55ab20ebfc20 .part L_0x55ab20ec06d0, 1, 1;
+L_0x55ab20ebfdd0 .part L_0x55ab20ec06d0, 0, 1;
+L_0x55ab20ebff50 .part L_0x55ab20ec0630, 0, 1;
+L_0x55ab20ec0060 .part L_0x55ab20ec06d0, 0, 1;
+L_0x55ab20ec0190 .part L_0x55ab20ec0630, 1, 1;
+L_0x55ab20ec03e0 .concat8 [ 1 1 0 0], L_0x55ab20ec02d0, L_0x55ab20ec0520;
+S_0x55ab20e51d20 .scope generate, "genblk7[14]" "genblk7[14]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e51eb0 .param/l "j" 0 2 164, +C4<01110>;
+L_0x55ab20ec14c0 .part L_0x55ab20ebb860, 10, 2;
+L_0x55ab20ec1560 .part L_0x55ab20ebb860, 14, 2;
+S_0x55ab20e51f90 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e51d20;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ec0770 .functor NOT 1, L_0x55ab20ec07e0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ec08d0 .functor AND 1, L_0x55ab20ec0940, L_0x55ab20ec0a80, C4<1>, C4<1>;
+L_0x55ab20ec0b70 .functor AND 1, L_0x55ab20ec0770, L_0x55ab20ec0c30, L_0x55ab20ec0db0, C4<1>;
+L_0x55ab20ec0e50 .functor AND 1, L_0x55ab20ec0770, L_0x55ab20ec0ef0, L_0x55ab20ec1020, C4<1>;
+L_0x55ab20ec1160 .functor OR 1, L_0x55ab20ec08d0, L_0x55ab20ec0b70, C4<0>, C4<0>;
+L_0x55ab20ec13b0 .functor OR 1, L_0x55ab20ec08d0, L_0x55ab20ec0e50, C4<0>, C4<0>;
+v0x55ab20e521e0_0 .net *"_ivl_1", 0 0, L_0x55ab20ec07e0; 1 drivers
+v0x55ab20e522e0_0 .net *"_ivl_11", 0 0, L_0x55ab20ec0ef0; 1 drivers
+v0x55ab20e523c0_0 .net *"_ivl_13", 0 0, L_0x55ab20ec1020; 1 drivers
+v0x55ab20e52480_0 .net *"_ivl_14", 0 0, L_0x55ab20ec1160; 1 drivers
+v0x55ab20e52560_0 .net *"_ivl_16", 0 0, L_0x55ab20ec13b0; 1 drivers
+v0x55ab20e52690_0 .net *"_ivl_3", 0 0, L_0x55ab20ec0940; 1 drivers
+v0x55ab20e52770_0 .net *"_ivl_5", 0 0, L_0x55ab20ec0a80; 1 drivers
+v0x55ab20e52850_0 .net *"_ivl_7", 0 0, L_0x55ab20ec0c30; 1 drivers
+v0x55ab20e52930_0 .net *"_ivl_9", 0 0, L_0x55ab20ec0db0; 1 drivers
+v0x55ab20e52aa0_0 .net "a", 1 0, L_0x55ab20ec14c0; 1 drivers
+v0x55ab20e52b80_0 .net "b", 1 0, L_0x55ab20ec1560; 1 drivers
+v0x55ab20e52c60_0 .net "b0", 0 0, L_0x55ab20ec0770; 1 drivers
+v0x55ab20e52d20_0 .net "f", 0 0, L_0x55ab20ec08d0; 1 drivers
+v0x55ab20e52de0_0 .net "g0", 0 0, L_0x55ab20ec0b70; 1 drivers
+v0x55ab20e52ea0_0 .net "g1", 0 0, L_0x55ab20ec0e50; 1 drivers
+v0x55ab20e52f60_0 .net "y", 1 0, L_0x55ab20ec1270; 1 drivers
+L_0x55ab20ec07e0 .part L_0x55ab20ec1560, 1, 1;
+L_0x55ab20ec0940 .part L_0x55ab20ec1560, 0, 1;
+L_0x55ab20ec0a80 .part L_0x55ab20ec1560, 1, 1;
+L_0x55ab20ec0c30 .part L_0x55ab20ec1560, 0, 1;
+L_0x55ab20ec0db0 .part L_0x55ab20ec14c0, 0, 1;
+L_0x55ab20ec0ef0 .part L_0x55ab20ec1560, 0, 1;
+L_0x55ab20ec1020 .part L_0x55ab20ec14c0, 1, 1;
+L_0x55ab20ec1270 .concat8 [ 1 1 0 0], L_0x55ab20ec1160, L_0x55ab20ec13b0;
+S_0x55ab20e530c0 .scope generate, "genblk7[16]" "genblk7[16]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e53250 .param/l "j" 0 2 164, +C4<010000>;
+L_0x55ab20ec2380 .part L_0x55ab20ebb860, 12, 2;
+L_0x55ab20ec2420 .part L_0x55ab20ebb860, 16, 2;
+S_0x55ab20e53330 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e530c0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ec1600 .functor NOT 1, L_0x55ab20ec1670, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ec1760 .functor AND 1, L_0x55ab20ec17d0, L_0x55ab20ec1910, C4<1>, C4<1>;
+L_0x55ab20ec1a00 .functor AND 1, L_0x55ab20ec1600, L_0x55ab20ec1ac0, L_0x55ab20ec1c40, C4<1>;
+L_0x55ab20ec1ce0 .functor AND 1, L_0x55ab20ec1600, L_0x55ab20ec1db0, L_0x55ab20ec1ee0, C4<1>;
+L_0x55ab20ec2020 .functor OR 1, L_0x55ab20ec1760, L_0x55ab20ec1a00, C4<0>, C4<0>;
+L_0x55ab20ec2270 .functor OR 1, L_0x55ab20ec1760, L_0x55ab20ec1ce0, C4<0>, C4<0>;
+v0x55ab20e53580_0 .net *"_ivl_1", 0 0, L_0x55ab20ec1670; 1 drivers
+v0x55ab20e53680_0 .net *"_ivl_11", 0 0, L_0x55ab20ec1db0; 1 drivers
+v0x55ab20e53760_0 .net *"_ivl_13", 0 0, L_0x55ab20ec1ee0; 1 drivers
+v0x55ab20e53820_0 .net *"_ivl_14", 0 0, L_0x55ab20ec2020; 1 drivers
+v0x55ab20e53900_0 .net *"_ivl_16", 0 0, L_0x55ab20ec2270; 1 drivers
+v0x55ab20e53a30_0 .net *"_ivl_3", 0 0, L_0x55ab20ec17d0; 1 drivers
+v0x55ab20e53b10_0 .net *"_ivl_5", 0 0, L_0x55ab20ec1910; 1 drivers
+v0x55ab20e53bf0_0 .net *"_ivl_7", 0 0, L_0x55ab20ec1ac0; 1 drivers
+v0x55ab20e53cd0_0 .net *"_ivl_9", 0 0, L_0x55ab20ec1c40; 1 drivers
+v0x55ab20e53e40_0 .net "a", 1 0, L_0x55ab20ec2380; 1 drivers
+v0x55ab20e53f20_0 .net "b", 1 0, L_0x55ab20ec2420; 1 drivers
+v0x55ab20e54000_0 .net "b0", 0 0, L_0x55ab20ec1600; 1 drivers
+v0x55ab20e540c0_0 .net "f", 0 0, L_0x55ab20ec1760; 1 drivers
+v0x55ab20e54180_0 .net "g0", 0 0, L_0x55ab20ec1a00; 1 drivers
+v0x55ab20e54240_0 .net "g1", 0 0, L_0x55ab20ec1ce0; 1 drivers
+v0x55ab20e54300_0 .net "y", 1 0, L_0x55ab20ec2130; 1 drivers
+L_0x55ab20ec1670 .part L_0x55ab20ec2420, 1, 1;
+L_0x55ab20ec17d0 .part L_0x55ab20ec2420, 0, 1;
+L_0x55ab20ec1910 .part L_0x55ab20ec2420, 1, 1;
+L_0x55ab20ec1ac0 .part L_0x55ab20ec2420, 0, 1;
+L_0x55ab20ec1c40 .part L_0x55ab20ec2380, 0, 1;
+L_0x55ab20ec1db0 .part L_0x55ab20ec2420, 0, 1;
+L_0x55ab20ec1ee0 .part L_0x55ab20ec2380, 1, 1;
+L_0x55ab20ec2130 .concat8 [ 1 1 0 0], L_0x55ab20ec2020, L_0x55ab20ec2270;
+S_0x55ab20e54460 .scope generate, "genblk7[18]" "genblk7[18]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e545f0 .param/l "j" 0 2 164, +C4<010010>;
+L_0x55ab20ec3270 .part L_0x55ab20ebb860, 14, 2;
+L_0x55ab20ec3310 .part L_0x55ab20ebb860, 18, 2;
+S_0x55ab20e546d0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e54460;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ec24c0 .functor NOT 1, L_0x55ab20ec2530, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ec2620 .functor AND 1, L_0x55ab20ec2690, L_0x55ab20ec27d0, C4<1>, C4<1>;
+L_0x55ab20ec28c0 .functor AND 1, L_0x55ab20ec24c0, L_0x55ab20ec2980, L_0x55ab20ec2b30, C4<1>;
+L_0x55ab20ec2bd0 .functor AND 1, L_0x55ab20ec24c0, L_0x55ab20ec2ca0, L_0x55ab20ec2dd0, C4<1>;
+L_0x55ab20ec2f10 .functor OR 1, L_0x55ab20ec2620, L_0x55ab20ec28c0, C4<0>, C4<0>;
+L_0x55ab20ec3160 .functor OR 1, L_0x55ab20ec2620, L_0x55ab20ec2bd0, C4<0>, C4<0>;
+v0x55ab20e54920_0 .net *"_ivl_1", 0 0, L_0x55ab20ec2530; 1 drivers
+v0x55ab20e54a20_0 .net *"_ivl_11", 0 0, L_0x55ab20ec2ca0; 1 drivers
+v0x55ab20e54b00_0 .net *"_ivl_13", 0 0, L_0x55ab20ec2dd0; 1 drivers
+v0x55ab20e54bc0_0 .net *"_ivl_14", 0 0, L_0x55ab20ec2f10; 1 drivers
+v0x55ab20e54ca0_0 .net *"_ivl_16", 0 0, L_0x55ab20ec3160; 1 drivers
+v0x55ab20e54dd0_0 .net *"_ivl_3", 0 0, L_0x55ab20ec2690; 1 drivers
+v0x55ab20e54eb0_0 .net *"_ivl_5", 0 0, L_0x55ab20ec27d0; 1 drivers
+v0x55ab20e54f90_0 .net *"_ivl_7", 0 0, L_0x55ab20ec2980; 1 drivers
+v0x55ab20e55070_0 .net *"_ivl_9", 0 0, L_0x55ab20ec2b30; 1 drivers
+v0x55ab20e551e0_0 .net "a", 1 0, L_0x55ab20ec3270; 1 drivers
+v0x55ab20e552c0_0 .net "b", 1 0, L_0x55ab20ec3310; 1 drivers
+v0x55ab20e553a0_0 .net "b0", 0 0, L_0x55ab20ec24c0; 1 drivers
+v0x55ab20e55460_0 .net "f", 0 0, L_0x55ab20ec2620; 1 drivers
+v0x55ab20e55520_0 .net "g0", 0 0, L_0x55ab20ec28c0; 1 drivers
+v0x55ab20e555e0_0 .net "g1", 0 0, L_0x55ab20ec2bd0; 1 drivers
+v0x55ab20e556a0_0 .net "y", 1 0, L_0x55ab20ec3020; 1 drivers
+L_0x55ab20ec2530 .part L_0x55ab20ec3310, 1, 1;
+L_0x55ab20ec2690 .part L_0x55ab20ec3310, 0, 1;
+L_0x55ab20ec27d0 .part L_0x55ab20ec3310, 1, 1;
+L_0x55ab20ec2980 .part L_0x55ab20ec3310, 0, 1;
+L_0x55ab20ec2b30 .part L_0x55ab20ec3270, 0, 1;
+L_0x55ab20ec2ca0 .part L_0x55ab20ec3310, 0, 1;
+L_0x55ab20ec2dd0 .part L_0x55ab20ec3270, 1, 1;
+L_0x55ab20ec3020 .concat8 [ 1 1 0 0], L_0x55ab20ec2f10, L_0x55ab20ec3160;
+S_0x55ab20e55800 .scope generate, "genblk7[20]" "genblk7[20]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e50ac0 .param/l "j" 0 2 164, +C4<010100>;
+L_0x55ab20ec4160 .part L_0x55ab20ebb860, 16, 2;
+L_0x55ab20ec4200 .part L_0x55ab20ebb860, 20, 2;
+S_0x55ab20e55ab0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e55800;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ec33b0 .functor NOT 1, L_0x55ab20ec3420, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ec3510 .functor AND 1, L_0x55ab20ec3580, L_0x55ab20ec36c0, C4<1>, C4<1>;
+L_0x55ab20ec37b0 .functor AND 1, L_0x55ab20ec33b0, L_0x55ab20ec3870, L_0x55ab20ec3a20, C4<1>;
+L_0x55ab20ec3ac0 .functor AND 1, L_0x55ab20ec33b0, L_0x55ab20ec3b90, L_0x55ab20ec3cc0, C4<1>;
+L_0x55ab20ec3e00 .functor OR 1, L_0x55ab20ec3510, L_0x55ab20ec37b0, C4<0>, C4<0>;
+L_0x55ab20ec4050 .functor OR 1, L_0x55ab20ec3510, L_0x55ab20ec3ac0, C4<0>, C4<0>;
+v0x55ab20e55d00_0 .net *"_ivl_1", 0 0, L_0x55ab20ec3420; 1 drivers
+v0x55ab20e55e00_0 .net *"_ivl_11", 0 0, L_0x55ab20ec3b90; 1 drivers
+v0x55ab20e55ee0_0 .net *"_ivl_13", 0 0, L_0x55ab20ec3cc0; 1 drivers
+v0x55ab20e55fa0_0 .net *"_ivl_14", 0 0, L_0x55ab20ec3e00; 1 drivers
+v0x55ab20e56080_0 .net *"_ivl_16", 0 0, L_0x55ab20ec4050; 1 drivers
+v0x55ab20e561b0_0 .net *"_ivl_3", 0 0, L_0x55ab20ec3580; 1 drivers
+v0x55ab20e56290_0 .net *"_ivl_5", 0 0, L_0x55ab20ec36c0; 1 drivers
+v0x55ab20e56370_0 .net *"_ivl_7", 0 0, L_0x55ab20ec3870; 1 drivers
+v0x55ab20e56450_0 .net *"_ivl_9", 0 0, L_0x55ab20ec3a20; 1 drivers
+v0x55ab20e565c0_0 .net "a", 1 0, L_0x55ab20ec4160; 1 drivers
+v0x55ab20e566a0_0 .net "b", 1 0, L_0x55ab20ec4200; 1 drivers
+v0x55ab20e56780_0 .net "b0", 0 0, L_0x55ab20ec33b0; 1 drivers
+v0x55ab20e56840_0 .net "f", 0 0, L_0x55ab20ec3510; 1 drivers
+v0x55ab20e56900_0 .net "g0", 0 0, L_0x55ab20ec37b0; 1 drivers
+v0x55ab20e569c0_0 .net "g1", 0 0, L_0x55ab20ec3ac0; 1 drivers
+v0x55ab20e56a80_0 .net "y", 1 0, L_0x55ab20ec3f10; 1 drivers
+L_0x55ab20ec3420 .part L_0x55ab20ec4200, 1, 1;
+L_0x55ab20ec3580 .part L_0x55ab20ec4200, 0, 1;
+L_0x55ab20ec36c0 .part L_0x55ab20ec4200, 1, 1;
+L_0x55ab20ec3870 .part L_0x55ab20ec4200, 0, 1;
+L_0x55ab20ec3a20 .part L_0x55ab20ec4160, 0, 1;
+L_0x55ab20ec3b90 .part L_0x55ab20ec4200, 0, 1;
+L_0x55ab20ec3cc0 .part L_0x55ab20ec4160, 1, 1;
+L_0x55ab20ec3f10 .concat8 [ 1 1 0 0], L_0x55ab20ec3e00, L_0x55ab20ec4050;
+S_0x55ab20e56be0 .scope generate, "genblk7[22]" "genblk7[22]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e56d70 .param/l "j" 0 2 164, +C4<010110>;
+L_0x55ab20ec5050 .part L_0x55ab20ebb860, 18, 2;
+L_0x55ab20ec50f0 .part L_0x55ab20ebb860, 22, 2;
+S_0x55ab20e56e50 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e56be0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ec42a0 .functor NOT 1, L_0x55ab20ec4310, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ec4400 .functor AND 1, L_0x55ab20ec4470, L_0x55ab20ec45b0, C4<1>, C4<1>;
+L_0x55ab20ec46a0 .functor AND 1, L_0x55ab20ec42a0, L_0x55ab20ec4760, L_0x55ab20ec4910, C4<1>;
+L_0x55ab20ec49b0 .functor AND 1, L_0x55ab20ec42a0, L_0x55ab20ec4a80, L_0x55ab20ec4bb0, C4<1>;
+L_0x55ab20ec4cf0 .functor OR 1, L_0x55ab20ec4400, L_0x55ab20ec46a0, C4<0>, C4<0>;
+L_0x55ab20ec4f40 .functor OR 1, L_0x55ab20ec4400, L_0x55ab20ec49b0, C4<0>, C4<0>;
+v0x55ab20e570a0_0 .net *"_ivl_1", 0 0, L_0x55ab20ec4310; 1 drivers
+v0x55ab20e571a0_0 .net *"_ivl_11", 0 0, L_0x55ab20ec4a80; 1 drivers
+v0x55ab20e57280_0 .net *"_ivl_13", 0 0, L_0x55ab20ec4bb0; 1 drivers
+v0x55ab20e57340_0 .net *"_ivl_14", 0 0, L_0x55ab20ec4cf0; 1 drivers
+v0x55ab20e57420_0 .net *"_ivl_16", 0 0, L_0x55ab20ec4f40; 1 drivers
+v0x55ab20e57550_0 .net *"_ivl_3", 0 0, L_0x55ab20ec4470; 1 drivers
+v0x55ab20e57630_0 .net *"_ivl_5", 0 0, L_0x55ab20ec45b0; 1 drivers
+v0x55ab20e57710_0 .net *"_ivl_7", 0 0, L_0x55ab20ec4760; 1 drivers
+v0x55ab20e577f0_0 .net *"_ivl_9", 0 0, L_0x55ab20ec4910; 1 drivers
+v0x55ab20e57960_0 .net "a", 1 0, L_0x55ab20ec5050; 1 drivers
+v0x55ab20e57a40_0 .net "b", 1 0, L_0x55ab20ec50f0; 1 drivers
+v0x55ab20e57b20_0 .net "b0", 0 0, L_0x55ab20ec42a0; 1 drivers
+v0x55ab20e57be0_0 .net "f", 0 0, L_0x55ab20ec4400; 1 drivers
+v0x55ab20e57ca0_0 .net "g0", 0 0, L_0x55ab20ec46a0; 1 drivers
+v0x55ab20e57d60_0 .net "g1", 0 0, L_0x55ab20ec49b0; 1 drivers
+v0x55ab20e57e20_0 .net "y", 1 0, L_0x55ab20ec4e00; 1 drivers
+L_0x55ab20ec4310 .part L_0x55ab20ec50f0, 1, 1;
+L_0x55ab20ec4470 .part L_0x55ab20ec50f0, 0, 1;
+L_0x55ab20ec45b0 .part L_0x55ab20ec50f0, 1, 1;
+L_0x55ab20ec4760 .part L_0x55ab20ec50f0, 0, 1;
+L_0x55ab20ec4910 .part L_0x55ab20ec5050, 0, 1;
+L_0x55ab20ec4a80 .part L_0x55ab20ec50f0, 0, 1;
+L_0x55ab20ec4bb0 .part L_0x55ab20ec5050, 1, 1;
+L_0x55ab20ec4e00 .concat8 [ 1 1 0 0], L_0x55ab20ec4cf0, L_0x55ab20ec4f40;
+S_0x55ab20e57f80 .scope generate, "genblk7[24]" "genblk7[24]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e58110 .param/l "j" 0 2 164, +C4<011000>;
+L_0x55ab20ec5f40 .part L_0x55ab20ebb860, 20, 2;
+L_0x55ab20ec5fe0 .part L_0x55ab20ebb860, 24, 2;
+S_0x55ab20e581f0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e57f80;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ec5190 .functor NOT 1, L_0x55ab20ec5200, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ec52f0 .functor AND 1, L_0x55ab20ec5360, L_0x55ab20ec54a0, C4<1>, C4<1>;
+L_0x55ab20ec5590 .functor AND 1, L_0x55ab20ec5190, L_0x55ab20ec5650, L_0x55ab20ec5800, C4<1>;
+L_0x55ab20ec58a0 .functor AND 1, L_0x55ab20ec5190, L_0x55ab20ec5970, L_0x55ab20ec5aa0, C4<1>;
+L_0x55ab20ec5be0 .functor OR 1, L_0x55ab20ec52f0, L_0x55ab20ec5590, C4<0>, C4<0>;
+L_0x55ab20ec5e30 .functor OR 1, L_0x55ab20ec52f0, L_0x55ab20ec58a0, C4<0>, C4<0>;
+v0x55ab20e58440_0 .net *"_ivl_1", 0 0, L_0x55ab20ec5200; 1 drivers
+v0x55ab20e58540_0 .net *"_ivl_11", 0 0, L_0x55ab20ec5970; 1 drivers
+v0x55ab20e58620_0 .net *"_ivl_13", 0 0, L_0x55ab20ec5aa0; 1 drivers
+v0x55ab20e586e0_0 .net *"_ivl_14", 0 0, L_0x55ab20ec5be0; 1 drivers
+v0x55ab20e587c0_0 .net *"_ivl_16", 0 0, L_0x55ab20ec5e30; 1 drivers
+v0x55ab20e588f0_0 .net *"_ivl_3", 0 0, L_0x55ab20ec5360; 1 drivers
+v0x55ab20e589d0_0 .net *"_ivl_5", 0 0, L_0x55ab20ec54a0; 1 drivers
+v0x55ab20e58ab0_0 .net *"_ivl_7", 0 0, L_0x55ab20ec5650; 1 drivers
+v0x55ab20e58b90_0 .net *"_ivl_9", 0 0, L_0x55ab20ec5800; 1 drivers
+v0x55ab20e58d00_0 .net "a", 1 0, L_0x55ab20ec5f40; 1 drivers
+v0x55ab20e58de0_0 .net "b", 1 0, L_0x55ab20ec5fe0; 1 drivers
+v0x55ab20e58ec0_0 .net "b0", 0 0, L_0x55ab20ec5190; 1 drivers
+v0x55ab20e58f80_0 .net "f", 0 0, L_0x55ab20ec52f0; 1 drivers
+v0x55ab20e59040_0 .net "g0", 0 0, L_0x55ab20ec5590; 1 drivers
+v0x55ab20e59100_0 .net "g1", 0 0, L_0x55ab20ec58a0; 1 drivers
+v0x55ab20e591c0_0 .net "y", 1 0, L_0x55ab20ec5cf0; 1 drivers
+L_0x55ab20ec5200 .part L_0x55ab20ec5fe0, 1, 1;
+L_0x55ab20ec5360 .part L_0x55ab20ec5fe0, 0, 1;
+L_0x55ab20ec54a0 .part L_0x55ab20ec5fe0, 1, 1;
+L_0x55ab20ec5650 .part L_0x55ab20ec5fe0, 0, 1;
+L_0x55ab20ec5800 .part L_0x55ab20ec5f40, 0, 1;
+L_0x55ab20ec5970 .part L_0x55ab20ec5fe0, 0, 1;
+L_0x55ab20ec5aa0 .part L_0x55ab20ec5f40, 1, 1;
+L_0x55ab20ec5cf0 .concat8 [ 1 1 0 0], L_0x55ab20ec5be0, L_0x55ab20ec5e30;
+S_0x55ab20e59320 .scope generate, "genblk7[26]" "genblk7[26]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e594b0 .param/l "j" 0 2 164, +C4<011010>;
+L_0x55ab20ec6e30 .part L_0x55ab20ebb860, 22, 2;
+L_0x55ab20ec6ed0 .part L_0x55ab20ebb860, 26, 2;
+S_0x55ab20e59590 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e59320;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ec6080 .functor NOT 1, L_0x55ab20ec60f0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ec61e0 .functor AND 1, L_0x55ab20ec6250, L_0x55ab20ec6390, C4<1>, C4<1>;
+L_0x55ab20ec6480 .functor AND 1, L_0x55ab20ec6080, L_0x55ab20ec6540, L_0x55ab20ec66f0, C4<1>;
+L_0x55ab20ec6790 .functor AND 1, L_0x55ab20ec6080, L_0x55ab20ec6860, L_0x55ab20ec6990, C4<1>;
+L_0x55ab20ec6ad0 .functor OR 1, L_0x55ab20ec61e0, L_0x55ab20ec6480, C4<0>, C4<0>;
+L_0x55ab20ec6d20 .functor OR 1, L_0x55ab20ec61e0, L_0x55ab20ec6790, C4<0>, C4<0>;
+v0x55ab20e597e0_0 .net *"_ivl_1", 0 0, L_0x55ab20ec60f0; 1 drivers
+v0x55ab20e598e0_0 .net *"_ivl_11", 0 0, L_0x55ab20ec6860; 1 drivers
+v0x55ab20e599c0_0 .net *"_ivl_13", 0 0, L_0x55ab20ec6990; 1 drivers
+v0x55ab20e59a80_0 .net *"_ivl_14", 0 0, L_0x55ab20ec6ad0; 1 drivers
+v0x55ab20e59b60_0 .net *"_ivl_16", 0 0, L_0x55ab20ec6d20; 1 drivers
+v0x55ab20e59c90_0 .net *"_ivl_3", 0 0, L_0x55ab20ec6250; 1 drivers
+v0x55ab20e59d70_0 .net *"_ivl_5", 0 0, L_0x55ab20ec6390; 1 drivers
+v0x55ab20e59e50_0 .net *"_ivl_7", 0 0, L_0x55ab20ec6540; 1 drivers
+v0x55ab20e59f30_0 .net *"_ivl_9", 0 0, L_0x55ab20ec66f0; 1 drivers
+v0x55ab20e5a0a0_0 .net "a", 1 0, L_0x55ab20ec6e30; 1 drivers
+v0x55ab20e5a180_0 .net "b", 1 0, L_0x55ab20ec6ed0; 1 drivers
+v0x55ab20e5a260_0 .net "b0", 0 0, L_0x55ab20ec6080; 1 drivers
+v0x55ab20e5a320_0 .net "f", 0 0, L_0x55ab20ec61e0; 1 drivers
+v0x55ab20e5a3e0_0 .net "g0", 0 0, L_0x55ab20ec6480; 1 drivers
+v0x55ab20e5a4a0_0 .net "g1", 0 0, L_0x55ab20ec6790; 1 drivers
+v0x55ab20e5a560_0 .net "y", 1 0, L_0x55ab20ec6be0; 1 drivers
+L_0x55ab20ec60f0 .part L_0x55ab20ec6ed0, 1, 1;
+L_0x55ab20ec6250 .part L_0x55ab20ec6ed0, 0, 1;
+L_0x55ab20ec6390 .part L_0x55ab20ec6ed0, 1, 1;
+L_0x55ab20ec6540 .part L_0x55ab20ec6ed0, 0, 1;
+L_0x55ab20ec66f0 .part L_0x55ab20ec6e30, 0, 1;
+L_0x55ab20ec6860 .part L_0x55ab20ec6ed0, 0, 1;
+L_0x55ab20ec6990 .part L_0x55ab20ec6e30, 1, 1;
+L_0x55ab20ec6be0 .concat8 [ 1 1 0 0], L_0x55ab20ec6ad0, L_0x55ab20ec6d20;
+S_0x55ab20e5a6c0 .scope generate, "genblk7[28]" "genblk7[28]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e5a850 .param/l "j" 0 2 164, +C4<011100>;
+L_0x55ab20ec7d20 .part L_0x55ab20ebb860, 24, 2;
+L_0x55ab20ec7dc0 .part L_0x55ab20ebb860, 28, 2;
+S_0x55ab20e5a930 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e5a6c0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ec6f70 .functor NOT 1, L_0x55ab20ec6fe0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ec70d0 .functor AND 1, L_0x55ab20ec7140, L_0x55ab20ec7280, C4<1>, C4<1>;
+L_0x55ab20ec7370 .functor AND 1, L_0x55ab20ec6f70, L_0x55ab20ec7430, L_0x55ab20ec75e0, C4<1>;
+L_0x55ab20ec7680 .functor AND 1, L_0x55ab20ec6f70, L_0x55ab20ec7750, L_0x55ab20ec7880, C4<1>;
+L_0x55ab20ec79c0 .functor OR 1, L_0x55ab20ec70d0, L_0x55ab20ec7370, C4<0>, C4<0>;
+L_0x55ab20ec7c10 .functor OR 1, L_0x55ab20ec70d0, L_0x55ab20ec7680, C4<0>, C4<0>;
+v0x55ab20e5ab80_0 .net *"_ivl_1", 0 0, L_0x55ab20ec6fe0; 1 drivers
+v0x55ab20e5ac80_0 .net *"_ivl_11", 0 0, L_0x55ab20ec7750; 1 drivers
+v0x55ab20e5ad60_0 .net *"_ivl_13", 0 0, L_0x55ab20ec7880; 1 drivers
+v0x55ab20e5ae20_0 .net *"_ivl_14", 0 0, L_0x55ab20ec79c0; 1 drivers
+v0x55ab20e5af00_0 .net *"_ivl_16", 0 0, L_0x55ab20ec7c10; 1 drivers
+v0x55ab20e5b030_0 .net *"_ivl_3", 0 0, L_0x55ab20ec7140; 1 drivers
+v0x55ab20e5b110_0 .net *"_ivl_5", 0 0, L_0x55ab20ec7280; 1 drivers
+v0x55ab20e5b1f0_0 .net *"_ivl_7", 0 0, L_0x55ab20ec7430; 1 drivers
+v0x55ab20e5b2d0_0 .net *"_ivl_9", 0 0, L_0x55ab20ec75e0; 1 drivers
+v0x55ab20e5b440_0 .net "a", 1 0, L_0x55ab20ec7d20; 1 drivers
+v0x55ab20e5b520_0 .net "b", 1 0, L_0x55ab20ec7dc0; 1 drivers
+v0x55ab20e5b600_0 .net "b0", 0 0, L_0x55ab20ec6f70; 1 drivers
+v0x55ab20e5b6c0_0 .net "f", 0 0, L_0x55ab20ec70d0; 1 drivers
+v0x55ab20e5b780_0 .net "g0", 0 0, L_0x55ab20ec7370; 1 drivers
+v0x55ab20e5b840_0 .net "g1", 0 0, L_0x55ab20ec7680; 1 drivers
+v0x55ab20e5b900_0 .net "y", 1 0, L_0x55ab20ec7ad0; 1 drivers
+L_0x55ab20ec6fe0 .part L_0x55ab20ec7dc0, 1, 1;
+L_0x55ab20ec7140 .part L_0x55ab20ec7dc0, 0, 1;
+L_0x55ab20ec7280 .part L_0x55ab20ec7dc0, 1, 1;
+L_0x55ab20ec7430 .part L_0x55ab20ec7dc0, 0, 1;
+L_0x55ab20ec75e0 .part L_0x55ab20ec7d20, 0, 1;
+L_0x55ab20ec7750 .part L_0x55ab20ec7dc0, 0, 1;
+L_0x55ab20ec7880 .part L_0x55ab20ec7d20, 1, 1;
+L_0x55ab20ec7ad0 .concat8 [ 1 1 0 0], L_0x55ab20ec79c0, L_0x55ab20ec7c10;
+S_0x55ab20e5ba60 .scope generate, "genblk7[30]" "genblk7[30]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e5bbf0 .param/l "j" 0 2 164, +C4<011110>;
+L_0x55ab20ec8c10 .part L_0x55ab20ebb860, 26, 2;
+L_0x55ab20ec8cb0 .part L_0x55ab20ebb860, 30, 2;
+S_0x55ab20e5bcd0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e5ba60;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ec7e60 .functor NOT 1, L_0x55ab20ec7ed0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ec7fc0 .functor AND 1, L_0x55ab20ec8030, L_0x55ab20ec8170, C4<1>, C4<1>;
+L_0x55ab20ec8260 .functor AND 1, L_0x55ab20ec7e60, L_0x55ab20ec8320, L_0x55ab20ec84d0, C4<1>;
+L_0x55ab20ec8570 .functor AND 1, L_0x55ab20ec7e60, L_0x55ab20ec8640, L_0x55ab20ec8770, C4<1>;
+L_0x55ab20ec88b0 .functor OR 1, L_0x55ab20ec7fc0, L_0x55ab20ec8260, C4<0>, C4<0>;
+L_0x55ab20ec8b00 .functor OR 1, L_0x55ab20ec7fc0, L_0x55ab20ec8570, C4<0>, C4<0>;
+v0x55ab20e5bf20_0 .net *"_ivl_1", 0 0, L_0x55ab20ec7ed0; 1 drivers
+v0x55ab20e5c020_0 .net *"_ivl_11", 0 0, L_0x55ab20ec8640; 1 drivers
+v0x55ab20e5c100_0 .net *"_ivl_13", 0 0, L_0x55ab20ec8770; 1 drivers
+v0x55ab20e5c1c0_0 .net *"_ivl_14", 0 0, L_0x55ab20ec88b0; 1 drivers
+v0x55ab20e5c2a0_0 .net *"_ivl_16", 0 0, L_0x55ab20ec8b00; 1 drivers
+v0x55ab20e5c3d0_0 .net *"_ivl_3", 0 0, L_0x55ab20ec8030; 1 drivers
+v0x55ab20e5c4b0_0 .net *"_ivl_5", 0 0, L_0x55ab20ec8170; 1 drivers
+v0x55ab20e5c590_0 .net *"_ivl_7", 0 0, L_0x55ab20ec8320; 1 drivers
+v0x55ab20e5c670_0 .net *"_ivl_9", 0 0, L_0x55ab20ec84d0; 1 drivers
+v0x55ab20e5c7e0_0 .net "a", 1 0, L_0x55ab20ec8c10; 1 drivers
+v0x55ab20e5c8c0_0 .net "b", 1 0, L_0x55ab20ec8cb0; 1 drivers
+v0x55ab20e5c9a0_0 .net "b0", 0 0, L_0x55ab20ec7e60; 1 drivers
+v0x55ab20e5ca60_0 .net "f", 0 0, L_0x55ab20ec7fc0; 1 drivers
+v0x55ab20e5cb20_0 .net "g0", 0 0, L_0x55ab20ec8260; 1 drivers
+v0x55ab20e5cbe0_0 .net "g1", 0 0, L_0x55ab20ec8570; 1 drivers
+v0x55ab20e5cca0_0 .net "y", 1 0, L_0x55ab20ec89c0; 1 drivers
+L_0x55ab20ec7ed0 .part L_0x55ab20ec8cb0, 1, 1;
+L_0x55ab20ec8030 .part L_0x55ab20ec8cb0, 0, 1;
+L_0x55ab20ec8170 .part L_0x55ab20ec8cb0, 1, 1;
+L_0x55ab20ec8320 .part L_0x55ab20ec8cb0, 0, 1;
+L_0x55ab20ec84d0 .part L_0x55ab20ec8c10, 0, 1;
+L_0x55ab20ec8640 .part L_0x55ab20ec8cb0, 0, 1;
+L_0x55ab20ec8770 .part L_0x55ab20ec8c10, 1, 1;
+L_0x55ab20ec89c0 .concat8 [ 1 1 0 0], L_0x55ab20ec88b0, L_0x55ab20ec8b00;
+S_0x55ab20e5ce00 .scope generate, "genblk7[32]" "genblk7[32]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e5cf90 .param/l "j" 0 2 164, +C4<0100000>;
+L_0x55ab20ec9b00 .part L_0x55ab20ebb860, 28, 2;
+L_0x55ab20ec9ba0 .part L_0x55ab20ebb860, 32, 2;
+S_0x55ab20e5d050 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e5ce00;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ec8d50 .functor NOT 1, L_0x55ab20ec8dc0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ec8eb0 .functor AND 1, L_0x55ab20ec8f20, L_0x55ab20ec9060, C4<1>, C4<1>;
+L_0x55ab20ec9150 .functor AND 1, L_0x55ab20ec8d50, L_0x55ab20ec9210, L_0x55ab20ec93c0, C4<1>;
+L_0x55ab20ec9460 .functor AND 1, L_0x55ab20ec8d50, L_0x55ab20ec9530, L_0x55ab20ec9660, C4<1>;
+L_0x55ab20ec97a0 .functor OR 1, L_0x55ab20ec8eb0, L_0x55ab20ec9150, C4<0>, C4<0>;
+L_0x55ab20ec99f0 .functor OR 1, L_0x55ab20ec8eb0, L_0x55ab20ec9460, C4<0>, C4<0>;
+v0x55ab20e5d2c0_0 .net *"_ivl_1", 0 0, L_0x55ab20ec8dc0; 1 drivers
+v0x55ab20e5d3c0_0 .net *"_ivl_11", 0 0, L_0x55ab20ec9530; 1 drivers
+v0x55ab20e5d4a0_0 .net *"_ivl_13", 0 0, L_0x55ab20ec9660; 1 drivers
+v0x55ab20e5d560_0 .net *"_ivl_14", 0 0, L_0x55ab20ec97a0; 1 drivers
+v0x55ab20e5d640_0 .net *"_ivl_16", 0 0, L_0x55ab20ec99f0; 1 drivers
+v0x55ab20e5d770_0 .net *"_ivl_3", 0 0, L_0x55ab20ec8f20; 1 drivers
+v0x55ab20e5d850_0 .net *"_ivl_5", 0 0, L_0x55ab20ec9060; 1 drivers
+v0x55ab20e5d930_0 .net *"_ivl_7", 0 0, L_0x55ab20ec9210; 1 drivers
+v0x55ab20e5da10_0 .net *"_ivl_9", 0 0, L_0x55ab20ec93c0; 1 drivers
+v0x55ab20e5db80_0 .net "a", 1 0, L_0x55ab20ec9b00; 1 drivers
+v0x55ab20e5dc60_0 .net "b", 1 0, L_0x55ab20ec9ba0; 1 drivers
+v0x55ab20e5dd40_0 .net "b0", 0 0, L_0x55ab20ec8d50; 1 drivers
+v0x55ab20e5de00_0 .net "f", 0 0, L_0x55ab20ec8eb0; 1 drivers
+v0x55ab20e5dec0_0 .net "g0", 0 0, L_0x55ab20ec9150; 1 drivers
+v0x55ab20e5df80_0 .net "g1", 0 0, L_0x55ab20ec9460; 1 drivers
+v0x55ab20e5e040_0 .net "y", 1 0, L_0x55ab20ec98b0; 1 drivers
+L_0x55ab20ec8dc0 .part L_0x55ab20ec9ba0, 1, 1;
+L_0x55ab20ec8f20 .part L_0x55ab20ec9ba0, 0, 1;
+L_0x55ab20ec9060 .part L_0x55ab20ec9ba0, 1, 1;
+L_0x55ab20ec9210 .part L_0x55ab20ec9ba0, 0, 1;
+L_0x55ab20ec93c0 .part L_0x55ab20ec9b00, 0, 1;
+L_0x55ab20ec9530 .part L_0x55ab20ec9ba0, 0, 1;
+L_0x55ab20ec9660 .part L_0x55ab20ec9b00, 1, 1;
+L_0x55ab20ec98b0 .concat8 [ 1 1 0 0], L_0x55ab20ec97a0, L_0x55ab20ec99f0;
+S_0x55ab20e5e1a0 .scope generate, "genblk7[34]" "genblk7[34]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e5e330 .param/l "j" 0 2 164, +C4<0100010>;
+L_0x55ab20ecae00 .part L_0x55ab20ebb860, 30, 2;
+L_0x55ab20ecaea0 .part L_0x55ab20ebb860, 34, 2;
+S_0x55ab20e5e3f0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e5e1a0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20eca050 .functor NOT 1, L_0x55ab20eca0c0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20eca1b0 .functor AND 1, L_0x55ab20eca220, L_0x55ab20eca360, C4<1>, C4<1>;
+L_0x55ab20eca450 .functor AND 1, L_0x55ab20eca050, L_0x55ab20eca510, L_0x55ab20eca6c0, C4<1>;
+L_0x55ab20eca760 .functor AND 1, L_0x55ab20eca050, L_0x55ab20eca830, L_0x55ab20eca960, C4<1>;
+L_0x55ab20ecaaa0 .functor OR 1, L_0x55ab20eca1b0, L_0x55ab20eca450, C4<0>, C4<0>;
+L_0x55ab20ecacf0 .functor OR 1, L_0x55ab20eca1b0, L_0x55ab20eca760, C4<0>, C4<0>;
+v0x55ab20e5e660_0 .net *"_ivl_1", 0 0, L_0x55ab20eca0c0; 1 drivers
+v0x55ab20e5e760_0 .net *"_ivl_11", 0 0, L_0x55ab20eca830; 1 drivers
+v0x55ab20e5e840_0 .net *"_ivl_13", 0 0, L_0x55ab20eca960; 1 drivers
+v0x55ab20e5e900_0 .net *"_ivl_14", 0 0, L_0x55ab20ecaaa0; 1 drivers
+v0x55ab20e5e9e0_0 .net *"_ivl_16", 0 0, L_0x55ab20ecacf0; 1 drivers
+v0x55ab20e5eb10_0 .net *"_ivl_3", 0 0, L_0x55ab20eca220; 1 drivers
+v0x55ab20e5ebf0_0 .net *"_ivl_5", 0 0, L_0x55ab20eca360; 1 drivers
+v0x55ab20e5ecd0_0 .net *"_ivl_7", 0 0, L_0x55ab20eca510; 1 drivers
+v0x55ab20e5edb0_0 .net *"_ivl_9", 0 0, L_0x55ab20eca6c0; 1 drivers
+v0x55ab20e5ef20_0 .net "a", 1 0, L_0x55ab20ecae00; 1 drivers
+v0x55ab20e5f000_0 .net "b", 1 0, L_0x55ab20ecaea0; 1 drivers
+v0x55ab20e5f0e0_0 .net "b0", 0 0, L_0x55ab20eca050; 1 drivers
+v0x55ab20e5f1a0_0 .net "f", 0 0, L_0x55ab20eca1b0; 1 drivers
+v0x55ab20e5f260_0 .net "g0", 0 0, L_0x55ab20eca450; 1 drivers
+v0x55ab20e5f320_0 .net "g1", 0 0, L_0x55ab20eca760; 1 drivers
+v0x55ab20e5f3e0_0 .net "y", 1 0, L_0x55ab20ecabb0; 1 drivers
+L_0x55ab20eca0c0 .part L_0x55ab20ecaea0, 1, 1;
+L_0x55ab20eca220 .part L_0x55ab20ecaea0, 0, 1;
+L_0x55ab20eca360 .part L_0x55ab20ecaea0, 1, 1;
+L_0x55ab20eca510 .part L_0x55ab20ecaea0, 0, 1;
+L_0x55ab20eca6c0 .part L_0x55ab20ecae00, 0, 1;
+L_0x55ab20eca830 .part L_0x55ab20ecaea0, 0, 1;
+L_0x55ab20eca960 .part L_0x55ab20ecae00, 1, 1;
+L_0x55ab20ecabb0 .concat8 [ 1 1 0 0], L_0x55ab20ecaaa0, L_0x55ab20ecacf0;
+S_0x55ab20e5f540 .scope generate, "genblk7[36]" "genblk7[36]" 2 164, 2 164 0, S_0x55ab20e4b7d0;
+ .timescale 0 0;
+P_0x55ab20e5f7e0 .param/l "j" 0 2 164, +C4<0100100>;
+L_0x55ab20ecbcf0 .part L_0x55ab20ebb860, 32, 2;
+L_0x55ab20ecbd90 .part L_0x55ab20ebb860, 36, 2;
+LS_0x55ab20ecbe30_0_0 .concat8 [ 4 2 2 2], L_0x55ab20ebbef0, L_0x55ab20ebcab0, L_0x55ab20ebd950, L_0x55ab20ebe7b0;
+LS_0x55ab20ecbe30_0_4 .concat8 [ 2 2 2 2], L_0x55ab20ebf580, L_0x55ab20ec03e0, L_0x55ab20ec1270, L_0x55ab20ec2130;
+LS_0x55ab20ecbe30_0_8 .concat8 [ 2 2 2 2], L_0x55ab20ec3020, L_0x55ab20ec3f10, L_0x55ab20ec4e00, L_0x55ab20ec5cf0;
+LS_0x55ab20ecbe30_0_12 .concat8 [ 2 2 2 2], L_0x55ab20ec6be0, L_0x55ab20ec7ad0, L_0x55ab20ec89c0, L_0x55ab20ec98b0;
+LS_0x55ab20ecbe30_0_16 .concat8 [ 2 2 0 0], L_0x55ab20ecabb0, L_0x55ab20ecbaa0;
+LS_0x55ab20ecbe30_1_0 .concat8 [ 10 8 8 8], LS_0x55ab20ecbe30_0_0, LS_0x55ab20ecbe30_0_4, LS_0x55ab20ecbe30_0_8, LS_0x55ab20ecbe30_0_12;
+LS_0x55ab20ecbe30_1_4 .concat8 [ 4 0 0 0], LS_0x55ab20ecbe30_0_16;
+L_0x55ab20ecbe30 .concat8 [ 34 4 0 0], LS_0x55ab20ecbe30_1_0, LS_0x55ab20ecbe30_1_4;
+S_0x55ab20e5f8a0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e5f540;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ecaf40 .functor NOT 1, L_0x55ab20ecafb0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ecb0a0 .functor AND 1, L_0x55ab20ecb110, L_0x55ab20ecb250, C4<1>, C4<1>;
+L_0x55ab20ecb340 .functor AND 1, L_0x55ab20ecaf40, L_0x55ab20ecb400, L_0x55ab20ecb5b0, C4<1>;
+L_0x55ab20ecb650 .functor AND 1, L_0x55ab20ecaf40, L_0x55ab20ecb720, L_0x55ab20ecb850, C4<1>;
+L_0x55ab20ecb990 .functor OR 1, L_0x55ab20ecb0a0, L_0x55ab20ecb340, C4<0>, C4<0>;
+L_0x55ab20ecbbe0 .functor OR 1, L_0x55ab20ecb0a0, L_0x55ab20ecb650, C4<0>, C4<0>;
+v0x55ab20e5fb10_0 .net *"_ivl_1", 0 0, L_0x55ab20ecafb0; 1 drivers
+v0x55ab20e5fc10_0 .net *"_ivl_11", 0 0, L_0x55ab20ecb720; 1 drivers
+v0x55ab20e5fcf0_0 .net *"_ivl_13", 0 0, L_0x55ab20ecb850; 1 drivers
+v0x55ab20e5fdb0_0 .net *"_ivl_14", 0 0, L_0x55ab20ecb990; 1 drivers
+v0x55ab20e5fe90_0 .net *"_ivl_16", 0 0, L_0x55ab20ecbbe0; 1 drivers
+v0x55ab20e5ffc0_0 .net *"_ivl_3", 0 0, L_0x55ab20ecb110; 1 drivers
+v0x55ab20e600a0_0 .net *"_ivl_5", 0 0, L_0x55ab20ecb250; 1 drivers
+v0x55ab20e60180_0 .net *"_ivl_7", 0 0, L_0x55ab20ecb400; 1 drivers
+v0x55ab20e60260_0 .net *"_ivl_9", 0 0, L_0x55ab20ecb5b0; 1 drivers
+v0x55ab20e60340_0 .net "a", 1 0, L_0x55ab20ecbcf0; 1 drivers
+v0x55ab20e60420_0 .net "b", 1 0, L_0x55ab20ecbd90; 1 drivers
+v0x55ab20e60500_0 .net "b0", 0 0, L_0x55ab20ecaf40; 1 drivers
+v0x55ab20e605c0_0 .net "f", 0 0, L_0x55ab20ecb0a0; 1 drivers
+v0x55ab20e60680_0 .net "g0", 0 0, L_0x55ab20ecb340; 1 drivers
+v0x55ab20e60740_0 .net "g1", 0 0, L_0x55ab20ecb650; 1 drivers
+v0x55ab20e60800_0 .net "y", 1 0, L_0x55ab20ecbaa0; 1 drivers
+L_0x55ab20ecafb0 .part L_0x55ab20ecbd90, 1, 1;
+L_0x55ab20ecb110 .part L_0x55ab20ecbd90, 0, 1;
+L_0x55ab20ecb250 .part L_0x55ab20ecbd90, 1, 1;
+L_0x55ab20ecb400 .part L_0x55ab20ecbd90, 0, 1;
+L_0x55ab20ecb5b0 .part L_0x55ab20ecbcf0, 0, 1;
+L_0x55ab20ecb720 .part L_0x55ab20ecbd90, 0, 1;
+L_0x55ab20ecb850 .part L_0x55ab20ecbcf0, 1, 1;
+L_0x55ab20ecbaa0 .concat8 [ 1 1 0 0], L_0x55ab20ecb990, L_0x55ab20ecbbe0;
+S_0x55ab20e60a40 .scope generate, "genblk6[2]" "genblk6[2]" 2 161, 2 161 0, S_0x55ab20e352b0;
+ .timescale 0 0;
+P_0x55ab20e60bf0 .param/l "i" 0 2 161, +C4<010>;
+v0x55ab20e733f0_0 .net *"_ivl_5", 7 0, L_0x55ab20ecc510; 1 drivers
+L_0x55ab20ecc510 .part L_0x55ab20ecbe30, 0, 8;
+S_0x55ab20e60cb0 .scope generate, "genblk7[8]" "genblk7[8]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e60eb0 .param/l "j" 0 2 164, +C4<01000>;
+L_0x55ab20ecd320 .part L_0x55ab20ecbe30, 0, 2;
+L_0x55ab20ecd3c0 .part L_0x55ab20ecbe30, 8, 2;
+S_0x55ab20e60f90 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e60cb0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ecc600 .functor NOT 1, L_0x55ab20ecc670, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ecc760 .functor AND 1, L_0x55ab20ecc7d0, L_0x55ab20ecc910, C4<1>, C4<1>;
+L_0x55ab20ecca00 .functor AND 1, L_0x55ab20ecc600, L_0x55ab20eccac0, L_0x55ab20eccc40, C4<1>;
+L_0x55ab20eccce0 .functor AND 1, L_0x55ab20ecc600, L_0x55ab20eccd50, L_0x55ab20ecce80, C4<1>;
+L_0x55ab20eccfc0 .functor OR 1, L_0x55ab20ecc760, L_0x55ab20ecca00, C4<0>, C4<0>;
+L_0x55ab20ecd210 .functor OR 1, L_0x55ab20ecc760, L_0x55ab20eccce0, C4<0>, C4<0>;
+v0x55ab20e611e0_0 .net *"_ivl_1", 0 0, L_0x55ab20ecc670; 1 drivers
+v0x55ab20e612e0_0 .net *"_ivl_11", 0 0, L_0x55ab20eccd50; 1 drivers
+v0x55ab20e613c0_0 .net *"_ivl_13", 0 0, L_0x55ab20ecce80; 1 drivers
+v0x55ab20e61480_0 .net *"_ivl_14", 0 0, L_0x55ab20eccfc0; 1 drivers
+v0x55ab20e61560_0 .net *"_ivl_16", 0 0, L_0x55ab20ecd210; 1 drivers
+v0x55ab20e61690_0 .net *"_ivl_3", 0 0, L_0x55ab20ecc7d0; 1 drivers
+v0x55ab20e61770_0 .net *"_ivl_5", 0 0, L_0x55ab20ecc910; 1 drivers
+v0x55ab20e61850_0 .net *"_ivl_7", 0 0, L_0x55ab20eccac0; 1 drivers
+v0x55ab20e61930_0 .net *"_ivl_9", 0 0, L_0x55ab20eccc40; 1 drivers
+v0x55ab20e61aa0_0 .net "a", 1 0, L_0x55ab20ecd320; 1 drivers
+v0x55ab20e61b80_0 .net "b", 1 0, L_0x55ab20ecd3c0; 1 drivers
+v0x55ab20e61c60_0 .net "b0", 0 0, L_0x55ab20ecc600; 1 drivers
+v0x55ab20e61d20_0 .net "f", 0 0, L_0x55ab20ecc760; 1 drivers
+v0x55ab20e61de0_0 .net "g0", 0 0, L_0x55ab20ecca00; 1 drivers
+v0x55ab20e61ea0_0 .net "g1", 0 0, L_0x55ab20eccce0; 1 drivers
+v0x55ab20e61f60_0 .net "y", 1 0, L_0x55ab20ecd0d0; 1 drivers
+L_0x55ab20ecc670 .part L_0x55ab20ecd3c0, 1, 1;
+L_0x55ab20ecc7d0 .part L_0x55ab20ecd3c0, 0, 1;
+L_0x55ab20ecc910 .part L_0x55ab20ecd3c0, 1, 1;
+L_0x55ab20eccac0 .part L_0x55ab20ecd3c0, 0, 1;
+L_0x55ab20eccc40 .part L_0x55ab20ecd320, 0, 1;
+L_0x55ab20eccd50 .part L_0x55ab20ecd3c0, 0, 1;
+L_0x55ab20ecce80 .part L_0x55ab20ecd320, 1, 1;
+L_0x55ab20ecd0d0 .concat8 [ 1 1 0 0], L_0x55ab20eccfc0, L_0x55ab20ecd210;
+S_0x55ab20e620c0 .scope generate, "genblk7[10]" "genblk7[10]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e62270 .param/l "j" 0 2 164, +C4<01010>;
+L_0x55ab20ece1c0 .part L_0x55ab20ecbe30, 2, 2;
+L_0x55ab20ece260 .part L_0x55ab20ecbe30, 10, 2;
+S_0x55ab20e62330 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e620c0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ecd4f0 .functor NOT 1, L_0x55ab20ecd560, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ecd600 .functor AND 1, L_0x55ab20ecd670, L_0x55ab20ecd7b0, C4<1>, C4<1>;
+L_0x55ab20ecd8a0 .functor AND 1, L_0x55ab20ecd4f0, L_0x55ab20ecd960, L_0x55ab20ecdae0, C4<1>;
+L_0x55ab20ecdb80 .functor AND 1, L_0x55ab20ecd4f0, L_0x55ab20ecdbf0, L_0x55ab20ecdd20, C4<1>;
+L_0x55ab20ecde60 .functor OR 1, L_0x55ab20ecd600, L_0x55ab20ecd8a0, C4<0>, C4<0>;
+L_0x55ab20ece0b0 .functor OR 1, L_0x55ab20ecd600, L_0x55ab20ecdb80, C4<0>, C4<0>;
+v0x55ab20e62580_0 .net *"_ivl_1", 0 0, L_0x55ab20ecd560; 1 drivers
+v0x55ab20e62680_0 .net *"_ivl_11", 0 0, L_0x55ab20ecdbf0; 1 drivers
+v0x55ab20e62760_0 .net *"_ivl_13", 0 0, L_0x55ab20ecdd20; 1 drivers
+v0x55ab20e62820_0 .net *"_ivl_14", 0 0, L_0x55ab20ecde60; 1 drivers
+v0x55ab20e62900_0 .net *"_ivl_16", 0 0, L_0x55ab20ece0b0; 1 drivers
+v0x55ab20e62a30_0 .net *"_ivl_3", 0 0, L_0x55ab20ecd670; 1 drivers
+v0x55ab20e62b10_0 .net *"_ivl_5", 0 0, L_0x55ab20ecd7b0; 1 drivers
+v0x55ab20e62bf0_0 .net *"_ivl_7", 0 0, L_0x55ab20ecd960; 1 drivers
+v0x55ab20e62cd0_0 .net *"_ivl_9", 0 0, L_0x55ab20ecdae0; 1 drivers
+v0x55ab20e62e40_0 .net "a", 1 0, L_0x55ab20ece1c0; 1 drivers
+v0x55ab20e62f20_0 .net "b", 1 0, L_0x55ab20ece260; 1 drivers
+v0x55ab20e63000_0 .net "b0", 0 0, L_0x55ab20ecd4f0; 1 drivers
+v0x55ab20e630c0_0 .net "f", 0 0, L_0x55ab20ecd600; 1 drivers
+v0x55ab20e63180_0 .net "g0", 0 0, L_0x55ab20ecd8a0; 1 drivers
+v0x55ab20e63240_0 .net "g1", 0 0, L_0x55ab20ecdb80; 1 drivers
+v0x55ab20e63300_0 .net "y", 1 0, L_0x55ab20ecdf70; 1 drivers
+L_0x55ab20ecd560 .part L_0x55ab20ece260, 1, 1;
+L_0x55ab20ecd670 .part L_0x55ab20ece260, 0, 1;
+L_0x55ab20ecd7b0 .part L_0x55ab20ece260, 1, 1;
+L_0x55ab20ecd960 .part L_0x55ab20ece260, 0, 1;
+L_0x55ab20ecdae0 .part L_0x55ab20ece1c0, 0, 1;
+L_0x55ab20ecdbf0 .part L_0x55ab20ece260, 0, 1;
+L_0x55ab20ecdd20 .part L_0x55ab20ece1c0, 1, 1;
+L_0x55ab20ecdf70 .concat8 [ 1 1 0 0], L_0x55ab20ecde60, L_0x55ab20ece0b0;
+S_0x55ab20e63460 .scope generate, "genblk7[12]" "genblk7[12]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e635f0 .param/l "j" 0 2 164, +C4<01100>;
+L_0x55ab20ecf020 .part L_0x55ab20ecbe30, 4, 2;
+L_0x55ab20ecf0c0 .part L_0x55ab20ecbe30, 12, 2;
+S_0x55ab20e636b0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e63460;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ece300 .functor NOT 1, L_0x55ab20ece370, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ece460 .functor AND 1, L_0x55ab20ece4d0, L_0x55ab20ece610, C4<1>, C4<1>;
+L_0x55ab20ece700 .functor AND 1, L_0x55ab20ece300, L_0x55ab20ece7c0, L_0x55ab20ece940, C4<1>;
+L_0x55ab20ece9e0 .functor AND 1, L_0x55ab20ece300, L_0x55ab20ecea50, L_0x55ab20eceb80, C4<1>;
+L_0x55ab20ececc0 .functor OR 1, L_0x55ab20ece460, L_0x55ab20ece700, C4<0>, C4<0>;
+L_0x55ab20ecef10 .functor OR 1, L_0x55ab20ece460, L_0x55ab20ece9e0, C4<0>, C4<0>;
+v0x55ab20e63900_0 .net *"_ivl_1", 0 0, L_0x55ab20ece370; 1 drivers
+v0x55ab20e63a00_0 .net *"_ivl_11", 0 0, L_0x55ab20ecea50; 1 drivers
+v0x55ab20e63ae0_0 .net *"_ivl_13", 0 0, L_0x55ab20eceb80; 1 drivers
+v0x55ab20e63ba0_0 .net *"_ivl_14", 0 0, L_0x55ab20ececc0; 1 drivers
+v0x55ab20e63c80_0 .net *"_ivl_16", 0 0, L_0x55ab20ecef10; 1 drivers
+v0x55ab20e63db0_0 .net *"_ivl_3", 0 0, L_0x55ab20ece4d0; 1 drivers
+v0x55ab20e63e90_0 .net *"_ivl_5", 0 0, L_0x55ab20ece610; 1 drivers
+v0x55ab20e63f70_0 .net *"_ivl_7", 0 0, L_0x55ab20ece7c0; 1 drivers
+v0x55ab20e64050_0 .net *"_ivl_9", 0 0, L_0x55ab20ece940; 1 drivers
+v0x55ab20e641c0_0 .net "a", 1 0, L_0x55ab20ecf020; 1 drivers
+v0x55ab20e642a0_0 .net "b", 1 0, L_0x55ab20ecf0c0; 1 drivers
+v0x55ab20e64380_0 .net "b0", 0 0, L_0x55ab20ece300; 1 drivers
+v0x55ab20e64440_0 .net "f", 0 0, L_0x55ab20ece460; 1 drivers
+v0x55ab20e64500_0 .net "g0", 0 0, L_0x55ab20ece700; 1 drivers
+v0x55ab20e645c0_0 .net "g1", 0 0, L_0x55ab20ece9e0; 1 drivers
+v0x55ab20e64680_0 .net "y", 1 0, L_0x55ab20ecedd0; 1 drivers
+L_0x55ab20ece370 .part L_0x55ab20ecf0c0, 1, 1;
+L_0x55ab20ece4d0 .part L_0x55ab20ecf0c0, 0, 1;
+L_0x55ab20ece610 .part L_0x55ab20ecf0c0, 1, 1;
+L_0x55ab20ece7c0 .part L_0x55ab20ecf0c0, 0, 1;
+L_0x55ab20ece940 .part L_0x55ab20ecf020, 0, 1;
+L_0x55ab20ecea50 .part L_0x55ab20ecf0c0, 0, 1;
+L_0x55ab20eceb80 .part L_0x55ab20ecf020, 1, 1;
+L_0x55ab20ecedd0 .concat8 [ 1 1 0 0], L_0x55ab20ececc0, L_0x55ab20ecef10;
+S_0x55ab20e647e0 .scope generate, "genblk7[14]" "genblk7[14]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e64970 .param/l "j" 0 2 164, +C4<01110>;
+L_0x55ab20ecfdf0 .part L_0x55ab20ecbe30, 6, 2;
+L_0x55ab20ecfe90 .part L_0x55ab20ecbe30, 14, 2;
+S_0x55ab20e64a50 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e647e0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ecf160 .functor NOT 1, L_0x55ab20ecf1d0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ecf2c0 .functor AND 1, L_0x55ab20ecf330, L_0x55ab20ecf470, C4<1>, C4<1>;
+L_0x55ab20ecf560 .functor AND 1, L_0x55ab20ecf160, L_0x55ab20ecf620, L_0x55ab20ecf710, C4<1>;
+L_0x55ab20ecf7b0 .functor AND 1, L_0x55ab20ecf160, L_0x55ab20ecf820, L_0x55ab20ecf950, C4<1>;
+L_0x55ab20ecfa90 .functor OR 1, L_0x55ab20ecf2c0, L_0x55ab20ecf560, C4<0>, C4<0>;
+L_0x55ab20ecfce0 .functor OR 1, L_0x55ab20ecf2c0, L_0x55ab20ecf7b0, C4<0>, C4<0>;
+v0x55ab20e64ca0_0 .net *"_ivl_1", 0 0, L_0x55ab20ecf1d0; 1 drivers
+v0x55ab20e64da0_0 .net *"_ivl_11", 0 0, L_0x55ab20ecf820; 1 drivers
+v0x55ab20e64e80_0 .net *"_ivl_13", 0 0, L_0x55ab20ecf950; 1 drivers
+v0x55ab20e64f40_0 .net *"_ivl_14", 0 0, L_0x55ab20ecfa90; 1 drivers
+v0x55ab20e65020_0 .net *"_ivl_16", 0 0, L_0x55ab20ecfce0; 1 drivers
+v0x55ab20e65150_0 .net *"_ivl_3", 0 0, L_0x55ab20ecf330; 1 drivers
+v0x55ab20e65230_0 .net *"_ivl_5", 0 0, L_0x55ab20ecf470; 1 drivers
+v0x55ab20e65310_0 .net *"_ivl_7", 0 0, L_0x55ab20ecf620; 1 drivers
+v0x55ab20e653f0_0 .net *"_ivl_9", 0 0, L_0x55ab20ecf710; 1 drivers
+v0x55ab20e65560_0 .net "a", 1 0, L_0x55ab20ecfdf0; 1 drivers
+v0x55ab20e65640_0 .net "b", 1 0, L_0x55ab20ecfe90; 1 drivers
+v0x55ab20e65720_0 .net "b0", 0 0, L_0x55ab20ecf160; 1 drivers
+v0x55ab20e657e0_0 .net "f", 0 0, L_0x55ab20ecf2c0; 1 drivers
+v0x55ab20e658a0_0 .net "g0", 0 0, L_0x55ab20ecf560; 1 drivers
+v0x55ab20e65960_0 .net "g1", 0 0, L_0x55ab20ecf7b0; 1 drivers
+v0x55ab20e65a20_0 .net "y", 1 0, L_0x55ab20ecfba0; 1 drivers
+L_0x55ab20ecf1d0 .part L_0x55ab20ecfe90, 1, 1;
+L_0x55ab20ecf330 .part L_0x55ab20ecfe90, 0, 1;
+L_0x55ab20ecf470 .part L_0x55ab20ecfe90, 1, 1;
+L_0x55ab20ecf620 .part L_0x55ab20ecfe90, 0, 1;
+L_0x55ab20ecf710 .part L_0x55ab20ecfdf0, 0, 1;
+L_0x55ab20ecf820 .part L_0x55ab20ecfe90, 0, 1;
+L_0x55ab20ecf950 .part L_0x55ab20ecfdf0, 1, 1;
+L_0x55ab20ecfba0 .concat8 [ 1 1 0 0], L_0x55ab20ecfa90, L_0x55ab20ecfce0;
+S_0x55ab20e65b80 .scope generate, "genblk7[16]" "genblk7[16]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e65d60 .param/l "j" 0 2 164, +C4<010000>;
+L_0x55ab20ed0c50 .part L_0x55ab20ecbe30, 8, 2;
+L_0x55ab20ed0cf0 .part L_0x55ab20ecbe30, 16, 2;
+S_0x55ab20e65e40 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e65b80;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ecff30 .functor NOT 1, L_0x55ab20ecffa0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed0090 .functor AND 1, L_0x55ab20ed0100, L_0x55ab20ed0240, C4<1>, C4<1>;
+L_0x55ab20ed0330 .functor AND 1, L_0x55ab20ecff30, L_0x55ab20ed03f0, L_0x55ab20ed0570, C4<1>;
+L_0x55ab20ed0610 .functor AND 1, L_0x55ab20ecff30, L_0x55ab20ed0680, L_0x55ab20ed07b0, C4<1>;
+L_0x55ab20ed08f0 .functor OR 1, L_0x55ab20ed0090, L_0x55ab20ed0330, C4<0>, C4<0>;
+L_0x55ab20ed0b40 .functor OR 1, L_0x55ab20ed0090, L_0x55ab20ed0610, C4<0>, C4<0>;
+v0x55ab20e66090_0 .net *"_ivl_1", 0 0, L_0x55ab20ecffa0; 1 drivers
+v0x55ab20e66190_0 .net *"_ivl_11", 0 0, L_0x55ab20ed0680; 1 drivers
+v0x55ab20e66270_0 .net *"_ivl_13", 0 0, L_0x55ab20ed07b0; 1 drivers
+v0x55ab20e66330_0 .net *"_ivl_14", 0 0, L_0x55ab20ed08f0; 1 drivers
+v0x55ab20e66410_0 .net *"_ivl_16", 0 0, L_0x55ab20ed0b40; 1 drivers
+v0x55ab20e66540_0 .net *"_ivl_3", 0 0, L_0x55ab20ed0100; 1 drivers
+v0x55ab20e66620_0 .net *"_ivl_5", 0 0, L_0x55ab20ed0240; 1 drivers
+v0x55ab20e66700_0 .net *"_ivl_7", 0 0, L_0x55ab20ed03f0; 1 drivers
+v0x55ab20e667e0_0 .net *"_ivl_9", 0 0, L_0x55ab20ed0570; 1 drivers
+v0x55ab20e66950_0 .net "a", 1 0, L_0x55ab20ed0c50; 1 drivers
+v0x55ab20e66a30_0 .net "b", 1 0, L_0x55ab20ed0cf0; 1 drivers
+v0x55ab20e66b10_0 .net "b0", 0 0, L_0x55ab20ecff30; 1 drivers
+v0x55ab20e66bd0_0 .net "f", 0 0, L_0x55ab20ed0090; 1 drivers
+v0x55ab20e66c90_0 .net "g0", 0 0, L_0x55ab20ed0330; 1 drivers
+v0x55ab20e66d50_0 .net "g1", 0 0, L_0x55ab20ed0610; 1 drivers
+v0x55ab20e66e10_0 .net "y", 1 0, L_0x55ab20ed0a00; 1 drivers
+L_0x55ab20ecffa0 .part L_0x55ab20ed0cf0, 1, 1;
+L_0x55ab20ed0100 .part L_0x55ab20ed0cf0, 0, 1;
+L_0x55ab20ed0240 .part L_0x55ab20ed0cf0, 1, 1;
+L_0x55ab20ed03f0 .part L_0x55ab20ed0cf0, 0, 1;
+L_0x55ab20ed0570 .part L_0x55ab20ed0c50, 0, 1;
+L_0x55ab20ed0680 .part L_0x55ab20ed0cf0, 0, 1;
+L_0x55ab20ed07b0 .part L_0x55ab20ed0c50, 1, 1;
+L_0x55ab20ed0a00 .concat8 [ 1 1 0 0], L_0x55ab20ed08f0, L_0x55ab20ed0b40;
+S_0x55ab20e66f70 .scope generate, "genblk7[18]" "genblk7[18]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e67100 .param/l "j" 0 2 164, +C4<010010>;
+L_0x55ab20ed1ae0 .part L_0x55ab20ecbe30, 10, 2;
+L_0x55ab20ed1b80 .part L_0x55ab20ecbe30, 18, 2;
+S_0x55ab20e671e0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e66f70;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ed0d90 .functor NOT 1, L_0x55ab20ed0e00, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed0ef0 .functor AND 1, L_0x55ab20ed0f60, L_0x55ab20ed10a0, C4<1>, C4<1>;
+L_0x55ab20ed1190 .functor AND 1, L_0x55ab20ed0d90, L_0x55ab20ed1250, L_0x55ab20ed13d0, C4<1>;
+L_0x55ab20ed1470 .functor AND 1, L_0x55ab20ed0d90, L_0x55ab20ed1510, L_0x55ab20ed1640, C4<1>;
+L_0x55ab20ed1780 .functor OR 1, L_0x55ab20ed0ef0, L_0x55ab20ed1190, C4<0>, C4<0>;
+L_0x55ab20ed19d0 .functor OR 1, L_0x55ab20ed0ef0, L_0x55ab20ed1470, C4<0>, C4<0>;
+v0x55ab20e67430_0 .net *"_ivl_1", 0 0, L_0x55ab20ed0e00; 1 drivers
+v0x55ab20e67530_0 .net *"_ivl_11", 0 0, L_0x55ab20ed1510; 1 drivers
+v0x55ab20e67610_0 .net *"_ivl_13", 0 0, L_0x55ab20ed1640; 1 drivers
+v0x55ab20e676d0_0 .net *"_ivl_14", 0 0, L_0x55ab20ed1780; 1 drivers
+v0x55ab20e677b0_0 .net *"_ivl_16", 0 0, L_0x55ab20ed19d0; 1 drivers
+v0x55ab20e678e0_0 .net *"_ivl_3", 0 0, L_0x55ab20ed0f60; 1 drivers
+v0x55ab20e679c0_0 .net *"_ivl_5", 0 0, L_0x55ab20ed10a0; 1 drivers
+v0x55ab20e67aa0_0 .net *"_ivl_7", 0 0, L_0x55ab20ed1250; 1 drivers
+v0x55ab20e67b80_0 .net *"_ivl_9", 0 0, L_0x55ab20ed13d0; 1 drivers
+v0x55ab20e67cf0_0 .net "a", 1 0, L_0x55ab20ed1ae0; 1 drivers
+v0x55ab20e67dd0_0 .net "b", 1 0, L_0x55ab20ed1b80; 1 drivers
+v0x55ab20e67eb0_0 .net "b0", 0 0, L_0x55ab20ed0d90; 1 drivers
+v0x55ab20e67f70_0 .net "f", 0 0, L_0x55ab20ed0ef0; 1 drivers
+v0x55ab20e68030_0 .net "g0", 0 0, L_0x55ab20ed1190; 1 drivers
+v0x55ab20e680f0_0 .net "g1", 0 0, L_0x55ab20ed1470; 1 drivers
+v0x55ab20e681b0_0 .net "y", 1 0, L_0x55ab20ed1890; 1 drivers
+L_0x55ab20ed0e00 .part L_0x55ab20ed1b80, 1, 1;
+L_0x55ab20ed0f60 .part L_0x55ab20ed1b80, 0, 1;
+L_0x55ab20ed10a0 .part L_0x55ab20ed1b80, 1, 1;
+L_0x55ab20ed1250 .part L_0x55ab20ed1b80, 0, 1;
+L_0x55ab20ed13d0 .part L_0x55ab20ed1ae0, 0, 1;
+L_0x55ab20ed1510 .part L_0x55ab20ed1b80, 0, 1;
+L_0x55ab20ed1640 .part L_0x55ab20ed1ae0, 1, 1;
+L_0x55ab20ed1890 .concat8 [ 1 1 0 0], L_0x55ab20ed1780, L_0x55ab20ed19d0;
+S_0x55ab20e68310 .scope generate, "genblk7[20]" "genblk7[20]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e684a0 .param/l "j" 0 2 164, +C4<010100>;
+L_0x55ab20ed29d0 .part L_0x55ab20ecbe30, 12, 2;
+L_0x55ab20ed2a70 .part L_0x55ab20ecbe30, 20, 2;
+S_0x55ab20e68580 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e68310;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ed1c20 .functor NOT 1, L_0x55ab20ed1c90, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed1d80 .functor AND 1, L_0x55ab20ed1df0, L_0x55ab20ed1f30, C4<1>, C4<1>;
+L_0x55ab20ed2020 .functor AND 1, L_0x55ab20ed1c20, L_0x55ab20ed20e0, L_0x55ab20ed2290, C4<1>;
+L_0x55ab20ed2330 .functor AND 1, L_0x55ab20ed1c20, L_0x55ab20ed2400, L_0x55ab20ed2530, C4<1>;
+L_0x55ab20ed2670 .functor OR 1, L_0x55ab20ed1d80, L_0x55ab20ed2020, C4<0>, C4<0>;
+L_0x55ab20ed28c0 .functor OR 1, L_0x55ab20ed1d80, L_0x55ab20ed2330, C4<0>, C4<0>;
+v0x55ab20e687d0_0 .net *"_ivl_1", 0 0, L_0x55ab20ed1c90; 1 drivers
+v0x55ab20e688d0_0 .net *"_ivl_11", 0 0, L_0x55ab20ed2400; 1 drivers
+v0x55ab20e689b0_0 .net *"_ivl_13", 0 0, L_0x55ab20ed2530; 1 drivers
+v0x55ab20e68a70_0 .net *"_ivl_14", 0 0, L_0x55ab20ed2670; 1 drivers
+v0x55ab20e68b50_0 .net *"_ivl_16", 0 0, L_0x55ab20ed28c0; 1 drivers
+v0x55ab20e68c80_0 .net *"_ivl_3", 0 0, L_0x55ab20ed1df0; 1 drivers
+v0x55ab20e68d60_0 .net *"_ivl_5", 0 0, L_0x55ab20ed1f30; 1 drivers
+v0x55ab20e68e40_0 .net *"_ivl_7", 0 0, L_0x55ab20ed20e0; 1 drivers
+v0x55ab20e68f20_0 .net *"_ivl_9", 0 0, L_0x55ab20ed2290; 1 drivers
+v0x55ab20e69090_0 .net "a", 1 0, L_0x55ab20ed29d0; 1 drivers
+v0x55ab20e69170_0 .net "b", 1 0, L_0x55ab20ed2a70; 1 drivers
+v0x55ab20e69250_0 .net "b0", 0 0, L_0x55ab20ed1c20; 1 drivers
+v0x55ab20e69310_0 .net "f", 0 0, L_0x55ab20ed1d80; 1 drivers
+v0x55ab20e693d0_0 .net "g0", 0 0, L_0x55ab20ed2020; 1 drivers
+v0x55ab20e69490_0 .net "g1", 0 0, L_0x55ab20ed2330; 1 drivers
+v0x55ab20e69550_0 .net "y", 1 0, L_0x55ab20ed2780; 1 drivers
+L_0x55ab20ed1c90 .part L_0x55ab20ed2a70, 1, 1;
+L_0x55ab20ed1df0 .part L_0x55ab20ed2a70, 0, 1;
+L_0x55ab20ed1f30 .part L_0x55ab20ed2a70, 1, 1;
+L_0x55ab20ed20e0 .part L_0x55ab20ed2a70, 0, 1;
+L_0x55ab20ed2290 .part L_0x55ab20ed29d0, 0, 1;
+L_0x55ab20ed2400 .part L_0x55ab20ed2a70, 0, 1;
+L_0x55ab20ed2530 .part L_0x55ab20ed29d0, 1, 1;
+L_0x55ab20ed2780 .concat8 [ 1 1 0 0], L_0x55ab20ed2670, L_0x55ab20ed28c0;
+S_0x55ab20e696b0 .scope generate, "genblk7[22]" "genblk7[22]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e69840 .param/l "j" 0 2 164, +C4<010110>;
+L_0x55ab20ed38c0 .part L_0x55ab20ecbe30, 14, 2;
+L_0x55ab20ed3960 .part L_0x55ab20ecbe30, 22, 2;
+S_0x55ab20e69920 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e696b0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ed2b10 .functor NOT 1, L_0x55ab20ed2b80, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed2c70 .functor AND 1, L_0x55ab20ed2ce0, L_0x55ab20ed2e20, C4<1>, C4<1>;
+L_0x55ab20ed2f10 .functor AND 1, L_0x55ab20ed2b10, L_0x55ab20ed2fd0, L_0x55ab20ed3180, C4<1>;
+L_0x55ab20ed3220 .functor AND 1, L_0x55ab20ed2b10, L_0x55ab20ed32f0, L_0x55ab20ed3420, C4<1>;
+L_0x55ab20ed3560 .functor OR 1, L_0x55ab20ed2c70, L_0x55ab20ed2f10, C4<0>, C4<0>;
+L_0x55ab20ed37b0 .functor OR 1, L_0x55ab20ed2c70, L_0x55ab20ed3220, C4<0>, C4<0>;
+v0x55ab20e69b70_0 .net *"_ivl_1", 0 0, L_0x55ab20ed2b80; 1 drivers
+v0x55ab20e69c70_0 .net *"_ivl_11", 0 0, L_0x55ab20ed32f0; 1 drivers
+v0x55ab20e69d50_0 .net *"_ivl_13", 0 0, L_0x55ab20ed3420; 1 drivers
+v0x55ab20e69e10_0 .net *"_ivl_14", 0 0, L_0x55ab20ed3560; 1 drivers
+v0x55ab20e69ef0_0 .net *"_ivl_16", 0 0, L_0x55ab20ed37b0; 1 drivers
+v0x55ab20e6a020_0 .net *"_ivl_3", 0 0, L_0x55ab20ed2ce0; 1 drivers
+v0x55ab20e6a100_0 .net *"_ivl_5", 0 0, L_0x55ab20ed2e20; 1 drivers
+v0x55ab20e6a1e0_0 .net *"_ivl_7", 0 0, L_0x55ab20ed2fd0; 1 drivers
+v0x55ab20e6a2c0_0 .net *"_ivl_9", 0 0, L_0x55ab20ed3180; 1 drivers
+v0x55ab20e6a430_0 .net "a", 1 0, L_0x55ab20ed38c0; 1 drivers
+v0x55ab20e6a510_0 .net "b", 1 0, L_0x55ab20ed3960; 1 drivers
+v0x55ab20e6a5f0_0 .net "b0", 0 0, L_0x55ab20ed2b10; 1 drivers
+v0x55ab20e6a6b0_0 .net "f", 0 0, L_0x55ab20ed2c70; 1 drivers
+v0x55ab20e6a770_0 .net "g0", 0 0, L_0x55ab20ed2f10; 1 drivers
+v0x55ab20e6a830_0 .net "g1", 0 0, L_0x55ab20ed3220; 1 drivers
+v0x55ab20e6a8f0_0 .net "y", 1 0, L_0x55ab20ed3670; 1 drivers
+L_0x55ab20ed2b80 .part L_0x55ab20ed3960, 1, 1;
+L_0x55ab20ed2ce0 .part L_0x55ab20ed3960, 0, 1;
+L_0x55ab20ed2e20 .part L_0x55ab20ed3960, 1, 1;
+L_0x55ab20ed2fd0 .part L_0x55ab20ed3960, 0, 1;
+L_0x55ab20ed3180 .part L_0x55ab20ed38c0, 0, 1;
+L_0x55ab20ed32f0 .part L_0x55ab20ed3960, 0, 1;
+L_0x55ab20ed3420 .part L_0x55ab20ed38c0, 1, 1;
+L_0x55ab20ed3670 .concat8 [ 1 1 0 0], L_0x55ab20ed3560, L_0x55ab20ed37b0;
+S_0x55ab20e6aa50 .scope generate, "genblk7[24]" "genblk7[24]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e65d10 .param/l "j" 0 2 164, +C4<011000>;
+L_0x55ab20ed47b0 .part L_0x55ab20ecbe30, 16, 2;
+L_0x55ab20ed4850 .part L_0x55ab20ecbe30, 24, 2;
+S_0x55ab20e6ad00 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e6aa50;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ed3a00 .functor NOT 1, L_0x55ab20ed3a70, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed3b60 .functor AND 1, L_0x55ab20ed3bd0, L_0x55ab20ed3d10, C4<1>, C4<1>;
+L_0x55ab20ed3e00 .functor AND 1, L_0x55ab20ed3a00, L_0x55ab20ed3ec0, L_0x55ab20ed4070, C4<1>;
+L_0x55ab20ed4110 .functor AND 1, L_0x55ab20ed3a00, L_0x55ab20ed41e0, L_0x55ab20ed4310, C4<1>;
+L_0x55ab20ed4450 .functor OR 1, L_0x55ab20ed3b60, L_0x55ab20ed3e00, C4<0>, C4<0>;
+L_0x55ab20ed46a0 .functor OR 1, L_0x55ab20ed3b60, L_0x55ab20ed4110, C4<0>, C4<0>;
+v0x55ab20e6af50_0 .net *"_ivl_1", 0 0, L_0x55ab20ed3a70; 1 drivers
+v0x55ab20e6b050_0 .net *"_ivl_11", 0 0, L_0x55ab20ed41e0; 1 drivers
+v0x55ab20e6b130_0 .net *"_ivl_13", 0 0, L_0x55ab20ed4310; 1 drivers
+v0x55ab20e6b1f0_0 .net *"_ivl_14", 0 0, L_0x55ab20ed4450; 1 drivers
+v0x55ab20e6b2d0_0 .net *"_ivl_16", 0 0, L_0x55ab20ed46a0; 1 drivers
+v0x55ab20e6b400_0 .net *"_ivl_3", 0 0, L_0x55ab20ed3bd0; 1 drivers
+v0x55ab20e6b4e0_0 .net *"_ivl_5", 0 0, L_0x55ab20ed3d10; 1 drivers
+v0x55ab20e6b5c0_0 .net *"_ivl_7", 0 0, L_0x55ab20ed3ec0; 1 drivers
+v0x55ab20e6b6a0_0 .net *"_ivl_9", 0 0, L_0x55ab20ed4070; 1 drivers
+v0x55ab20e6b810_0 .net "a", 1 0, L_0x55ab20ed47b0; 1 drivers
+v0x55ab20e6b8f0_0 .net "b", 1 0, L_0x55ab20ed4850; 1 drivers
+v0x55ab20e6b9d0_0 .net "b0", 0 0, L_0x55ab20ed3a00; 1 drivers
+v0x55ab20e6ba90_0 .net "f", 0 0, L_0x55ab20ed3b60; 1 drivers
+v0x55ab20e6bb50_0 .net "g0", 0 0, L_0x55ab20ed3e00; 1 drivers
+v0x55ab20e6bc10_0 .net "g1", 0 0, L_0x55ab20ed4110; 1 drivers
+v0x55ab20e6bcd0_0 .net "y", 1 0, L_0x55ab20ed4560; 1 drivers
+L_0x55ab20ed3a70 .part L_0x55ab20ed4850, 1, 1;
+L_0x55ab20ed3bd0 .part L_0x55ab20ed4850, 0, 1;
+L_0x55ab20ed3d10 .part L_0x55ab20ed4850, 1, 1;
+L_0x55ab20ed3ec0 .part L_0x55ab20ed4850, 0, 1;
+L_0x55ab20ed4070 .part L_0x55ab20ed47b0, 0, 1;
+L_0x55ab20ed41e0 .part L_0x55ab20ed4850, 0, 1;
+L_0x55ab20ed4310 .part L_0x55ab20ed47b0, 1, 1;
+L_0x55ab20ed4560 .concat8 [ 1 1 0 0], L_0x55ab20ed4450, L_0x55ab20ed46a0;
+S_0x55ab20e6be30 .scope generate, "genblk7[26]" "genblk7[26]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e6bfc0 .param/l "j" 0 2 164, +C4<011010>;
+L_0x55ab20ed56a0 .part L_0x55ab20ecbe30, 18, 2;
+L_0x55ab20ed5740 .part L_0x55ab20ecbe30, 26, 2;
+S_0x55ab20e6c0a0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e6be30;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ed48f0 .functor NOT 1, L_0x55ab20ed4960, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed4a50 .functor AND 1, L_0x55ab20ed4ac0, L_0x55ab20ed4c00, C4<1>, C4<1>;
+L_0x55ab20ed4cf0 .functor AND 1, L_0x55ab20ed48f0, L_0x55ab20ed4db0, L_0x55ab20ed4f60, C4<1>;
+L_0x55ab20ed5000 .functor AND 1, L_0x55ab20ed48f0, L_0x55ab20ed50d0, L_0x55ab20ed5200, C4<1>;
+L_0x55ab20ed5340 .functor OR 1, L_0x55ab20ed4a50, L_0x55ab20ed4cf0, C4<0>, C4<0>;
+L_0x55ab20ed5590 .functor OR 1, L_0x55ab20ed4a50, L_0x55ab20ed5000, C4<0>, C4<0>;
+v0x55ab20e6c2f0_0 .net *"_ivl_1", 0 0, L_0x55ab20ed4960; 1 drivers
+v0x55ab20e6c3f0_0 .net *"_ivl_11", 0 0, L_0x55ab20ed50d0; 1 drivers
+v0x55ab20e6c4d0_0 .net *"_ivl_13", 0 0, L_0x55ab20ed5200; 1 drivers
+v0x55ab20e6c590_0 .net *"_ivl_14", 0 0, L_0x55ab20ed5340; 1 drivers
+v0x55ab20e6c670_0 .net *"_ivl_16", 0 0, L_0x55ab20ed5590; 1 drivers
+v0x55ab20e6c7a0_0 .net *"_ivl_3", 0 0, L_0x55ab20ed4ac0; 1 drivers
+v0x55ab20e6c880_0 .net *"_ivl_5", 0 0, L_0x55ab20ed4c00; 1 drivers
+v0x55ab20e6c960_0 .net *"_ivl_7", 0 0, L_0x55ab20ed4db0; 1 drivers
+v0x55ab20e6ca40_0 .net *"_ivl_9", 0 0, L_0x55ab20ed4f60; 1 drivers
+v0x55ab20e6cbb0_0 .net "a", 1 0, L_0x55ab20ed56a0; 1 drivers
+v0x55ab20e6cc90_0 .net "b", 1 0, L_0x55ab20ed5740; 1 drivers
+v0x55ab20e6cd70_0 .net "b0", 0 0, L_0x55ab20ed48f0; 1 drivers
+v0x55ab20e6ce30_0 .net "f", 0 0, L_0x55ab20ed4a50; 1 drivers
+v0x55ab20e6cef0_0 .net "g0", 0 0, L_0x55ab20ed4cf0; 1 drivers
+v0x55ab20e6cfb0_0 .net "g1", 0 0, L_0x55ab20ed5000; 1 drivers
+v0x55ab20e6d070_0 .net "y", 1 0, L_0x55ab20ed5450; 1 drivers
+L_0x55ab20ed4960 .part L_0x55ab20ed5740, 1, 1;
+L_0x55ab20ed4ac0 .part L_0x55ab20ed5740, 0, 1;
+L_0x55ab20ed4c00 .part L_0x55ab20ed5740, 1, 1;
+L_0x55ab20ed4db0 .part L_0x55ab20ed5740, 0, 1;
+L_0x55ab20ed4f60 .part L_0x55ab20ed56a0, 0, 1;
+L_0x55ab20ed50d0 .part L_0x55ab20ed5740, 0, 1;
+L_0x55ab20ed5200 .part L_0x55ab20ed56a0, 1, 1;
+L_0x55ab20ed5450 .concat8 [ 1 1 0 0], L_0x55ab20ed5340, L_0x55ab20ed5590;
+S_0x55ab20e6d1d0 .scope generate, "genblk7[28]" "genblk7[28]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e6d360 .param/l "j" 0 2 164, +C4<011100>;
+L_0x55ab20ed6590 .part L_0x55ab20ecbe30, 20, 2;
+L_0x55ab20ed6630 .part L_0x55ab20ecbe30, 28, 2;
+S_0x55ab20e6d440 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e6d1d0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ed57e0 .functor NOT 1, L_0x55ab20ed5850, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed5940 .functor AND 1, L_0x55ab20ed59b0, L_0x55ab20ed5af0, C4<1>, C4<1>;
+L_0x55ab20ed5be0 .functor AND 1, L_0x55ab20ed57e0, L_0x55ab20ed5ca0, L_0x55ab20ed5e50, C4<1>;
+L_0x55ab20ed5ef0 .functor AND 1, L_0x55ab20ed57e0, L_0x55ab20ed5fc0, L_0x55ab20ed60f0, C4<1>;
+L_0x55ab20ed6230 .functor OR 1, L_0x55ab20ed5940, L_0x55ab20ed5be0, C4<0>, C4<0>;
+L_0x55ab20ed6480 .functor OR 1, L_0x55ab20ed5940, L_0x55ab20ed5ef0, C4<0>, C4<0>;
+v0x55ab20e6d690_0 .net *"_ivl_1", 0 0, L_0x55ab20ed5850; 1 drivers
+v0x55ab20e6d790_0 .net *"_ivl_11", 0 0, L_0x55ab20ed5fc0; 1 drivers
+v0x55ab20e6d870_0 .net *"_ivl_13", 0 0, L_0x55ab20ed60f0; 1 drivers
+v0x55ab20e6d930_0 .net *"_ivl_14", 0 0, L_0x55ab20ed6230; 1 drivers
+v0x55ab20e6da10_0 .net *"_ivl_16", 0 0, L_0x55ab20ed6480; 1 drivers
+v0x55ab20e6db40_0 .net *"_ivl_3", 0 0, L_0x55ab20ed59b0; 1 drivers
+v0x55ab20e6dc20_0 .net *"_ivl_5", 0 0, L_0x55ab20ed5af0; 1 drivers
+v0x55ab20e6dd00_0 .net *"_ivl_7", 0 0, L_0x55ab20ed5ca0; 1 drivers
+v0x55ab20e6dde0_0 .net *"_ivl_9", 0 0, L_0x55ab20ed5e50; 1 drivers
+v0x55ab20e6df50_0 .net "a", 1 0, L_0x55ab20ed6590; 1 drivers
+v0x55ab20e6e030_0 .net "b", 1 0, L_0x55ab20ed6630; 1 drivers
+v0x55ab20e6e110_0 .net "b0", 0 0, L_0x55ab20ed57e0; 1 drivers
+v0x55ab20e6e1d0_0 .net "f", 0 0, L_0x55ab20ed5940; 1 drivers
+v0x55ab20e6e290_0 .net "g0", 0 0, L_0x55ab20ed5be0; 1 drivers
+v0x55ab20e6e350_0 .net "g1", 0 0, L_0x55ab20ed5ef0; 1 drivers
+v0x55ab20e6e410_0 .net "y", 1 0, L_0x55ab20ed6340; 1 drivers
+L_0x55ab20ed5850 .part L_0x55ab20ed6630, 1, 1;
+L_0x55ab20ed59b0 .part L_0x55ab20ed6630, 0, 1;
+L_0x55ab20ed5af0 .part L_0x55ab20ed6630, 1, 1;
+L_0x55ab20ed5ca0 .part L_0x55ab20ed6630, 0, 1;
+L_0x55ab20ed5e50 .part L_0x55ab20ed6590, 0, 1;
+L_0x55ab20ed5fc0 .part L_0x55ab20ed6630, 0, 1;
+L_0x55ab20ed60f0 .part L_0x55ab20ed6590, 1, 1;
+L_0x55ab20ed6340 .concat8 [ 1 1 0 0], L_0x55ab20ed6230, L_0x55ab20ed6480;
+S_0x55ab20e6e570 .scope generate, "genblk7[30]" "genblk7[30]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e6e700 .param/l "j" 0 2 164, +C4<011110>;
+L_0x55ab20ed7480 .part L_0x55ab20ecbe30, 22, 2;
+L_0x55ab20ed7520 .part L_0x55ab20ecbe30, 30, 2;
+S_0x55ab20e6e7e0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e6e570;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ed66d0 .functor NOT 1, L_0x55ab20ed6740, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed6830 .functor AND 1, L_0x55ab20ed68a0, L_0x55ab20ed69e0, C4<1>, C4<1>;
+L_0x55ab20ed6ad0 .functor AND 1, L_0x55ab20ed66d0, L_0x55ab20ed6b90, L_0x55ab20ed6d40, C4<1>;
+L_0x55ab20ed6de0 .functor AND 1, L_0x55ab20ed66d0, L_0x55ab20ed6eb0, L_0x55ab20ed6fe0, C4<1>;
+L_0x55ab20ed7120 .functor OR 1, L_0x55ab20ed6830, L_0x55ab20ed6ad0, C4<0>, C4<0>;
+L_0x55ab20ed7370 .functor OR 1, L_0x55ab20ed6830, L_0x55ab20ed6de0, C4<0>, C4<0>;
+v0x55ab20e6ea30_0 .net *"_ivl_1", 0 0, L_0x55ab20ed6740; 1 drivers
+v0x55ab20e6eb30_0 .net *"_ivl_11", 0 0, L_0x55ab20ed6eb0; 1 drivers
+v0x55ab20e6ec10_0 .net *"_ivl_13", 0 0, L_0x55ab20ed6fe0; 1 drivers
+v0x55ab20e6ecd0_0 .net *"_ivl_14", 0 0, L_0x55ab20ed7120; 1 drivers
+v0x55ab20e6edb0_0 .net *"_ivl_16", 0 0, L_0x55ab20ed7370; 1 drivers
+v0x55ab20e6eee0_0 .net *"_ivl_3", 0 0, L_0x55ab20ed68a0; 1 drivers
+v0x55ab20e6efc0_0 .net *"_ivl_5", 0 0, L_0x55ab20ed69e0; 1 drivers
+v0x55ab20e6f0a0_0 .net *"_ivl_7", 0 0, L_0x55ab20ed6b90; 1 drivers
+v0x55ab20e6f180_0 .net *"_ivl_9", 0 0, L_0x55ab20ed6d40; 1 drivers
+v0x55ab20e6f2f0_0 .net "a", 1 0, L_0x55ab20ed7480; 1 drivers
+v0x55ab20e6f3d0_0 .net "b", 1 0, L_0x55ab20ed7520; 1 drivers
+v0x55ab20e6f4b0_0 .net "b0", 0 0, L_0x55ab20ed66d0; 1 drivers
+v0x55ab20e6f570_0 .net "f", 0 0, L_0x55ab20ed6830; 1 drivers
+v0x55ab20e6f630_0 .net "g0", 0 0, L_0x55ab20ed6ad0; 1 drivers
+v0x55ab20e6f6f0_0 .net "g1", 0 0, L_0x55ab20ed6de0; 1 drivers
+v0x55ab20e6f7b0_0 .net "y", 1 0, L_0x55ab20ed7230; 1 drivers
+L_0x55ab20ed6740 .part L_0x55ab20ed7520, 1, 1;
+L_0x55ab20ed68a0 .part L_0x55ab20ed7520, 0, 1;
+L_0x55ab20ed69e0 .part L_0x55ab20ed7520, 1, 1;
+L_0x55ab20ed6b90 .part L_0x55ab20ed7520, 0, 1;
+L_0x55ab20ed6d40 .part L_0x55ab20ed7480, 0, 1;
+L_0x55ab20ed6eb0 .part L_0x55ab20ed7520, 0, 1;
+L_0x55ab20ed6fe0 .part L_0x55ab20ed7480, 1, 1;
+L_0x55ab20ed7230 .concat8 [ 1 1 0 0], L_0x55ab20ed7120, L_0x55ab20ed7370;
+S_0x55ab20e6f910 .scope generate, "genblk7[32]" "genblk7[32]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e6faa0 .param/l "j" 0 2 164, +C4<0100000>;
+L_0x55ab20ed8370 .part L_0x55ab20ecbe30, 24, 2;
+L_0x55ab20ed8410 .part L_0x55ab20ecbe30, 32, 2;
+S_0x55ab20e6fb60 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e6f910;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ed75c0 .functor NOT 1, L_0x55ab20ed7630, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed7720 .functor AND 1, L_0x55ab20ed7790, L_0x55ab20ed78d0, C4<1>, C4<1>;
+L_0x55ab20ed79c0 .functor AND 1, L_0x55ab20ed75c0, L_0x55ab20ed7a80, L_0x55ab20ed7c30, C4<1>;
+L_0x55ab20ed7cd0 .functor AND 1, L_0x55ab20ed75c0, L_0x55ab20ed7da0, L_0x55ab20ed7ed0, C4<1>;
+L_0x55ab20ed8010 .functor OR 1, L_0x55ab20ed7720, L_0x55ab20ed79c0, C4<0>, C4<0>;
+L_0x55ab20ed8260 .functor OR 1, L_0x55ab20ed7720, L_0x55ab20ed7cd0, C4<0>, C4<0>;
+v0x55ab20e6fdd0_0 .net *"_ivl_1", 0 0, L_0x55ab20ed7630; 1 drivers
+v0x55ab20e6fed0_0 .net *"_ivl_11", 0 0, L_0x55ab20ed7da0; 1 drivers
+v0x55ab20e6ffb0_0 .net *"_ivl_13", 0 0, L_0x55ab20ed7ed0; 1 drivers
+v0x55ab20e70070_0 .net *"_ivl_14", 0 0, L_0x55ab20ed8010; 1 drivers
+v0x55ab20e70150_0 .net *"_ivl_16", 0 0, L_0x55ab20ed8260; 1 drivers
+v0x55ab20e70280_0 .net *"_ivl_3", 0 0, L_0x55ab20ed7790; 1 drivers
+v0x55ab20e70360_0 .net *"_ivl_5", 0 0, L_0x55ab20ed78d0; 1 drivers
+v0x55ab20e70440_0 .net *"_ivl_7", 0 0, L_0x55ab20ed7a80; 1 drivers
+v0x55ab20e70520_0 .net *"_ivl_9", 0 0, L_0x55ab20ed7c30; 1 drivers
+v0x55ab20e70690_0 .net "a", 1 0, L_0x55ab20ed8370; 1 drivers
+v0x55ab20e70770_0 .net "b", 1 0, L_0x55ab20ed8410; 1 drivers
+v0x55ab20e70850_0 .net "b0", 0 0, L_0x55ab20ed75c0; 1 drivers
+v0x55ab20e70910_0 .net "f", 0 0, L_0x55ab20ed7720; 1 drivers
+v0x55ab20e709d0_0 .net "g0", 0 0, L_0x55ab20ed79c0; 1 drivers
+v0x55ab20e70a90_0 .net "g1", 0 0, L_0x55ab20ed7cd0; 1 drivers
+v0x55ab20e70b50_0 .net "y", 1 0, L_0x55ab20ed8120; 1 drivers
+L_0x55ab20ed7630 .part L_0x55ab20ed8410, 1, 1;
+L_0x55ab20ed7790 .part L_0x55ab20ed8410, 0, 1;
+L_0x55ab20ed78d0 .part L_0x55ab20ed8410, 1, 1;
+L_0x55ab20ed7a80 .part L_0x55ab20ed8410, 0, 1;
+L_0x55ab20ed7c30 .part L_0x55ab20ed8370, 0, 1;
+L_0x55ab20ed7da0 .part L_0x55ab20ed8410, 0, 1;
+L_0x55ab20ed7ed0 .part L_0x55ab20ed8370, 1, 1;
+L_0x55ab20ed8120 .concat8 [ 1 1 0 0], L_0x55ab20ed8010, L_0x55ab20ed8260;
+S_0x55ab20e70cb0 .scope generate, "genblk7[34]" "genblk7[34]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e70e40 .param/l "j" 0 2 164, +C4<0100010>;
+L_0x55ab20ed9260 .part L_0x55ab20ecbe30, 26, 2;
+L_0x55ab20ed9300 .part L_0x55ab20ecbe30, 34, 2;
+S_0x55ab20e70f00 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e70cb0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ed84b0 .functor NOT 1, L_0x55ab20ed8520, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed8610 .functor AND 1, L_0x55ab20ed8680, L_0x55ab20ed87c0, C4<1>, C4<1>;
+L_0x55ab20ed88b0 .functor AND 1, L_0x55ab20ed84b0, L_0x55ab20ed8970, L_0x55ab20ed8b20, C4<1>;
+L_0x55ab20ed8bc0 .functor AND 1, L_0x55ab20ed84b0, L_0x55ab20ed8c90, L_0x55ab20ed8dc0, C4<1>;
+L_0x55ab20ed8f00 .functor OR 1, L_0x55ab20ed8610, L_0x55ab20ed88b0, C4<0>, C4<0>;
+L_0x55ab20ed9150 .functor OR 1, L_0x55ab20ed8610, L_0x55ab20ed8bc0, C4<0>, C4<0>;
+v0x55ab20e71170_0 .net *"_ivl_1", 0 0, L_0x55ab20ed8520; 1 drivers
+v0x55ab20e71270_0 .net *"_ivl_11", 0 0, L_0x55ab20ed8c90; 1 drivers
+v0x55ab20e71350_0 .net *"_ivl_13", 0 0, L_0x55ab20ed8dc0; 1 drivers
+v0x55ab20e71410_0 .net *"_ivl_14", 0 0, L_0x55ab20ed8f00; 1 drivers
+v0x55ab20e714f0_0 .net *"_ivl_16", 0 0, L_0x55ab20ed9150; 1 drivers
+v0x55ab20e71620_0 .net *"_ivl_3", 0 0, L_0x55ab20ed8680; 1 drivers
+v0x55ab20e71700_0 .net *"_ivl_5", 0 0, L_0x55ab20ed87c0; 1 drivers
+v0x55ab20e717e0_0 .net *"_ivl_7", 0 0, L_0x55ab20ed8970; 1 drivers
+v0x55ab20e718c0_0 .net *"_ivl_9", 0 0, L_0x55ab20ed8b20; 1 drivers
+v0x55ab20e71a30_0 .net "a", 1 0, L_0x55ab20ed9260; 1 drivers
+v0x55ab20e71b10_0 .net "b", 1 0, L_0x55ab20ed9300; 1 drivers
+v0x55ab20e71bf0_0 .net "b0", 0 0, L_0x55ab20ed84b0; 1 drivers
+v0x55ab20e71cb0_0 .net "f", 0 0, L_0x55ab20ed8610; 1 drivers
+v0x55ab20e71d70_0 .net "g0", 0 0, L_0x55ab20ed88b0; 1 drivers
+v0x55ab20e71e30_0 .net "g1", 0 0, L_0x55ab20ed8bc0; 1 drivers
+v0x55ab20e71ef0_0 .net "y", 1 0, L_0x55ab20ed9010; 1 drivers
+L_0x55ab20ed8520 .part L_0x55ab20ed9300, 1, 1;
+L_0x55ab20ed8680 .part L_0x55ab20ed9300, 0, 1;
+L_0x55ab20ed87c0 .part L_0x55ab20ed9300, 1, 1;
+L_0x55ab20ed8970 .part L_0x55ab20ed9300, 0, 1;
+L_0x55ab20ed8b20 .part L_0x55ab20ed9260, 0, 1;
+L_0x55ab20ed8c90 .part L_0x55ab20ed9300, 0, 1;
+L_0x55ab20ed8dc0 .part L_0x55ab20ed9260, 1, 1;
+L_0x55ab20ed9010 .concat8 [ 1 1 0 0], L_0x55ab20ed8f00, L_0x55ab20ed9150;
+S_0x55ab20e72050 .scope generate, "genblk7[36]" "genblk7[36]" 2 164, 2 164 0, S_0x55ab20e60a40;
+ .timescale 0 0;
+P_0x55ab20e721e0 .param/l "j" 0 2 164, +C4<0100100>;
+L_0x55ab20eda150 .part L_0x55ab20ecbe30, 28, 2;
+L_0x55ab20eda1f0 .part L_0x55ab20ecbe30, 36, 2;
+LS_0x55ab20eda6a0_0_0 .concat8 [ 8 2 2 2], L_0x55ab20ecc510, L_0x55ab20ecd0d0, L_0x55ab20ecdf70, L_0x55ab20ecedd0;
+LS_0x55ab20eda6a0_0_4 .concat8 [ 2 2 2 2], L_0x55ab20ecfba0, L_0x55ab20ed0a00, L_0x55ab20ed1890, L_0x55ab20ed2780;
+LS_0x55ab20eda6a0_0_8 .concat8 [ 2 2 2 2], L_0x55ab20ed3670, L_0x55ab20ed4560, L_0x55ab20ed5450, L_0x55ab20ed6340;
+LS_0x55ab20eda6a0_0_12 .concat8 [ 2 2 2 2], L_0x55ab20ed7230, L_0x55ab20ed8120, L_0x55ab20ed9010, L_0x55ab20ed9f00;
+L_0x55ab20eda6a0 .concat8 [ 14 8 8 8], LS_0x55ab20eda6a0_0_0, LS_0x55ab20eda6a0_0_4, LS_0x55ab20eda6a0_0_8, LS_0x55ab20eda6a0_0_12;
+S_0x55ab20e722a0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e72050;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ed93a0 .functor NOT 1, L_0x55ab20ed9410, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ed9500 .functor AND 1, L_0x55ab20ed9570, L_0x55ab20ed96b0, C4<1>, C4<1>;
+L_0x55ab20ed97a0 .functor AND 1, L_0x55ab20ed93a0, L_0x55ab20ed9860, L_0x55ab20ed9a10, C4<1>;
+L_0x55ab20ed9ab0 .functor AND 1, L_0x55ab20ed93a0, L_0x55ab20ed9b80, L_0x55ab20ed9cb0, C4<1>;
+L_0x55ab20ed9df0 .functor OR 1, L_0x55ab20ed9500, L_0x55ab20ed97a0, C4<0>, C4<0>;
+L_0x55ab20eda040 .functor OR 1, L_0x55ab20ed9500, L_0x55ab20ed9ab0, C4<0>, C4<0>;
+v0x55ab20e72510_0 .net *"_ivl_1", 0 0, L_0x55ab20ed9410; 1 drivers
+v0x55ab20e72610_0 .net *"_ivl_11", 0 0, L_0x55ab20ed9b80; 1 drivers
+v0x55ab20e726f0_0 .net *"_ivl_13", 0 0, L_0x55ab20ed9cb0; 1 drivers
+v0x55ab20e727b0_0 .net *"_ivl_14", 0 0, L_0x55ab20ed9df0; 1 drivers
+v0x55ab20e72890_0 .net *"_ivl_16", 0 0, L_0x55ab20eda040; 1 drivers
+v0x55ab20e729c0_0 .net *"_ivl_3", 0 0, L_0x55ab20ed9570; 1 drivers
+v0x55ab20e72aa0_0 .net *"_ivl_5", 0 0, L_0x55ab20ed96b0; 1 drivers
+v0x55ab20e72b80_0 .net *"_ivl_7", 0 0, L_0x55ab20ed9860; 1 drivers
+v0x55ab20e72c60_0 .net *"_ivl_9", 0 0, L_0x55ab20ed9a10; 1 drivers
+v0x55ab20e72dd0_0 .net "a", 1 0, L_0x55ab20eda150; 1 drivers
+v0x55ab20e72eb0_0 .net "b", 1 0, L_0x55ab20eda1f0; 1 drivers
+v0x55ab20e72f90_0 .net "b0", 0 0, L_0x55ab20ed93a0; 1 drivers
+v0x55ab20e73050_0 .net "f", 0 0, L_0x55ab20ed9500; 1 drivers
+v0x55ab20e73110_0 .net "g0", 0 0, L_0x55ab20ed97a0; 1 drivers
+v0x55ab20e731d0_0 .net "g1", 0 0, L_0x55ab20ed9ab0; 1 drivers
+v0x55ab20e73290_0 .net "y", 1 0, L_0x55ab20ed9f00; 1 drivers
+L_0x55ab20ed9410 .part L_0x55ab20eda1f0, 1, 1;
+L_0x55ab20ed9570 .part L_0x55ab20eda1f0, 0, 1;
+L_0x55ab20ed96b0 .part L_0x55ab20eda1f0, 1, 1;
+L_0x55ab20ed9860 .part L_0x55ab20eda1f0, 0, 1;
+L_0x55ab20ed9a10 .part L_0x55ab20eda150, 0, 1;
+L_0x55ab20ed9b80 .part L_0x55ab20eda1f0, 0, 1;
+L_0x55ab20ed9cb0 .part L_0x55ab20eda150, 1, 1;
+L_0x55ab20ed9f00 .concat8 [ 1 1 0 0], L_0x55ab20ed9df0, L_0x55ab20eda040;
+S_0x55ab20e734d0 .scope generate, "genblk6[3]" "genblk6[3]" 2 161, 2 161 0, S_0x55ab20e352b0;
+ .timescale 0 0;
+P_0x55ab20e73680 .param/l "i" 0 2 161, +C4<011>;
+v0x55ab20e81020_0 .net *"_ivl_5", 15 0, L_0x55ab20edacd0; 1 drivers
+L_0x55ab20edacd0 .part L_0x55ab20eda6a0, 0, 16;
+S_0x55ab20e73760 .scope generate, "genblk7[16]" "genblk7[16]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e73960 .param/l "j" 0 2 164, +C4<010000>;
+L_0x55ab20edbae0 .part L_0x55ab20eda6a0, 0, 2;
+L_0x55ab20edbb80 .part L_0x55ab20eda6a0, 16, 2;
+S_0x55ab20e73a40 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e73760;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20edadc0 .functor NOT 1, L_0x55ab20edae30, C4<0>, C4<0>, C4<0>;
+L_0x55ab20edaf20 .functor AND 1, L_0x55ab20edaf90, L_0x55ab20edb0d0, C4<1>, C4<1>;
+L_0x55ab20edb1c0 .functor AND 1, L_0x55ab20edadc0, L_0x55ab20edb280, L_0x55ab20edb400, C4<1>;
+L_0x55ab20edb4a0 .functor AND 1, L_0x55ab20edadc0, L_0x55ab20edb510, L_0x55ab20edb640, C4<1>;
+L_0x55ab20edb780 .functor OR 1, L_0x55ab20edaf20, L_0x55ab20edb1c0, C4<0>, C4<0>;
+L_0x55ab20edb9d0 .functor OR 1, L_0x55ab20edaf20, L_0x55ab20edb4a0, C4<0>, C4<0>;
+v0x55ab20e73c90_0 .net *"_ivl_1", 0 0, L_0x55ab20edae30; 1 drivers
+v0x55ab20e73d90_0 .net *"_ivl_11", 0 0, L_0x55ab20edb510; 1 drivers
+v0x55ab20e73e70_0 .net *"_ivl_13", 0 0, L_0x55ab20edb640; 1 drivers
+v0x55ab20e73f30_0 .net *"_ivl_14", 0 0, L_0x55ab20edb780; 1 drivers
+v0x55ab20e74010_0 .net *"_ivl_16", 0 0, L_0x55ab20edb9d0; 1 drivers
+v0x55ab20e74140_0 .net *"_ivl_3", 0 0, L_0x55ab20edaf90; 1 drivers
+v0x55ab20e74220_0 .net *"_ivl_5", 0 0, L_0x55ab20edb0d0; 1 drivers
+v0x55ab20e74300_0 .net *"_ivl_7", 0 0, L_0x55ab20edb280; 1 drivers
+v0x55ab20e743e0_0 .net *"_ivl_9", 0 0, L_0x55ab20edb400; 1 drivers
+v0x55ab20e74550_0 .net "a", 1 0, L_0x55ab20edbae0; 1 drivers
+v0x55ab20e74630_0 .net "b", 1 0, L_0x55ab20edbb80; 1 drivers
+v0x55ab20e74710_0 .net "b0", 0 0, L_0x55ab20edadc0; 1 drivers
+v0x55ab20e747d0_0 .net "f", 0 0, L_0x55ab20edaf20; 1 drivers
+v0x55ab20e74890_0 .net "g0", 0 0, L_0x55ab20edb1c0; 1 drivers
+v0x55ab20e74950_0 .net "g1", 0 0, L_0x55ab20edb4a0; 1 drivers
+v0x55ab20e74a10_0 .net "y", 1 0, L_0x55ab20edb890; 1 drivers
+L_0x55ab20edae30 .part L_0x55ab20edbb80, 1, 1;
+L_0x55ab20edaf90 .part L_0x55ab20edbb80, 0, 1;
+L_0x55ab20edb0d0 .part L_0x55ab20edbb80, 1, 1;
+L_0x55ab20edb280 .part L_0x55ab20edbb80, 0, 1;
+L_0x55ab20edb400 .part L_0x55ab20edbae0, 0, 1;
+L_0x55ab20edb510 .part L_0x55ab20edbb80, 0, 1;
+L_0x55ab20edb640 .part L_0x55ab20edbae0, 1, 1;
+L_0x55ab20edb890 .concat8 [ 1 1 0 0], L_0x55ab20edb780, L_0x55ab20edb9d0;
+S_0x55ab20e74b70 .scope generate, "genblk7[18]" "genblk7[18]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e74d20 .param/l "j" 0 2 164, +C4<010010>;
+L_0x55ab20edc980 .part L_0x55ab20eda6a0, 2, 2;
+L_0x55ab20edca20 .part L_0x55ab20eda6a0, 18, 2;
+S_0x55ab20e74de0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e74b70;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20edbcb0 .functor NOT 1, L_0x55ab20edbd20, C4<0>, C4<0>, C4<0>;
+L_0x55ab20edbdc0 .functor AND 1, L_0x55ab20edbe30, L_0x55ab20edbf70, C4<1>, C4<1>;
+L_0x55ab20edc060 .functor AND 1, L_0x55ab20edbcb0, L_0x55ab20edc120, L_0x55ab20edc2a0, C4<1>;
+L_0x55ab20edc340 .functor AND 1, L_0x55ab20edbcb0, L_0x55ab20edc3b0, L_0x55ab20edc4e0, C4<1>;
+L_0x55ab20edc620 .functor OR 1, L_0x55ab20edbdc0, L_0x55ab20edc060, C4<0>, C4<0>;
+L_0x55ab20edc870 .functor OR 1, L_0x55ab20edbdc0, L_0x55ab20edc340, C4<0>, C4<0>;
+v0x55ab20e75030_0 .net *"_ivl_1", 0 0, L_0x55ab20edbd20; 1 drivers
+v0x55ab20e75130_0 .net *"_ivl_11", 0 0, L_0x55ab20edc3b0; 1 drivers
+v0x55ab20e75210_0 .net *"_ivl_13", 0 0, L_0x55ab20edc4e0; 1 drivers
+v0x55ab20e752d0_0 .net *"_ivl_14", 0 0, L_0x55ab20edc620; 1 drivers
+v0x55ab20e753b0_0 .net *"_ivl_16", 0 0, L_0x55ab20edc870; 1 drivers
+v0x55ab20e754e0_0 .net *"_ivl_3", 0 0, L_0x55ab20edbe30; 1 drivers
+v0x55ab20e755c0_0 .net *"_ivl_5", 0 0, L_0x55ab20edbf70; 1 drivers
+v0x55ab20e756a0_0 .net *"_ivl_7", 0 0, L_0x55ab20edc120; 1 drivers
+v0x55ab20e75780_0 .net *"_ivl_9", 0 0, L_0x55ab20edc2a0; 1 drivers
+v0x55ab20e758f0_0 .net "a", 1 0, L_0x55ab20edc980; 1 drivers
+v0x55ab20e759d0_0 .net "b", 1 0, L_0x55ab20edca20; 1 drivers
+v0x55ab20e75ab0_0 .net "b0", 0 0, L_0x55ab20edbcb0; 1 drivers
+v0x55ab20e75b70_0 .net "f", 0 0, L_0x55ab20edbdc0; 1 drivers
+v0x55ab20e75c30_0 .net "g0", 0 0, L_0x55ab20edc060; 1 drivers
+v0x55ab20e75cf0_0 .net "g1", 0 0, L_0x55ab20edc340; 1 drivers
+v0x55ab20e75db0_0 .net "y", 1 0, L_0x55ab20edc730; 1 drivers
+L_0x55ab20edbd20 .part L_0x55ab20edca20, 1, 1;
+L_0x55ab20edbe30 .part L_0x55ab20edca20, 0, 1;
+L_0x55ab20edbf70 .part L_0x55ab20edca20, 1, 1;
+L_0x55ab20edc120 .part L_0x55ab20edca20, 0, 1;
+L_0x55ab20edc2a0 .part L_0x55ab20edc980, 0, 1;
+L_0x55ab20edc3b0 .part L_0x55ab20edca20, 0, 1;
+L_0x55ab20edc4e0 .part L_0x55ab20edc980, 1, 1;
+L_0x55ab20edc730 .concat8 [ 1 1 0 0], L_0x55ab20edc620, L_0x55ab20edc870;
+S_0x55ab20e75f10 .scope generate, "genblk7[20]" "genblk7[20]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e760a0 .param/l "j" 0 2 164, +C4<010100>;
+L_0x55ab20edd7e0 .part L_0x55ab20eda6a0, 4, 2;
+L_0x55ab20edd880 .part L_0x55ab20eda6a0, 20, 2;
+S_0x55ab20e76160 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e75f10;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20edcac0 .functor NOT 1, L_0x55ab20edcb30, C4<0>, C4<0>, C4<0>;
+L_0x55ab20edcc20 .functor AND 1, L_0x55ab20edcc90, L_0x55ab20edcdd0, C4<1>, C4<1>;
+L_0x55ab20edcec0 .functor AND 1, L_0x55ab20edcac0, L_0x55ab20edcf80, L_0x55ab20edd100, C4<1>;
+L_0x55ab20edd1a0 .functor AND 1, L_0x55ab20edcac0, L_0x55ab20edd210, L_0x55ab20edd340, C4<1>;
+L_0x55ab20edd480 .functor OR 1, L_0x55ab20edcc20, L_0x55ab20edcec0, C4<0>, C4<0>;
+L_0x55ab20edd6d0 .functor OR 1, L_0x55ab20edcc20, L_0x55ab20edd1a0, C4<0>, C4<0>;
+v0x55ab20e763b0_0 .net *"_ivl_1", 0 0, L_0x55ab20edcb30; 1 drivers
+v0x55ab20e764b0_0 .net *"_ivl_11", 0 0, L_0x55ab20edd210; 1 drivers
+v0x55ab20e76590_0 .net *"_ivl_13", 0 0, L_0x55ab20edd340; 1 drivers
+v0x55ab20e76650_0 .net *"_ivl_14", 0 0, L_0x55ab20edd480; 1 drivers
+v0x55ab20e76730_0 .net *"_ivl_16", 0 0, L_0x55ab20edd6d0; 1 drivers
+v0x55ab20e76860_0 .net *"_ivl_3", 0 0, L_0x55ab20edcc90; 1 drivers
+v0x55ab20e76940_0 .net *"_ivl_5", 0 0, L_0x55ab20edcdd0; 1 drivers
+v0x55ab20e76a20_0 .net *"_ivl_7", 0 0, L_0x55ab20edcf80; 1 drivers
+v0x55ab20e76b00_0 .net *"_ivl_9", 0 0, L_0x55ab20edd100; 1 drivers
+v0x55ab20e76c70_0 .net "a", 1 0, L_0x55ab20edd7e0; 1 drivers
+v0x55ab20e76d50_0 .net "b", 1 0, L_0x55ab20edd880; 1 drivers
+v0x55ab20e76e30_0 .net "b0", 0 0, L_0x55ab20edcac0; 1 drivers
+v0x55ab20e76ef0_0 .net "f", 0 0, L_0x55ab20edcc20; 1 drivers
+v0x55ab20e76fb0_0 .net "g0", 0 0, L_0x55ab20edcec0; 1 drivers
+v0x55ab20e77070_0 .net "g1", 0 0, L_0x55ab20edd1a0; 1 drivers
+v0x55ab20e77130_0 .net "y", 1 0, L_0x55ab20edd590; 1 drivers
+L_0x55ab20edcb30 .part L_0x55ab20edd880, 1, 1;
+L_0x55ab20edcc90 .part L_0x55ab20edd880, 0, 1;
+L_0x55ab20edcdd0 .part L_0x55ab20edd880, 1, 1;
+L_0x55ab20edcf80 .part L_0x55ab20edd880, 0, 1;
+L_0x55ab20edd100 .part L_0x55ab20edd7e0, 0, 1;
+L_0x55ab20edd210 .part L_0x55ab20edd880, 0, 1;
+L_0x55ab20edd340 .part L_0x55ab20edd7e0, 1, 1;
+L_0x55ab20edd590 .concat8 [ 1 1 0 0], L_0x55ab20edd480, L_0x55ab20edd6d0;
+S_0x55ab20e77290 .scope generate, "genblk7[22]" "genblk7[22]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e77420 .param/l "j" 0 2 164, +C4<010110>;
+L_0x55ab20ede5b0 .part L_0x55ab20eda6a0, 6, 2;
+L_0x55ab20ede650 .part L_0x55ab20eda6a0, 22, 2;
+S_0x55ab20e77500 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e77290;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20edd920 .functor NOT 1, L_0x55ab20edd990, C4<0>, C4<0>, C4<0>;
+L_0x55ab20edda80 .functor AND 1, L_0x55ab20eddaf0, L_0x55ab20eddc30, C4<1>, C4<1>;
+L_0x55ab20eddd20 .functor AND 1, L_0x55ab20edd920, L_0x55ab20eddde0, L_0x55ab20edded0, C4<1>;
+L_0x55ab20eddf70 .functor AND 1, L_0x55ab20edd920, L_0x55ab20eddfe0, L_0x55ab20ede110, C4<1>;
+L_0x55ab20ede250 .functor OR 1, L_0x55ab20edda80, L_0x55ab20eddd20, C4<0>, C4<0>;
+L_0x55ab20ede4a0 .functor OR 1, L_0x55ab20edda80, L_0x55ab20eddf70, C4<0>, C4<0>;
+v0x55ab20e77750_0 .net *"_ivl_1", 0 0, L_0x55ab20edd990; 1 drivers
+v0x55ab20e77850_0 .net *"_ivl_11", 0 0, L_0x55ab20eddfe0; 1 drivers
+v0x55ab20e77930_0 .net *"_ivl_13", 0 0, L_0x55ab20ede110; 1 drivers
+v0x55ab20e779f0_0 .net *"_ivl_14", 0 0, L_0x55ab20ede250; 1 drivers
+v0x55ab20e77ad0_0 .net *"_ivl_16", 0 0, L_0x55ab20ede4a0; 1 drivers
+v0x55ab20e77c00_0 .net *"_ivl_3", 0 0, L_0x55ab20eddaf0; 1 drivers
+v0x55ab20e77ce0_0 .net *"_ivl_5", 0 0, L_0x55ab20eddc30; 1 drivers
+v0x55ab20e77dc0_0 .net *"_ivl_7", 0 0, L_0x55ab20eddde0; 1 drivers
+v0x55ab20e77ea0_0 .net *"_ivl_9", 0 0, L_0x55ab20edded0; 1 drivers
+v0x55ab20e78010_0 .net "a", 1 0, L_0x55ab20ede5b0; 1 drivers
+v0x55ab20e780f0_0 .net "b", 1 0, L_0x55ab20ede650; 1 drivers
+v0x55ab20e781d0_0 .net "b0", 0 0, L_0x55ab20edd920; 1 drivers
+v0x55ab20e78290_0 .net "f", 0 0, L_0x55ab20edda80; 1 drivers
+v0x55ab20e78350_0 .net "g0", 0 0, L_0x55ab20eddd20; 1 drivers
+v0x55ab20e78410_0 .net "g1", 0 0, L_0x55ab20eddf70; 1 drivers
+v0x55ab20e784d0_0 .net "y", 1 0, L_0x55ab20ede360; 1 drivers
+L_0x55ab20edd990 .part L_0x55ab20ede650, 1, 1;
+L_0x55ab20eddaf0 .part L_0x55ab20ede650, 0, 1;
+L_0x55ab20eddc30 .part L_0x55ab20ede650, 1, 1;
+L_0x55ab20eddde0 .part L_0x55ab20ede650, 0, 1;
+L_0x55ab20edded0 .part L_0x55ab20ede5b0, 0, 1;
+L_0x55ab20eddfe0 .part L_0x55ab20ede650, 0, 1;
+L_0x55ab20ede110 .part L_0x55ab20ede5b0, 1, 1;
+L_0x55ab20ede360 .concat8 [ 1 1 0 0], L_0x55ab20ede250, L_0x55ab20ede4a0;
+S_0x55ab20e78630 .scope generate, "genblk7[24]" "genblk7[24]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e78810 .param/l "j" 0 2 164, +C4<011000>;
+L_0x55ab20edf440 .part L_0x55ab20eda6a0, 8, 2;
+L_0x55ab20edf4e0 .part L_0x55ab20eda6a0, 24, 2;
+S_0x55ab20e788f0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e78630;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ede6f0 .functor NOT 1, L_0x55ab20ede760, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ede850 .functor AND 1, L_0x55ab20ede8c0, L_0x55ab20edea00, C4<1>, C4<1>;
+L_0x55ab20edeaf0 .functor AND 1, L_0x55ab20ede6f0, L_0x55ab20edebb0, L_0x55ab20eded30, C4<1>;
+L_0x55ab20ededd0 .functor AND 1, L_0x55ab20ede6f0, L_0x55ab20edee70, L_0x55ab20edefa0, C4<1>;
+L_0x55ab20edf0e0 .functor OR 1, L_0x55ab20ede850, L_0x55ab20edeaf0, C4<0>, C4<0>;
+L_0x55ab20edf330 .functor OR 1, L_0x55ab20ede850, L_0x55ab20ededd0, C4<0>, C4<0>;
+v0x55ab20e78b40_0 .net *"_ivl_1", 0 0, L_0x55ab20ede760; 1 drivers
+v0x55ab20e78c40_0 .net *"_ivl_11", 0 0, L_0x55ab20edee70; 1 drivers
+v0x55ab20e78d20_0 .net *"_ivl_13", 0 0, L_0x55ab20edefa0; 1 drivers
+v0x55ab20e78de0_0 .net *"_ivl_14", 0 0, L_0x55ab20edf0e0; 1 drivers
+v0x55ab20e78ec0_0 .net *"_ivl_16", 0 0, L_0x55ab20edf330; 1 drivers
+v0x55ab20e78ff0_0 .net *"_ivl_3", 0 0, L_0x55ab20ede8c0; 1 drivers
+v0x55ab20e790d0_0 .net *"_ivl_5", 0 0, L_0x55ab20edea00; 1 drivers
+v0x55ab20e791b0_0 .net *"_ivl_7", 0 0, L_0x55ab20edebb0; 1 drivers
+v0x55ab20e79290_0 .net *"_ivl_9", 0 0, L_0x55ab20eded30; 1 drivers
+v0x55ab20e79400_0 .net "a", 1 0, L_0x55ab20edf440; 1 drivers
+v0x55ab20e794e0_0 .net "b", 1 0, L_0x55ab20edf4e0; 1 drivers
+v0x55ab20e795c0_0 .net "b0", 0 0, L_0x55ab20ede6f0; 1 drivers
+v0x55ab20e79680_0 .net "f", 0 0, L_0x55ab20ede850; 1 drivers
+v0x55ab20e79740_0 .net "g0", 0 0, L_0x55ab20edeaf0; 1 drivers
+v0x55ab20e79800_0 .net "g1", 0 0, L_0x55ab20ededd0; 1 drivers
+v0x55ab20e798c0_0 .net "y", 1 0, L_0x55ab20edf1f0; 1 drivers
+L_0x55ab20ede760 .part L_0x55ab20edf4e0, 1, 1;
+L_0x55ab20ede8c0 .part L_0x55ab20edf4e0, 0, 1;
+L_0x55ab20edea00 .part L_0x55ab20edf4e0, 1, 1;
+L_0x55ab20edebb0 .part L_0x55ab20edf4e0, 0, 1;
+L_0x55ab20eded30 .part L_0x55ab20edf440, 0, 1;
+L_0x55ab20edee70 .part L_0x55ab20edf4e0, 0, 1;
+L_0x55ab20edefa0 .part L_0x55ab20edf440, 1, 1;
+L_0x55ab20edf1f0 .concat8 [ 1 1 0 0], L_0x55ab20edf0e0, L_0x55ab20edf330;
+S_0x55ab20e79a20 .scope generate, "genblk7[26]" "genblk7[26]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e79bb0 .param/l "j" 0 2 164, +C4<011010>;
+L_0x55ab20ee0300 .part L_0x55ab20eda6a0, 10, 2;
+L_0x55ab20ee03a0 .part L_0x55ab20eda6a0, 26, 2;
+S_0x55ab20e79c90 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e79a20;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20edf580 .functor NOT 1, L_0x55ab20edf5f0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20edf6e0 .functor AND 1, L_0x55ab20edf750, L_0x55ab20edf890, C4<1>, C4<1>;
+L_0x55ab20edf980 .functor AND 1, L_0x55ab20edf580, L_0x55ab20edfa40, L_0x55ab20edfbc0, C4<1>;
+L_0x55ab20edfc60 .functor AND 1, L_0x55ab20edf580, L_0x55ab20edfd30, L_0x55ab20edfe60, C4<1>;
+L_0x55ab20edffa0 .functor OR 1, L_0x55ab20edf6e0, L_0x55ab20edf980, C4<0>, C4<0>;
+L_0x55ab20ee01f0 .functor OR 1, L_0x55ab20edf6e0, L_0x55ab20edfc60, C4<0>, C4<0>;
+v0x55ab20e79ee0_0 .net *"_ivl_1", 0 0, L_0x55ab20edf5f0; 1 drivers
+v0x55ab20e79fe0_0 .net *"_ivl_11", 0 0, L_0x55ab20edfd30; 1 drivers
+v0x55ab20e7a0c0_0 .net *"_ivl_13", 0 0, L_0x55ab20edfe60; 1 drivers
+v0x55ab20e7a180_0 .net *"_ivl_14", 0 0, L_0x55ab20edffa0; 1 drivers
+v0x55ab20e7a260_0 .net *"_ivl_16", 0 0, L_0x55ab20ee01f0; 1 drivers
+v0x55ab20e7a390_0 .net *"_ivl_3", 0 0, L_0x55ab20edf750; 1 drivers
+v0x55ab20e7a470_0 .net *"_ivl_5", 0 0, L_0x55ab20edf890; 1 drivers
+v0x55ab20e7a550_0 .net *"_ivl_7", 0 0, L_0x55ab20edfa40; 1 drivers
+v0x55ab20e7a630_0 .net *"_ivl_9", 0 0, L_0x55ab20edfbc0; 1 drivers
+v0x55ab20e7a7a0_0 .net "a", 1 0, L_0x55ab20ee0300; 1 drivers
+v0x55ab20e7a880_0 .net "b", 1 0, L_0x55ab20ee03a0; 1 drivers
+v0x55ab20e7a960_0 .net "b0", 0 0, L_0x55ab20edf580; 1 drivers
+v0x55ab20e7aa20_0 .net "f", 0 0, L_0x55ab20edf6e0; 1 drivers
+v0x55ab20e7aae0_0 .net "g0", 0 0, L_0x55ab20edf980; 1 drivers
+v0x55ab20e7aba0_0 .net "g1", 0 0, L_0x55ab20edfc60; 1 drivers
+v0x55ab20e7ac60_0 .net "y", 1 0, L_0x55ab20ee00b0; 1 drivers
+L_0x55ab20edf5f0 .part L_0x55ab20ee03a0, 1, 1;
+L_0x55ab20edf750 .part L_0x55ab20ee03a0, 0, 1;
+L_0x55ab20edf890 .part L_0x55ab20ee03a0, 1, 1;
+L_0x55ab20edfa40 .part L_0x55ab20ee03a0, 0, 1;
+L_0x55ab20edfbc0 .part L_0x55ab20ee0300, 0, 1;
+L_0x55ab20edfd30 .part L_0x55ab20ee03a0, 0, 1;
+L_0x55ab20edfe60 .part L_0x55ab20ee0300, 1, 1;
+L_0x55ab20ee00b0 .concat8 [ 1 1 0 0], L_0x55ab20edffa0, L_0x55ab20ee01f0;
+S_0x55ab20e7adc0 .scope generate, "genblk7[28]" "genblk7[28]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e7af50 .param/l "j" 0 2 164, +C4<011100>;
+L_0x55ab20ee11f0 .part L_0x55ab20eda6a0, 12, 2;
+L_0x55ab20ee1290 .part L_0x55ab20eda6a0, 28, 2;
+S_0x55ab20e7b030 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e7adc0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ee0440 .functor NOT 1, L_0x55ab20ee04b0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ee05a0 .functor AND 1, L_0x55ab20ee0610, L_0x55ab20ee0750, C4<1>, C4<1>;
+L_0x55ab20ee0840 .functor AND 1, L_0x55ab20ee0440, L_0x55ab20ee0900, L_0x55ab20ee0ab0, C4<1>;
+L_0x55ab20ee0b50 .functor AND 1, L_0x55ab20ee0440, L_0x55ab20ee0c20, L_0x55ab20ee0d50, C4<1>;
+L_0x55ab20ee0e90 .functor OR 1, L_0x55ab20ee05a0, L_0x55ab20ee0840, C4<0>, C4<0>;
+L_0x55ab20ee10e0 .functor OR 1, L_0x55ab20ee05a0, L_0x55ab20ee0b50, C4<0>, C4<0>;
+v0x55ab20e7b280_0 .net *"_ivl_1", 0 0, L_0x55ab20ee04b0; 1 drivers
+v0x55ab20e7b380_0 .net *"_ivl_11", 0 0, L_0x55ab20ee0c20; 1 drivers
+v0x55ab20e7b460_0 .net *"_ivl_13", 0 0, L_0x55ab20ee0d50; 1 drivers
+v0x55ab20e7b520_0 .net *"_ivl_14", 0 0, L_0x55ab20ee0e90; 1 drivers
+v0x55ab20e7b600_0 .net *"_ivl_16", 0 0, L_0x55ab20ee10e0; 1 drivers
+v0x55ab20e7b730_0 .net *"_ivl_3", 0 0, L_0x55ab20ee0610; 1 drivers
+v0x55ab20e7b810_0 .net *"_ivl_5", 0 0, L_0x55ab20ee0750; 1 drivers
+v0x55ab20e7b8f0_0 .net *"_ivl_7", 0 0, L_0x55ab20ee0900; 1 drivers
+v0x55ab20e7b9d0_0 .net *"_ivl_9", 0 0, L_0x55ab20ee0ab0; 1 drivers
+v0x55ab20e7bb40_0 .net "a", 1 0, L_0x55ab20ee11f0; 1 drivers
+v0x55ab20e7bc20_0 .net "b", 1 0, L_0x55ab20ee1290; 1 drivers
+v0x55ab20e7bd00_0 .net "b0", 0 0, L_0x55ab20ee0440; 1 drivers
+v0x55ab20e7bdc0_0 .net "f", 0 0, L_0x55ab20ee05a0; 1 drivers
+v0x55ab20e7be80_0 .net "g0", 0 0, L_0x55ab20ee0840; 1 drivers
+v0x55ab20e7bf40_0 .net "g1", 0 0, L_0x55ab20ee0b50; 1 drivers
+v0x55ab20e7c000_0 .net "y", 1 0, L_0x55ab20ee0fa0; 1 drivers
+L_0x55ab20ee04b0 .part L_0x55ab20ee1290, 1, 1;
+L_0x55ab20ee0610 .part L_0x55ab20ee1290, 0, 1;
+L_0x55ab20ee0750 .part L_0x55ab20ee1290, 1, 1;
+L_0x55ab20ee0900 .part L_0x55ab20ee1290, 0, 1;
+L_0x55ab20ee0ab0 .part L_0x55ab20ee11f0, 0, 1;
+L_0x55ab20ee0c20 .part L_0x55ab20ee1290, 0, 1;
+L_0x55ab20ee0d50 .part L_0x55ab20ee11f0, 1, 1;
+L_0x55ab20ee0fa0 .concat8 [ 1 1 0 0], L_0x55ab20ee0e90, L_0x55ab20ee10e0;
+S_0x55ab20e7c160 .scope generate, "genblk7[30]" "genblk7[30]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e7c2f0 .param/l "j" 0 2 164, +C4<011110>;
+L_0x55ab20ee20e0 .part L_0x55ab20eda6a0, 14, 2;
+L_0x55ab20ee2180 .part L_0x55ab20eda6a0, 30, 2;
+S_0x55ab20e7c3d0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e7c160;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ee1330 .functor NOT 1, L_0x55ab20ee13a0, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ee1490 .functor AND 1, L_0x55ab20ee1500, L_0x55ab20ee1640, C4<1>, C4<1>;
+L_0x55ab20ee1730 .functor AND 1, L_0x55ab20ee1330, L_0x55ab20ee17f0, L_0x55ab20ee19a0, C4<1>;
+L_0x55ab20ee1a40 .functor AND 1, L_0x55ab20ee1330, L_0x55ab20ee1b10, L_0x55ab20ee1c40, C4<1>;
+L_0x55ab20ee1d80 .functor OR 1, L_0x55ab20ee1490, L_0x55ab20ee1730, C4<0>, C4<0>;
+L_0x55ab20ee1fd0 .functor OR 1, L_0x55ab20ee1490, L_0x55ab20ee1a40, C4<0>, C4<0>;
+v0x55ab20e7c620_0 .net *"_ivl_1", 0 0, L_0x55ab20ee13a0; 1 drivers
+v0x55ab20e7c720_0 .net *"_ivl_11", 0 0, L_0x55ab20ee1b10; 1 drivers
+v0x55ab20e7c800_0 .net *"_ivl_13", 0 0, L_0x55ab20ee1c40; 1 drivers
+v0x55ab20e7c8c0_0 .net *"_ivl_14", 0 0, L_0x55ab20ee1d80; 1 drivers
+v0x55ab20e7c9a0_0 .net *"_ivl_16", 0 0, L_0x55ab20ee1fd0; 1 drivers
+v0x55ab20e7cad0_0 .net *"_ivl_3", 0 0, L_0x55ab20ee1500; 1 drivers
+v0x55ab20e7cbb0_0 .net *"_ivl_5", 0 0, L_0x55ab20ee1640; 1 drivers
+v0x55ab20e7cc90_0 .net *"_ivl_7", 0 0, L_0x55ab20ee17f0; 1 drivers
+v0x55ab20e7cd70_0 .net *"_ivl_9", 0 0, L_0x55ab20ee19a0; 1 drivers
+v0x55ab20e7cee0_0 .net "a", 1 0, L_0x55ab20ee20e0; 1 drivers
+v0x55ab20e7cfc0_0 .net "b", 1 0, L_0x55ab20ee2180; 1 drivers
+v0x55ab20e7d0a0_0 .net "b0", 0 0, L_0x55ab20ee1330; 1 drivers
+v0x55ab20e7d160_0 .net "f", 0 0, L_0x55ab20ee1490; 1 drivers
+v0x55ab20e7d220_0 .net "g0", 0 0, L_0x55ab20ee1730; 1 drivers
+v0x55ab20e7d2e0_0 .net "g1", 0 0, L_0x55ab20ee1a40; 1 drivers
+v0x55ab20e7d3a0_0 .net "y", 1 0, L_0x55ab20ee1e90; 1 drivers
+L_0x55ab20ee13a0 .part L_0x55ab20ee2180, 1, 1;
+L_0x55ab20ee1500 .part L_0x55ab20ee2180, 0, 1;
+L_0x55ab20ee1640 .part L_0x55ab20ee2180, 1, 1;
+L_0x55ab20ee17f0 .part L_0x55ab20ee2180, 0, 1;
+L_0x55ab20ee19a0 .part L_0x55ab20ee20e0, 0, 1;
+L_0x55ab20ee1b10 .part L_0x55ab20ee2180, 0, 1;
+L_0x55ab20ee1c40 .part L_0x55ab20ee20e0, 1, 1;
+L_0x55ab20ee1e90 .concat8 [ 1 1 0 0], L_0x55ab20ee1d80, L_0x55ab20ee1fd0;
+S_0x55ab20e7d500 .scope generate, "genblk7[32]" "genblk7[32]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e787c0 .param/l "j" 0 2 164, +C4<0100000>;
+L_0x55ab20ee2fd0 .part L_0x55ab20eda6a0, 16, 2;
+L_0x55ab20ee3070 .part L_0x55ab20eda6a0, 32, 2;
+S_0x55ab20e7d790 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e7d500;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ee2220 .functor NOT 1, L_0x55ab20ee2290, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ee2380 .functor AND 1, L_0x55ab20ee23f0, L_0x55ab20ee2530, C4<1>, C4<1>;
+L_0x55ab20ee2620 .functor AND 1, L_0x55ab20ee2220, L_0x55ab20ee26e0, L_0x55ab20ee2890, C4<1>;
+L_0x55ab20ee2930 .functor AND 1, L_0x55ab20ee2220, L_0x55ab20ee2a00, L_0x55ab20ee2b30, C4<1>;
+L_0x55ab20ee2c70 .functor OR 1, L_0x55ab20ee2380, L_0x55ab20ee2620, C4<0>, C4<0>;
+L_0x55ab20ee2ec0 .functor OR 1, L_0x55ab20ee2380, L_0x55ab20ee2930, C4<0>, C4<0>;
+v0x55ab20e7da00_0 .net *"_ivl_1", 0 0, L_0x55ab20ee2290; 1 drivers
+v0x55ab20e7db00_0 .net *"_ivl_11", 0 0, L_0x55ab20ee2a00; 1 drivers
+v0x55ab20e7dbe0_0 .net *"_ivl_13", 0 0, L_0x55ab20ee2b30; 1 drivers
+v0x55ab20e7dca0_0 .net *"_ivl_14", 0 0, L_0x55ab20ee2c70; 1 drivers
+v0x55ab20e7dd80_0 .net *"_ivl_16", 0 0, L_0x55ab20ee2ec0; 1 drivers
+v0x55ab20e7deb0_0 .net *"_ivl_3", 0 0, L_0x55ab20ee23f0; 1 drivers
+v0x55ab20e7df90_0 .net *"_ivl_5", 0 0, L_0x55ab20ee2530; 1 drivers
+v0x55ab20e7e070_0 .net *"_ivl_7", 0 0, L_0x55ab20ee26e0; 1 drivers
+v0x55ab20e7e150_0 .net *"_ivl_9", 0 0, L_0x55ab20ee2890; 1 drivers
+v0x55ab20e7e2c0_0 .net "a", 1 0, L_0x55ab20ee2fd0; 1 drivers
+v0x55ab20e7e3a0_0 .net "b", 1 0, L_0x55ab20ee3070; 1 drivers
+v0x55ab20e7e480_0 .net "b0", 0 0, L_0x55ab20ee2220; 1 drivers
+v0x55ab20e7e540_0 .net "f", 0 0, L_0x55ab20ee2380; 1 drivers
+v0x55ab20e7e600_0 .net "g0", 0 0, L_0x55ab20ee2620; 1 drivers
+v0x55ab20e7e6c0_0 .net "g1", 0 0, L_0x55ab20ee2930; 1 drivers
+v0x55ab20e7e780_0 .net "y", 1 0, L_0x55ab20ee2d80; 1 drivers
+L_0x55ab20ee2290 .part L_0x55ab20ee3070, 1, 1;
+L_0x55ab20ee23f0 .part L_0x55ab20ee3070, 0, 1;
+L_0x55ab20ee2530 .part L_0x55ab20ee3070, 1, 1;
+L_0x55ab20ee26e0 .part L_0x55ab20ee3070, 0, 1;
+L_0x55ab20ee2890 .part L_0x55ab20ee2fd0, 0, 1;
+L_0x55ab20ee2a00 .part L_0x55ab20ee3070, 0, 1;
+L_0x55ab20ee2b30 .part L_0x55ab20ee2fd0, 1, 1;
+L_0x55ab20ee2d80 .concat8 [ 1 1 0 0], L_0x55ab20ee2c70, L_0x55ab20ee2ec0;
+S_0x55ab20e7e8e0 .scope generate, "genblk7[34]" "genblk7[34]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e7ea70 .param/l "j" 0 2 164, +C4<0100010>;
+L_0x55ab20ee3ec0 .part L_0x55ab20eda6a0, 18, 2;
+L_0x55ab20ee3f60 .part L_0x55ab20eda6a0, 34, 2;
+S_0x55ab20e7eb30 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e7e8e0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ee3110 .functor NOT 1, L_0x55ab20ee3180, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ee3270 .functor AND 1, L_0x55ab20ee32e0, L_0x55ab20ee3420, C4<1>, C4<1>;
+L_0x55ab20ee3510 .functor AND 1, L_0x55ab20ee3110, L_0x55ab20ee35d0, L_0x55ab20ee3780, C4<1>;
+L_0x55ab20ee3820 .functor AND 1, L_0x55ab20ee3110, L_0x55ab20ee38f0, L_0x55ab20ee3a20, C4<1>;
+L_0x55ab20ee3b60 .functor OR 1, L_0x55ab20ee3270, L_0x55ab20ee3510, C4<0>, C4<0>;
+L_0x55ab20ee3db0 .functor OR 1, L_0x55ab20ee3270, L_0x55ab20ee3820, C4<0>, C4<0>;
+v0x55ab20e7eda0_0 .net *"_ivl_1", 0 0, L_0x55ab20ee3180; 1 drivers
+v0x55ab20e7eea0_0 .net *"_ivl_11", 0 0, L_0x55ab20ee38f0; 1 drivers
+v0x55ab20e7ef80_0 .net *"_ivl_13", 0 0, L_0x55ab20ee3a20; 1 drivers
+v0x55ab20e7f040_0 .net *"_ivl_14", 0 0, L_0x55ab20ee3b60; 1 drivers
+v0x55ab20e7f120_0 .net *"_ivl_16", 0 0, L_0x55ab20ee3db0; 1 drivers
+v0x55ab20e7f250_0 .net *"_ivl_3", 0 0, L_0x55ab20ee32e0; 1 drivers
+v0x55ab20e7f330_0 .net *"_ivl_5", 0 0, L_0x55ab20ee3420; 1 drivers
+v0x55ab20e7f410_0 .net *"_ivl_7", 0 0, L_0x55ab20ee35d0; 1 drivers
+v0x55ab20e7f4f0_0 .net *"_ivl_9", 0 0, L_0x55ab20ee3780; 1 drivers
+v0x55ab20e7f660_0 .net "a", 1 0, L_0x55ab20ee3ec0; 1 drivers
+v0x55ab20e7f740_0 .net "b", 1 0, L_0x55ab20ee3f60; 1 drivers
+v0x55ab20e7f820_0 .net "b0", 0 0, L_0x55ab20ee3110; 1 drivers
+v0x55ab20e7f8e0_0 .net "f", 0 0, L_0x55ab20ee3270; 1 drivers
+v0x55ab20e7f9a0_0 .net "g0", 0 0, L_0x55ab20ee3510; 1 drivers
+v0x55ab20e7fa60_0 .net "g1", 0 0, L_0x55ab20ee3820; 1 drivers
+v0x55ab20e7fb20_0 .net "y", 1 0, L_0x55ab20ee3c70; 1 drivers
+L_0x55ab20ee3180 .part L_0x55ab20ee3f60, 1, 1;
+L_0x55ab20ee32e0 .part L_0x55ab20ee3f60, 0, 1;
+L_0x55ab20ee3420 .part L_0x55ab20ee3f60, 1, 1;
+L_0x55ab20ee35d0 .part L_0x55ab20ee3f60, 0, 1;
+L_0x55ab20ee3780 .part L_0x55ab20ee3ec0, 0, 1;
+L_0x55ab20ee38f0 .part L_0x55ab20ee3f60, 0, 1;
+L_0x55ab20ee3a20 .part L_0x55ab20ee3ec0, 1, 1;
+L_0x55ab20ee3c70 .concat8 [ 1 1 0 0], L_0x55ab20ee3b60, L_0x55ab20ee3db0;
+S_0x55ab20e7fc80 .scope generate, "genblk7[36]" "genblk7[36]" 2 164, 2 164 0, S_0x55ab20e734d0;
+ .timescale 0 0;
+P_0x55ab20e7fe10 .param/l "j" 0 2 164, +C4<0100100>;
+L_0x55ab20ee4db0 .part L_0x55ab20eda6a0, 20, 2;
+L_0x55ab20ee4e50 .part L_0x55ab20eda6a0, 36, 2;
+LS_0x55ab20ee4ef0_0_0 .concat8 [ 16 2 2 2], L_0x55ab20edacd0, L_0x55ab20edb890, L_0x55ab20edc730, L_0x55ab20edd590;
+LS_0x55ab20ee4ef0_0_4 .concat8 [ 2 2 2 2], L_0x55ab20ede360, L_0x55ab20edf1f0, L_0x55ab20ee00b0, L_0x55ab20ee0fa0;
+LS_0x55ab20ee4ef0_0_8 .concat8 [ 2 2 2 2], L_0x55ab20ee1e90, L_0x55ab20ee2d80, L_0x55ab20ee3c70, L_0x55ab20ee4b60;
+L_0x55ab20ee4ef0 .concat8 [ 22 8 8 0], LS_0x55ab20ee4ef0_0_0, LS_0x55ab20ee4ef0_0_4, LS_0x55ab20ee4ef0_0_8;
+S_0x55ab20e7fed0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e7fc80;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ee4000 .functor NOT 1, L_0x55ab20ee4070, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ee4160 .functor AND 1, L_0x55ab20ee41d0, L_0x55ab20ee4310, C4<1>, C4<1>;
+L_0x55ab20ee4400 .functor AND 1, L_0x55ab20ee4000, L_0x55ab20ee44c0, L_0x55ab20ee4670, C4<1>;
+L_0x55ab20ee4710 .functor AND 1, L_0x55ab20ee4000, L_0x55ab20ee47e0, L_0x55ab20ee4910, C4<1>;
+L_0x55ab20ee4a50 .functor OR 1, L_0x55ab20ee4160, L_0x55ab20ee4400, C4<0>, C4<0>;
+L_0x55ab20ee4ca0 .functor OR 1, L_0x55ab20ee4160, L_0x55ab20ee4710, C4<0>, C4<0>;
+v0x55ab20e80140_0 .net *"_ivl_1", 0 0, L_0x55ab20ee4070; 1 drivers
+v0x55ab20e80240_0 .net *"_ivl_11", 0 0, L_0x55ab20ee47e0; 1 drivers
+v0x55ab20e80320_0 .net *"_ivl_13", 0 0, L_0x55ab20ee4910; 1 drivers
+v0x55ab20e803e0_0 .net *"_ivl_14", 0 0, L_0x55ab20ee4a50; 1 drivers
+v0x55ab20e804c0_0 .net *"_ivl_16", 0 0, L_0x55ab20ee4ca0; 1 drivers
+v0x55ab20e805f0_0 .net *"_ivl_3", 0 0, L_0x55ab20ee41d0; 1 drivers
+v0x55ab20e806d0_0 .net *"_ivl_5", 0 0, L_0x55ab20ee4310; 1 drivers
+v0x55ab20e807b0_0 .net *"_ivl_7", 0 0, L_0x55ab20ee44c0; 1 drivers
+v0x55ab20e80890_0 .net *"_ivl_9", 0 0, L_0x55ab20ee4670; 1 drivers
+v0x55ab20e80a00_0 .net "a", 1 0, L_0x55ab20ee4db0; 1 drivers
+v0x55ab20e80ae0_0 .net "b", 1 0, L_0x55ab20ee4e50; 1 drivers
+v0x55ab20e80bc0_0 .net "b0", 0 0, L_0x55ab20ee4000; 1 drivers
+v0x55ab20e80c80_0 .net "f", 0 0, L_0x55ab20ee4160; 1 drivers
+v0x55ab20e80d40_0 .net "g0", 0 0, L_0x55ab20ee4400; 1 drivers
+v0x55ab20e80e00_0 .net "g1", 0 0, L_0x55ab20ee4710; 1 drivers
+v0x55ab20e80ec0_0 .net "y", 1 0, L_0x55ab20ee4b60; 1 drivers
+L_0x55ab20ee4070 .part L_0x55ab20ee4e50, 1, 1;
+L_0x55ab20ee41d0 .part L_0x55ab20ee4e50, 0, 1;
+L_0x55ab20ee4310 .part L_0x55ab20ee4e50, 1, 1;
+L_0x55ab20ee44c0 .part L_0x55ab20ee4e50, 0, 1;
+L_0x55ab20ee4670 .part L_0x55ab20ee4db0, 0, 1;
+L_0x55ab20ee47e0 .part L_0x55ab20ee4e50, 0, 1;
+L_0x55ab20ee4910 .part L_0x55ab20ee4db0, 1, 1;
+L_0x55ab20ee4b60 .concat8 [ 1 1 0 0], L_0x55ab20ee4a50, L_0x55ab20ee4ca0;
+S_0x55ab20e81100 .scope generate, "genblk6[4]" "genblk6[4]" 2 161, 2 161 0, S_0x55ab20e352b0;
+ .timescale 0 0;
+P_0x55ab20e81300 .param/l "i" 0 2 161, +C4<0100>;
+v0x55ab20e84f10_0 .net *"_ivl_5", 31 0, L_0x55ab20ee53c0; 1 drivers
+L_0x55ab20ee53c0 .part L_0x55ab20ee4ef0, 0, 32;
+S_0x55ab20e813e0 .scope generate, "genblk7[32]" "genblk7[32]" 2 164, 2 164 0, S_0x55ab20e81100;
+ .timescale 0 0;
+P_0x55ab20e815e0 .param/l "j" 0 2 164, +C4<0100000>;
+L_0x55ab20ee61d0 .part L_0x55ab20ee4ef0, 0, 2;
+L_0x55ab20ee6270 .part L_0x55ab20ee4ef0, 32, 2;
+S_0x55ab20e816a0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e813e0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ee54b0 .functor NOT 1, L_0x55ab20ee5520, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ee5610 .functor AND 1, L_0x55ab20ee5680, L_0x55ab20ee57c0, C4<1>, C4<1>;
+L_0x55ab20ee58b0 .functor AND 1, L_0x55ab20ee54b0, L_0x55ab20ee5970, L_0x55ab20ee5af0, C4<1>;
+L_0x55ab20ee5b90 .functor AND 1, L_0x55ab20ee54b0, L_0x55ab20ee5c00, L_0x55ab20ee5d30, C4<1>;
+L_0x55ab20ee5e70 .functor OR 1, L_0x55ab20ee5610, L_0x55ab20ee58b0, C4<0>, C4<0>;
+L_0x55ab20ee60c0 .functor OR 1, L_0x55ab20ee5610, L_0x55ab20ee5b90, C4<0>, C4<0>;
+v0x55ab20e81910_0 .net *"_ivl_1", 0 0, L_0x55ab20ee5520; 1 drivers
+v0x55ab20e81a10_0 .net *"_ivl_11", 0 0, L_0x55ab20ee5c00; 1 drivers
+v0x55ab20e81af0_0 .net *"_ivl_13", 0 0, L_0x55ab20ee5d30; 1 drivers
+v0x55ab20e81bb0_0 .net *"_ivl_14", 0 0, L_0x55ab20ee5e70; 1 drivers
+v0x55ab20e81c90_0 .net *"_ivl_16", 0 0, L_0x55ab20ee60c0; 1 drivers
+v0x55ab20e81dc0_0 .net *"_ivl_3", 0 0, L_0x55ab20ee5680; 1 drivers
+v0x55ab20e81ea0_0 .net *"_ivl_5", 0 0, L_0x55ab20ee57c0; 1 drivers
+v0x55ab20e81f80_0 .net *"_ivl_7", 0 0, L_0x55ab20ee5970; 1 drivers
+v0x55ab20e82060_0 .net *"_ivl_9", 0 0, L_0x55ab20ee5af0; 1 drivers
+v0x55ab20e821d0_0 .net "a", 1 0, L_0x55ab20ee61d0; 1 drivers
+v0x55ab20e822b0_0 .net "b", 1 0, L_0x55ab20ee6270; 1 drivers
+v0x55ab20e82390_0 .net "b0", 0 0, L_0x55ab20ee54b0; 1 drivers
+v0x55ab20e82450_0 .net "f", 0 0, L_0x55ab20ee5610; 1 drivers
+v0x55ab20e82510_0 .net "g0", 0 0, L_0x55ab20ee58b0; 1 drivers
+v0x55ab20e825d0_0 .net "g1", 0 0, L_0x55ab20ee5b90; 1 drivers
+v0x55ab20e82690_0 .net "y", 1 0, L_0x55ab20ee5f80; 1 drivers
+L_0x55ab20ee5520 .part L_0x55ab20ee6270, 1, 1;
+L_0x55ab20ee5680 .part L_0x55ab20ee6270, 0, 1;
+L_0x55ab20ee57c0 .part L_0x55ab20ee6270, 1, 1;
+L_0x55ab20ee5970 .part L_0x55ab20ee6270, 0, 1;
+L_0x55ab20ee5af0 .part L_0x55ab20ee61d0, 0, 1;
+L_0x55ab20ee5c00 .part L_0x55ab20ee6270, 0, 1;
+L_0x55ab20ee5d30 .part L_0x55ab20ee61d0, 1, 1;
+L_0x55ab20ee5f80 .concat8 [ 1 1 0 0], L_0x55ab20ee5e70, L_0x55ab20ee60c0;
+S_0x55ab20e827f0 .scope generate, "genblk7[34]" "genblk7[34]" 2 164, 2 164 0, S_0x55ab20e81100;
+ .timescale 0 0;
+P_0x55ab20e829a0 .param/l "j" 0 2 164, +C4<0100010>;
+L_0x55ab20ee7070 .part L_0x55ab20ee4ef0, 2, 2;
+L_0x55ab20ee7110 .part L_0x55ab20ee4ef0, 34, 2;
+S_0x55ab20e82a40 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e827f0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ee63a0 .functor NOT 1, L_0x55ab20ee6410, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ee64b0 .functor AND 1, L_0x55ab20ee6520, L_0x55ab20ee6660, C4<1>, C4<1>;
+L_0x55ab20ee6750 .functor AND 1, L_0x55ab20ee63a0, L_0x55ab20ee6810, L_0x55ab20ee6990, C4<1>;
+L_0x55ab20ee6a30 .functor AND 1, L_0x55ab20ee63a0, L_0x55ab20ee6aa0, L_0x55ab20ee6bd0, C4<1>;
+L_0x55ab20ee6d10 .functor OR 1, L_0x55ab20ee64b0, L_0x55ab20ee6750, C4<0>, C4<0>;
+L_0x55ab20ee6f60 .functor OR 1, L_0x55ab20ee64b0, L_0x55ab20ee6a30, C4<0>, C4<0>;
+v0x55ab20e82cb0_0 .net *"_ivl_1", 0 0, L_0x55ab20ee6410; 1 drivers
+v0x55ab20e82db0_0 .net *"_ivl_11", 0 0, L_0x55ab20ee6aa0; 1 drivers
+v0x55ab20e82e90_0 .net *"_ivl_13", 0 0, L_0x55ab20ee6bd0; 1 drivers
+v0x55ab20e82f50_0 .net *"_ivl_14", 0 0, L_0x55ab20ee6d10; 1 drivers
+v0x55ab20e83030_0 .net *"_ivl_16", 0 0, L_0x55ab20ee6f60; 1 drivers
+v0x55ab20e83160_0 .net *"_ivl_3", 0 0, L_0x55ab20ee6520; 1 drivers
+v0x55ab20e83240_0 .net *"_ivl_5", 0 0, L_0x55ab20ee6660; 1 drivers
+v0x55ab20e83320_0 .net *"_ivl_7", 0 0, L_0x55ab20ee6810; 1 drivers
+v0x55ab20e83400_0 .net *"_ivl_9", 0 0, L_0x55ab20ee6990; 1 drivers
+v0x55ab20e83570_0 .net "a", 1 0, L_0x55ab20ee7070; 1 drivers
+v0x55ab20e83650_0 .net "b", 1 0, L_0x55ab20ee7110; 1 drivers
+v0x55ab20e83730_0 .net "b0", 0 0, L_0x55ab20ee63a0; 1 drivers
+v0x55ab20e837f0_0 .net "f", 0 0, L_0x55ab20ee64b0; 1 drivers
+v0x55ab20e838b0_0 .net "g0", 0 0, L_0x55ab20ee6750; 1 drivers
+v0x55ab20e83970_0 .net "g1", 0 0, L_0x55ab20ee6a30; 1 drivers
+v0x55ab20e83a30_0 .net "y", 1 0, L_0x55ab20ee6e20; 1 drivers
+L_0x55ab20ee6410 .part L_0x55ab20ee7110, 1, 1;
+L_0x55ab20ee6520 .part L_0x55ab20ee7110, 0, 1;
+L_0x55ab20ee6660 .part L_0x55ab20ee7110, 1, 1;
+L_0x55ab20ee6810 .part L_0x55ab20ee7110, 0, 1;
+L_0x55ab20ee6990 .part L_0x55ab20ee7070, 0, 1;
+L_0x55ab20ee6aa0 .part L_0x55ab20ee7110, 0, 1;
+L_0x55ab20ee6bd0 .part L_0x55ab20ee7070, 1, 1;
+L_0x55ab20ee6e20 .concat8 [ 1 1 0 0], L_0x55ab20ee6d10, L_0x55ab20ee6f60;
+S_0x55ab20e83b90 .scope generate, "genblk7[36]" "genblk7[36]" 2 164, 2 164 0, S_0x55ab20e81100;
+ .timescale 0 0;
+P_0x55ab20e83d20 .param/l "j" 0 2 164, +C4<0100100>;
+L_0x55ab20ee7ed0 .part L_0x55ab20ee4ef0, 4, 2;
+L_0x55ab20ee7f70 .part L_0x55ab20ee4ef0, 36, 2;
+L_0x55ab20ee8010 .concat8 [ 32 2 2 2], L_0x55ab20ee53c0, L_0x55ab20ee5f80, L_0x55ab20ee6e20, L_0x55ab20ee7c80;
+S_0x55ab20e83dc0 .scope module, "s" "recursive_stage1" 2 166, 2 197 0, S_0x55ab20e83b90;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "a";
+ .port_info 1 /INPUT 2 "b";
+ .port_info 2 /OUTPUT 2 "y";
+L_0x55ab20ee71b0 .functor NOT 1, L_0x55ab20ee7220, C4<0>, C4<0>, C4<0>;
+L_0x55ab20ee7310 .functor AND 1, L_0x55ab20ee7380, L_0x55ab20ee74c0, C4<1>, C4<1>;
+L_0x55ab20ee75b0 .functor AND 1, L_0x55ab20ee71b0, L_0x55ab20ee7670, L_0x55ab20ee77f0, C4<1>;
+L_0x55ab20ee7890 .functor AND 1, L_0x55ab20ee71b0, L_0x55ab20ee7900, L_0x55ab20ee7a30, C4<1>;
+L_0x55ab20ee7b70 .functor OR 1, L_0x55ab20ee7310, L_0x55ab20ee75b0, C4<0>, C4<0>;
+L_0x55ab20ee7dc0 .functor OR 1, L_0x55ab20ee7310, L_0x55ab20ee7890, C4<0>, C4<0>;
+v0x55ab20e84030_0 .net *"_ivl_1", 0 0, L_0x55ab20ee7220; 1 drivers
+v0x55ab20e84130_0 .net *"_ivl_11", 0 0, L_0x55ab20ee7900; 1 drivers
+v0x55ab20e84210_0 .net *"_ivl_13", 0 0, L_0x55ab20ee7a30; 1 drivers
+v0x55ab20e842d0_0 .net *"_ivl_14", 0 0, L_0x55ab20ee7b70; 1 drivers
+v0x55ab20e843b0_0 .net *"_ivl_16", 0 0, L_0x55ab20ee7dc0; 1 drivers
+v0x55ab20e844e0_0 .net *"_ivl_3", 0 0, L_0x55ab20ee7380; 1 drivers
+v0x55ab20e845c0_0 .net *"_ivl_5", 0 0, L_0x55ab20ee74c0; 1 drivers
+v0x55ab20e846a0_0 .net *"_ivl_7", 0 0, L_0x55ab20ee7670; 1 drivers
+v0x55ab20e84780_0 .net *"_ivl_9", 0 0, L_0x55ab20ee77f0; 1 drivers
+v0x55ab20e848f0_0 .net "a", 1 0, L_0x55ab20ee7ed0; 1 drivers
+v0x55ab20e849d0_0 .net "b", 1 0, L_0x55ab20ee7f70; 1 drivers
+v0x55ab20e84ab0_0 .net "b0", 0 0, L_0x55ab20ee71b0; 1 drivers
+v0x55ab20e84b70_0 .net "f", 0 0, L_0x55ab20ee7310; 1 drivers
+v0x55ab20e84c30_0 .net "g0", 0 0, L_0x55ab20ee75b0; 1 drivers
+v0x55ab20e84cf0_0 .net "g1", 0 0, L_0x55ab20ee7890; 1 drivers
+v0x55ab20e84db0_0 .net "y", 1 0, L_0x55ab20ee7c80; 1 drivers
+L_0x55ab20ee7220 .part L_0x55ab20ee7f70, 1, 1;
+L_0x55ab20ee7380 .part L_0x55ab20ee7f70, 0, 1;
+L_0x55ab20ee74c0 .part L_0x55ab20ee7f70, 1, 1;
+L_0x55ab20ee7670 .part L_0x55ab20ee7f70, 0, 1;
+L_0x55ab20ee77f0 .part L_0x55ab20ee7ed0, 0, 1;
+L_0x55ab20ee7900 .part L_0x55ab20ee7f70, 0, 1;
+L_0x55ab20ee7a30 .part L_0x55ab20ee7ed0, 1, 1;
+L_0x55ab20ee7c80 .concat8 [ 1 1 0 0], L_0x55ab20ee7b70, L_0x55ab20ee7dc0;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+ "N/A";
+ "<interactive>";
+ "/soft/ProgramFiles/caravel_user_project/verilog/rtl/user_proj_example.v";
diff --git a/verilog/rtl/bakup/user_proj_example.v b/verilog/rtl/bakup/user_proj_example.v
new file mode 100644
index 0000000..26081e9
--- /dev/null
+++ b/verilog/rtl/bakup/user_proj_example.v
@@ -0,0 +1,165 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_example
+ *
+ * This is an example of a (trivially simple) user project,
+ * showing how the user project can connect to the logic
+ * analyzer, the wishbone bus, and the I/O pads.
+ *
+ * This project generates an integer count, which is output
+ * on the user area GPIO pads (digital output only). The
+ * wishbone connection allows the project to be controlled
+ * (start and stop) from the management SoC program.
+ *
+ * See the testbenches in directory "mprj_counter" for the
+ * example programs that drive this user project. The three
+ * testbenches are "io_ports", "la_test1", and "la_test2".
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_proj_example #(
+ parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // IRQ
+ output [2:0] irq
+);
+ wire clk;
+ wire rst;
+
+ wire [`MPRJ_IO_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-1:0] io_oeb;
+
+ wire [31:0] rdata;
+ wire [31:0] wdata;
+ wire [BITS-1:0] count;
+
+ wire valid;
+ wire [3:0] wstrb;
+ wire [31:0] la_write;
+
+ // WB MI A
+ assign valid = wbs_cyc_i && wbs_stb_i;
+ assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ assign wbs_dat_o = rdata;
+ assign wdata = wbs_dat_i;
+
+ // IO
+ assign io_out = count;
+ assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+
+ // IRQ
+ assign irq = 3'b000; // Unused
+
+ // LA
+ assign la_data_out = {{(127-BITS){1'b0}}, count};
+ // Assuming LA probes [63:32] are for controlling the count register
+ assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
+ // Assuming LA probes [65:64] are for controlling the count clk & reset
+ assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+ assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+
+ counter #(
+ .BITS(BITS)
+ ) counter(
+ .clk(clk),
+ .reset(rst),
+ .ready(wbs_ack_o),
+ .valid(valid),
+ .rdata(rdata),
+ .wdata(wbs_dat_i),
+ .wstrb(wstrb),
+ .la_write(la_write),
+ .la_input(la_data_in[63:32]),
+ .count(count)
+ );
+
+endmodule
+
+module counter #(
+ parameter BITS = 32
+)(
+ input clk,
+ input reset,
+ input valid,
+ input [3:0] wstrb,
+ input [BITS-1:0] wdata,
+ input [BITS-1:0] la_write,
+ input [BITS-1:0] la_input,
+ output ready,
+ output [BITS-1:0] rdata,
+ output [BITS-1:0] count
+);
+ reg ready;
+ reg [BITS-1:0] count;
+ reg [BITS-1:0] rdata;
+
+ always @(posedge clk) begin
+ if (reset) begin
+ count <= 0;
+ ready <= 0;
+ end else begin
+ ready <= 1'b0;
+ if (~|la_write) begin
+ count <= count + 1;
+ end
+ if (valid && !ready) begin
+ ready <= 1'b1;
+ rdata <= count;
+ if (wstrb[0]) count[7:0] <= wdata[7:0];
+ if (wstrb[1]) count[15:8] <= wdata[15:8];
+ if (wstrb[2]) count[23:16] <= wdata[23:16];
+ if (wstrb[3]) count[31:24] <= wdata[31:24];
+ end else if (|la_write) begin
+ count <= la_write & la_input;
+ end
+ end
+ end
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/bakup/user_project_wrapper.v b/verilog/rtl/bakup/user_project_wrapper.v
new file mode 100644
index 0000000..5ee1cee
--- /dev/null
+++ b/verilog/rtl/bakup/user_project_wrapper.v
@@ -0,0 +1,123 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper. The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+ parameter BITS = 32
+) (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // Analog (direct connection to GPIO pad---use with caution)
+ // Note that analog I/O is not available on the 7 lowest-numbered
+ // GPIO pads, and so the analog_io indexing is offset from the
+ // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+ inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+user_proj_example mprj (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb (la_oenb),
+
+ // IO Pads
+
+ .io_in (io_in),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+ // IRQ
+ .irq(user_irq)
+);
+
+endmodule // user_project_wrapper
+
+`default_nettype wire
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
new file mode 100644
index 0000000..3537de8
--- /dev/null
+++ b/verilog/rtl/uprj_netlists.v
@@ -0,0 +1,28 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// Include caravel global defines for the number of the user project IO pads
+`include "defines.v"
+`define USE_POWER_PINS
+
+`ifdef GL
+ // Assume default net type to be wire because GL netlists don't have the wire definitions
+ `default_nettype wire
+ `include "gl/user_project_wrapper.v"
+ `include "gl/user_proj_example.v"
+`else
+ `include "user_project_wrapper.v"
+ `include "user_proj_example.v"
+`endif
\ No newline at end of file
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
new file mode 100644
index 0000000..9087394
--- /dev/null
+++ b/verilog/rtl/user_proj_example.v
@@ -0,0 +1,237 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_example
+ *
+ * This is an example of a (trivially simple) user project,
+ * showing how the user project can connect to the logic
+ * analyzer, the wishbone bus, and the I/O pads.
+ *
+ * This project generates an integer count, which is output
+ * on the user area GPIO pads (digital output only). The
+ * wishbone connection allows the project to be controlled
+ * (start and stop) from the management SoC program.
+ *
+ * See the testbenches in directory "mprj_counter" for the
+ * example programs that drive this user project. The three
+ * testbenches are "io_ports", "la_test1", and "la_test2".
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_proj_example #(
+ parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // IRQ
+ output [2:0] irq
+);
+
+ wire [`MPRJ_IO_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-1:0] io_oeb;
+
+ wire [17:0] in1, in2;
+ wire [18:0] out;
+ wire en_mode;
+
+ assign {in1, in2, en_mode} = io_in[`MPRJ_IO_PADS-2:0];
+ assign io_out = {19'd0, out};
+
+ adder adder(.p(in1), .q(in2), .mode(en_mode), .sum(out));
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Company : SMDP-C2SD //
+// Create Date : 10 AUG 2021 //
+// Design Name : Feature Extraction Engine //
+// Target Devices : ASIC (SCL-180nm) : ZedBoard (FPGA-ZC702) //
+// Tool versions : Cadence Genus : Vivado //
+// //
+// Design Engineer : DHAYALAKUMAR M & SKANDHA DEEPSITA S //
+// Project Co-Ordinator : Dr NOOR MAHAMMAD SK //
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+
+
+/*
+mode 00 --> p+q
+ 01 --> p-q
+ 10 --> -p+q
+ 11 --> -p-q
+
+ ps qs mode out P Q
+ a+b 0 0 0 00 0 0 a+b
+ a-b 0 0 1 01 0 1 a+~b+1
+ a-b 0 1 0 01 0 1 a+~b+1
+ a+b 0 1 1 00 0 0 a+b
+ -a+b 1 0 0 10 1 0 ~a+b+1
+ -a-b 1 0 1 11 1 1 ~a+~b+2
+ -a-b 1 1 0 11 1 1 ~a+~b+2
+ -a+b 1 1 1 10 1 0 ~a+b+1
+*/
+
+//`define DSPoperator
+
+module adder(p, q, mode, sum);
+
+parameter num = 18;
+
+output [num:0] sum;
+input [num-1:0] p,q;
+input mode;
+
+wire [num:0] temp, temp1;
+
+`ifdef DSPoperator
+wire [num:0] temp2, temp3;
+ assign temp2[num:0] = p[num-1] ? -{2'b0, p[num-2:0]}:{1'b0,p};
+ assign temp3[num:0] = q[num-1] ? -{2'b0, q[num-2:0]}:{1'b0,q};
+ assign temp[num:0] = mode ? temp2-temp3 : temp2+temp3;
+`else
+ wire [2*num+1:0] x [0:$clog2(num+1)];
+ wire [num:0] a1, b1, a, b;
+
+ assign a1 = {(num+1){p[num-1]}}^{2'b0, p[num-2:0]};
+ assign b1 = {(num+1){mode^q[num-1]}}^{2'b0, q[num-2:0]};
+ assign a[0] = a1[0];
+ assign b[0] = b1[0];
+ assign b[1] = p[num-1]&(q[num-1]^mode);
+ assign a[num] = a1[num]^b1[num];
+
+ assign x[0][1:0]={2{p[num-1]^q[num-1]^mode}}; // Input carry
+
+ genvar i, j;
+ generate
+ begin:ha_fa //halfadder
+ for(i=1; i<num; i=i+1) begin
+ halfadd t0({a1[i],b1[i]}, a[i], b[i+1]);
+ end
+ end
+
+ begin: kgp_gen // kgp generation
+ for (i=0; i<num; i=i+1) begin
+ kgp t(a[i], b[i], x[0][2*i+3:2*i+2]);
+ end
+ end
+ begin:recursiveStg //recursive
+ for (i=0; i<$clog2(num+1); i=i+1)
+ begin
+ assign x[i+1][(2**(i+1))-1:0]=x[i][(2**(i+1))-1:0];
+ for(j=(2**(i+1)); j<2*num+1; j=j+2)
+ begin
+ recursive_stage1 s(x[i][j+1-(2**(i+1)):j-(2**(i+1))],x[i][j+1:j],x[i+1][j+1:j]);
+ end
+ end
+ end
+ begin:addition // SUM Calculation
+ for(i=0; i<num+1; i=i+1) begin
+ assign temp[i] = a[i]^b[i]^x[$clog2(num)][2*i];
+ end
+ end
+ endgenerate
+`endif
+ assign temp1 = -temp;
+ assign sum = temp[num] ? ({temp[num], temp1[num-1:0]}) : (temp);
+
+endmodule
+
+`ifdef DSPoperator
+
+`else
+
+ module kgp(a,b,y);
+
+ input a,b; output [1:0] y;
+
+ assign y[0]=a | b;
+ assign y[1]=a & b;
+
+ endmodule
+
+
+
+ module recursive_stage1(a,b,y);
+
+ input [1:0] a,b; output [1:0] y;
+
+ wire [1:0] y;
+ wire b0;
+ not n1(b0,b[1]);
+ wire f,g0,g1;
+ and a1(f,b[0],b[1]);
+ and a2(g0,b0,b[0],a[0]);
+ and a3(g1,b0,b[0],a[1]);
+
+ or o1(y[0],f,g0);
+ or o2(y[1],f,g1);
+
+ endmodule
+
+ module halfadd(x, sum, carry);
+
+output sum,carry;
+input [1:0] x;
+
+ assign sum = x[1] ^ x[0];
+ assign carry = x[1] & x[0];
+
+endmodule
+
+
+
+module fulladd(x, sum, carry);
+
+output sum,carry;
+input [2:0] x;
+
+wire w;
+ assign w = x[2] ^ x[1];
+ assign sum = w ^ x[0];
+ assign carry = (x[2] & x[1])|(w & x[0]);
+endmodule
+`endif
+`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
new file mode 100644
index 0000000..5ee1cee
--- /dev/null
+++ b/verilog/rtl/user_project_wrapper.v
@@ -0,0 +1,123 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper. The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+ parameter BITS = 32
+) (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // Analog (direct connection to GPIO pad---use with caution)
+ // Note that analog I/O is not available on the 7 lowest-numbered
+ // GPIO pads, and so the analog_io indexing is offset from the
+ // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+ inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+user_proj_example mprj (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb (la_oenb),
+
+ // IO Pads
+
+ .io_in (io_in),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+ // IRQ
+ .irq(user_irq)
+);
+
+endmodule // user_project_wrapper
+
+`default_nettype wire
