commit: 2f2a3f3a560740acb2771b246174bdb2ef8be465
[log] [tgz]
author: Dhayalakumar <61288836+dhayalakumarm@users.noreply.github.com>
Wed Oct 20 20:33:43 2021 +0530
committer: GitHub <noreply@github.com>
Wed Oct 20 20:33:43 2021 +0530
tree: 62894b717928e8f6094f876d2b4363727bd1eac9
parent: e5cd8b705b6186aba0f01cdda4eb7018a456a2f3 [diff]

Add files via upload

verilog/rtl/a.out[Added - diff]
verilog/rtl/bakup/user_proj_example.v[Added - diff]
verilog/rtl/bakup/user_project_wrapper.v[Added - diff]
verilog/rtl/uprj_netlists.v[Added - diff]
verilog/rtl/user_proj_example.v[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]

6 files changed

tree: 62894b717928e8f6094f876d2b4363727bd1eac9

README.md

Caravel User Project

18 bit Adder