commit: 06ba91dc1c7f2694dfe2f392fa85ea0afe106f5b
[log] [tgz]
author: Dhayalakumar <61288836+dhayalakumarm@users.noreply.github.com>
Wed Oct 20 13:19:57 2021 +0530
committer: GitHub <noreply@github.com>
Wed Oct 20 13:19:57 2021 +0530
tree: c48d76fac6ce764082ffc3a72b88c1dbf45e392d
parent: 72f51b1f6450076c84523434c4747d512aeb3072 [diff]

Add files via upload

caravel/verilog/dv/wb_utests/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/chip_io/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/chip_io/chip_io_split.v[Added - diff]
caravel/verilog/dv/wb_utests/chip_io/chip_io_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/chip_io/ports.v[Added - diff]
caravel/verilog/dv/wb_utests/gpio_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/intercon_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/la_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/la_wb/la_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/mem_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/mgmt_protect/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/mprj_ctrl/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/spi_sysctrl_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/spimemio_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/spimemio_wb/flash.hex[Added - diff]
caravel/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/storage_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/sysctrl_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/uart_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v[Added - diff]

28 files changed

tree: c48d76fac6ce764082ffc3a72b88c1dbf45e392d

README.md

Caravel User Project

18 bit Adder