| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/sudoku_accelerator_wrapper,sudoku_accelerator_wrapper,sudoku_accelerator_wrapper,flow_completed,1h33m12s,1h18m25s,90201.82897178642,0.7073027313,40590.82303730389,46.01,1395.79,28710,0,0,0,0,0,0,0,17,0,-1,-1,1470544,300949,-55.46,-77.49,-8.0,-12.23,-13.21,-123914.41,-201129.36,-2778.28,-6111.79,-5820.73,1008694920.0,0.12,47.28,46.63,6.56,4.45,-1,26858,31803,1033,5656,0,0,0,29949,0,0,0,0,0,0,0,4,8094,6711,41,606,9607,0,10213,30.111412225233362,33.21,20,AREA 0,5,45,1,153.6,153.18,0.55,0.0,sky130_fd_sc_hd,2,4 |
