wishbone is available!

verilog/dv/jacaranda_test/jacaranda_test.c

diff --git a/verilog/dv/jacaranda_test/jacaranda_test.c b/verilog/dv/jacaranda_test/jacaranda_test.c
index df7b26b..6c18fcf 100644
--- a/verilog/dv/jacaranda_test/jacaranda_test.c
+++ b/verilog/dv/jacaranda_test/jacaranda_test.c
@@ -24,7 +24,7 @@
 //
 
 #define BASE_ADDR 0x30000000
-#define IMEM_WRITE (BASE_ADDR + 0x100)
+#define IMEM_WRITE BASE_ADDR
 
 static void
 write(uint32_t addr, uint32_t val)
@@ -52,9 +52,9 @@
     // set reset to high
 	reg_la0_data = 1;
 
-    write(IMEM_WRITE + 0x00, 0b11000000);
-    write(IMEM_WRITE + 0x01, 0b11010000);
-    write(IMEM_WRITE + 0x02, 0b10110011);
+    write(IMEM_WRITE, 0x00 << 8 | 0xC0);
+    write(IMEM_WRITE, 0x01 << 8 | 0xD0);
+    write(IMEM_WRITE, 0x02 << 8 | 0xB3);
 
 //    reg_la0_data = 1 << 16 | 0x00 << 8 | 0b11000000; // ldih 0  0xC0
 //    reg_la0_data = 1 << 16 | 0x01 << 8 | 0b11010000; // ldil 0  0xD0

verilog/dv/jacaranda_test/jacaranda_test_tb.v

diff --git a/verilog/dv/jacaranda_test/jacaranda_test_tb.v b/verilog/dv/jacaranda_test/jacaranda_test_tb.v
index ea5a2dc..ea53532 100644
--- a/verilog/dv/jacaranda_test/jacaranda_test_tb.v
+++ b/verilog/dv/jacaranda_test/jacaranda_test_tb.v
@@ -46,7 +46,7 @@
 		$dumpvars(0, jacaranda_test_tb);
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (30) begin
+		repeat (20) begin
 			repeat (1000) @(posedge clock);
 			    $display("+1000 cycles");
 		end

verilog/rtl/jacaranda-8/computer.v

diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v
index 2e84175..5b20099 100644
--- a/verilog/rtl/jacaranda-8/computer.v
+++ b/verilog/rtl/jacaranda-8/computer.v
@@ -90,12 +90,16 @@
     wire [7:0] instr_mem_data; 
     wire instr_mem_en;
 
+    wire [7:0] wb_instr_req_addr;
+
+    assign instr_mem_addr = reset ? wb_instr_req_addr: pc;
+
     wire reset;
 
     assign reset = la_data_in[0];
 
     wire clock;
-    assign clock = ~reset & wb_clk_i;
+    assign clock = reset ? 1'b1 : wb_clk_i;
 
     wishbone wb(.wb_clk_i(wb_clk_i),
                 .wb_rst_i(wb_rst_i),
@@ -107,7 +111,7 @@
                 .wbs_dat_i(wbs_dat_i),
                 .wbs_ack_o(wbs_ack_o),
                 .wbs_dat_o(wbs_dat_o),
-                .instr_mem_addr(instr_mem_addr),
+                .instr_mem_addr(wb_instr_req_addr),
                 .instr_mem_data(instr_mem_data),
                 .instr_mem_en(instr_mem_en));
 
@@ -115,7 +119,8 @@
                         .w_data(instr_mem_data),
                         .w_en(instr_mem_en),
                         .r_data(instr),
-                        .clock(wb_clk_i));
+                        .clock(wb_clk_i),
+                        .reset(reset));
 
     cpu cpu(.clock(clock),
             .reset(reset),

verilog/rtl/jacaranda-8/instr_mem.v

diff --git a/verilog/rtl/jacaranda-8/instr_mem.v b/verilog/rtl/jacaranda-8/instr_mem.v
index 115fb11..0c638e8 100644
--- a/verilog/rtl/jacaranda-8/instr_mem.v
+++ b/verilog/rtl/jacaranda-8/instr_mem.v
@@ -1,13 +1,14 @@
-module instr_mem(addr, w_data, w_en, r_data, clock);
+module instr_mem(addr, w_data, w_en, r_data, clock, reset);
     input [7:0] addr;
     input [7:0] w_data;
     input w_en;
     input clock;
     output [7:0] r_data;
+    input reset;
 
     reg [7:0] mem[0:255];
     
-    assign r_data = mem[addr];
+    assign r_data = reset ? 8'b0 : mem[addr];
 
     always @(posedge clock) begin
         if(w_en) begin

verilog/rtl/jacaranda-8/wishbone.v

diff --git a/verilog/rtl/jacaranda-8/wishbone.v b/verilog/rtl/jacaranda-8/wishbone.v
index 57a1ded..06e2125 100644
--- a/verilog/rtl/jacaranda-8/wishbone.v
+++ b/verilog/rtl/jacaranda-8/wishbone.v
@@ -15,8 +15,7 @@
     output reg instr_mem_en
 );
 
-// 0x3000_0100 - 0x3000_01FF: IMEM_WRITE
-parameter IMEM_WRITE_PREFIX = 24'h3000_01;
+parameter IMEM_WRITE = 32'h3000_0000;
 
 wire valid;
 wire we;
@@ -41,23 +40,18 @@
 
 always @(posedge clk) begin
     if(reset) begin
-        // reset
         ready <= 1'b0;
     end else begin
         if(ready) begin
             ready <= 1'b0;
             instr_mem_en <= 1'b0;
         end
-        // Read
         if (valid && !ready && !we) begin
-            //case(addr)
-            //endcase
             ready <= 1'b1;
-        // Write
         end else if (valid && !ready && we) begin
-            case(addr[31:8])
-                IMEM_WRITE_PREFIX: begin
-                    instr_mem_addr <= addr[7:0];
+            case(addr)
+                IMEM_WRITE: begin
+                    instr_mem_addr <= wdata[15:8];
                     instr_mem_data <= wdata[7:0];
                     instr_mem_en <= 1'b1;
                 end