improve reset logic

verilog/rtl/jacaranda-8/computer.v

diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v
index 9d8b6c6..13dccf4 100644
--- a/verilog/rtl/jacaranda-8/computer.v
+++ b/verilog/rtl/jacaranda-8/computer.v
@@ -83,9 +83,13 @@
 
     reg [7:0] nanaseg_in_data;
 
-    wire reset = la_data_in[0];
-    wire instr_mem_data = wbs_dat_i[7:0];
-    wire instr_mem_addr = reset ? wbs_adr_i[7:0] : pc;
+    wire reset; 
+    wire [7:0] instr_mem_addr;
+    wire [7:0] instr_mem_data; 
+
+    assign reset = la_data_in[16];
+    assign instr_mem_addr = reset ? la_data_in[15:8] : pc;
+    assign instr_mem_data = la_data_in[7:0];
 
     instr_mem instr_mem(.addr(instr_mem_addr),
                         .w_data(instr_mem_data),
@@ -93,7 +97,8 @@
                         .r_data(instr),
                         .clock(wb_clk_i));
 
-    cpu cpu(.clock(wb_clk_i),
+    cpu cpu(.raw_clock(wb_clk_i),
+            .reset(reset),
             .instr(instr),
             .pc(pc),
             .rd_data(rd_data),

verilog/rtl/jacaranda-8/cpu.v

diff --git a/verilog/rtl/jacaranda-8/cpu.v b/verilog/rtl/jacaranda-8/cpu.v
index 2e7d3f2..f2e128f 100644
--- a/verilog/rtl/jacaranda-8/cpu.v
+++ b/verilog/rtl/jacaranda-8/cpu.v
@@ -1,5 +1,6 @@
-module cpu(clock, instr, pc, rd_data, rs_data, mem_w_en, mem_r_data, int_req, int_en, int_vec, reg_w_en);
-    input clock;
+module cpu(raw_clock, reset, instr, pc, rd_data, rs_data, mem_w_en, mem_r_data, int_req, int_en, int_vec, reg_w_en);
+    input raw_clock;
+    input reset;
     input [7:0] instr;
     //割り込み要求線
     input int_req;
@@ -36,6 +37,8 @@
     //レジスタに書き込むデータをALUからのデータか選択する(1)でALUから(0)でそれ以外
     wire reg_alu_w_sel;
 
+    wire clock;
+    assign clock = reset ? 1'b0 : raw_clock;
 
     //ALUの制御信号
     wire [3:0] alu_ctrl;