verilog/dv/jacaranda_test/uart.s

ldih 0
ldil 1
mov r0, r3
ldih f
ldil f
st r0, r3
ldih 4
ldil 1
mov r0, r3
ldih f
ldil d
mov r1, r3
ldih f
ldil e
ld r2, r3
ldih 0
ldil 1
and r2, r3
cmp r2, r3
ldih 0
ldil c
je r3
st r0, r1
ldih 0
ldil 1
add r0, r3
ldih 0
ldil c
jmp r3