どうして.....
diff --git a/verilog/dv/jacaranda_test/instr.c b/verilog/dv/jacaranda_test/instr.c
index c827e65..9b75e22 100644
--- a/verilog/dv/jacaranda_test/instr.c
+++ b/verilog/dv/jacaranda_test/instr.c
@@ -25,5 +25,9 @@
mem[21] = 0xa3;
mem[22] = 0xf1;
mem[23] = 0xc0;
-mem[24] = 0xd6;
-mem[25] = 0xb3;
+mem[24] = 0xd1;
+mem[25] = 0x13;
+mem[26] = 0xc0;
+mem[27] = 0xdc;
+mem[28] = 0xb3;
+
diff --git a/verilog/dv/jacaranda_test/jacaranda_test.c b/verilog/dv/jacaranda_test/jacaranda_test.c
index 54e1dee..746da67 100644
--- a/verilog/dv/jacaranda_test/jacaranda_test.c
+++ b/verilog/dv/jacaranda_test/jacaranda_test.c
@@ -35,10 +35,13 @@
void
reset()
{
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_la0_iena = 0;
reg_la0_oenb = 0;
reg_la0_data = 0;
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
}
void
@@ -52,7 +55,7 @@
// set reset to high
reg_la0_data = 1;
- for(int i = 0; i < 26; ++i) {
+ for(int i = 0; i < 29; ++i) {
write(IMEM_WRITE, i << 8 | mem[i]);
}
diff --git a/verilog/dv/jacaranda_test/uart.s b/verilog/dv/jacaranda_test/uart.s
index 80c1e98..4ad2bff 100644
--- a/verilog/dv/jacaranda_test/uart.s
+++ b/verilog/dv/jacaranda_test/uart.s
@@ -22,5 +22,8 @@
je r3
st r0, r1
ldih 0
-ldil 6
+ldil 1
+add r0, r3
+ldih 0
+ldil c
jmp r3
diff --git a/verilog/rtl/jacaranda-8/UART/tx.v b/verilog/rtl/jacaranda-8/UART/tx.v
index 8ec107c..9389f8a 100644
--- a/verilog/rtl/jacaranda-8/UART/tx.v
+++ b/verilog/rtl/jacaranda-8/UART/tx.v
@@ -19,51 +19,51 @@
assign update_flag = (clk_count == CLK_COUNT_BIT - 32'd1);
assign busy_flag = ~(state == 2'b00);
- always @(posedge reset) begin
- clk_count <= 32'd0;
- tx <= 1'b1;
- state <= 2'b00;
- bit_count <= 3'd0;
- end
-
- always @(posedge clk) begin
- case(state)
- 2'b00: begin
- tx <= 1'b1;
- clk_count = 32'd0;
- bit_count <= 3'd0;
- state <= (begin_flag & tx_en) ? 2'b01 : state;
- end
- 2'b01: begin
- tx <= 1'b0;
- clk_count <= clk_count + 32'd1;
- if(update_flag) begin
- state <= 2'b11;
- clk_count <= 32'd0;
+ always @(posedge clk or posedge reset) begin
+ if(reset) begin
+ clk_count <= 32'd0;
+ bit_count <= 3'd0;
+ state <= 2'b00;
+ tx <= 1'b1;
+ end else begin
+ case(state)
+ 2'b00: begin
+ tx <= 1'b1;
+ clk_count = 32'd0;
+ bit_count <= 3'd0;
+ state <= (begin_flag & tx_en) ? 2'b01 : state;
end
- end
- 2'b11: begin
- tx <= data[bit_count];
- clk_count <= clk_count + 32'd1;
- if(update_flag) begin
- state <= (bit_count == 3'd7) ? 2'b10 : state;
- bit_count <= bit_count + 3'd1;
- clk_count <= 32'd0;
- end
- end
- 2'b10: begin
- tx <= 1'b1;
- clk_count <= clk_count + 32'd1;
- case({update_flag, begin_flag})
- 2'b11: begin
- state <= 2'b01;
+ 2'b01: begin
+ tx <= 1'b0;
+ clk_count <= clk_count + 32'd1;
+ if(update_flag) begin
+ state <= 2'b11;
clk_count <= 32'd0;
- bit_count <= 3'd0;
end
- 2'b10: state <= 2'b00;
- default: state <= state;
- endcase
- end
- endcase
+ end
+ 2'b11: begin
+ tx <= data[bit_count];
+ clk_count <= clk_count + 32'd1;
+ if(update_flag) begin
+ state <= (bit_count == 3'd7) ? 2'b10 : state;
+ bit_count <= bit_count + 3'd1;
+ clk_count <= 32'd0;
+ end
+ end
+ 2'b10: begin
+ tx <= 1'b1;
+ clk_count <= clk_count + 32'd1;
+ case({update_flag, begin_flag})
+ 2'b11: begin
+ state <= 2'b01;
+ clk_count <= 32'd0;
+ bit_count <= 3'd0;
+ end
+ 2'b10: state <= 2'b00;
+ default: state <= state;
+ endcase
+ end
+ endcase
+ end
end
endmodule
diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v
index 4a8692c..84b8325 100644
--- a/verilog/rtl/jacaranda-8/computer.v
+++ b/verilog/rtl/jacaranda-8/computer.v
@@ -53,13 +53,14 @@
wire [6:0] seg_out_3;
/** **/
// output enable
- assign io_oeb[37:36] = 2'b11;
+ assign io_oeb[37:36] = 2'b10;
// UART - GPIO
assign io_out[37] = tx;
- assign io_out[36] = rx;
+ assign rx = io_in[36];
wire [7:0] instr;
wire [7:0] pc;
+ assign la_data_out[7:0] = pc;
wire [7:0] rd_data;
wire [7:0] rs_data;
wire mem_w_en;
