add UART
diff --git a/openlane/computer/config.tcl b/openlane/computer/config.tcl index 4c6779a..f095139 100644 --- a/openlane/computer/config.tcl +++ b/openlane/computer/config.tcl
@@ -25,6 +25,9 @@ set ::env(VERILOG_FILES) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/jacaranda-8/UART/UART.v \ + $script_dir/../../verilog/rtl/jacaranda-8/UART/rx.v \ + $script_dir/../../verilog/rtl/jacaranda-8/UART/tx.v \ $script_dir/../../verilog/rtl/jacaranda-8/alu.v \ $script_dir/../../verilog/rtl/jacaranda-8/cpu.v \ $script_dir/../../verilog/rtl/jacaranda-8/decoder.v \
diff --git a/verilog/rtl/jacaranda-8/UART/UART.v b/verilog/rtl/jacaranda-8/UART/UART.v index 5ba66c6..9262a66 100644 --- a/verilog/rtl/jacaranda-8/UART/UART.v +++ b/verilog/rtl/jacaranda-8/UART/UART.v
@@ -3,6 +3,7 @@ module UART( input wire clk, + input wire reset, input wire tx_en, input wire rx_en, input wire begin_flag, @@ -14,10 +15,10 @@ output wire[7:0] rx_data, output wire busy_flag, output wire receive_flag, - output reg int_req = 1'b0 + output reg int_req ); - reg state = 1'b0; + reg state; always @(negedge clk) begin if(state == 1'b0) begin //データ待機中 @@ -36,8 +37,12 @@ end end end + always @(posedge reset) begin + int_req <= 1'b0; + state <= 1'b0; + end - tx tx1(clk, tx_en, begin_flag, tx_data, tx, busy_flag); + tx tx1(clk, reset, tx_en, begin_flag, tx_data, tx, busy_flag); rx rx1(clk, rx_en, rx, rx_data, receive_flag); endmodule
diff --git a/verilog/rtl/jacaranda-8/UART/tx.v b/verilog/rtl/jacaranda-8/UART/tx.v index c3d8dda..f1ceadf 100644 --- a/verilog/rtl/jacaranda-8/UART/tx.v +++ b/verilog/rtl/jacaranda-8/UART/tx.v
@@ -1,9 +1,10 @@ -module tx(clk, tx_en, begin_flag, data, tx, busy_flag); +module tx(clk, reset, tx_en, begin_flag, data, tx, busy_flag); input wire clk; + input wire reset; input wire tx_en; input wire begin_flag; input wire[7:0] data; - output reg tx = 1'b1; + output reg tx; output wire busy_flag; parameter CLK_FREQ = 50_000_000; @@ -18,6 +19,11 @@ assign update_flag = (clk_count == CLK_COUNT_BIT - 32'd1); assign busy_flag = ~(state == 2'b00); + always @(posedge reset) begin + tx <= 1'b1; + state <= 2'b00; + bit_count <= 3'd0; + end always @(posedge clk) begin case(state) 2'b00: begin
diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v index 9d8b6c6..5b60eda 100644 --- a/verilog/rtl/jacaranda-8/computer.v +++ b/verilog/rtl/jacaranda-8/computer.v
@@ -52,8 +52,11 @@ wire [6:0] seg_out_2; wire [6:0] seg_out_3; /** **/ - - assign io_out[7:0] = pc; + // output enable + assign io_oeb[37:36] = 2'b11; + // UART - GPIO + assign io_out[37] = tx; + assign io_out[36] = rx; wire [7:0] instr; wire [7:0] pc; @@ -171,19 +174,20 @@ end end -// UART UART(.clk(wb_clk_i), -// .tx_en(tx_en), -// .rx_en(rx_en), -// .begin_flag(begin_flag), -// .rx(rx), -// .tx_data(tx_data), -// .tx(tx), -// .rx_data(rx_data), -// .busy_flag(busy_flag), -// .receive_flag(receive_flag), -// .int_req(int_req), -// .access_addr(rs_data), -// .reg_w_en(reg_w_en)); + UART UART(.clk(wb_clk_i), + .reset(reset), + .tx_en(tx_en), + .rx_en(rx_en), + .begin_flag(begin_flag), + .rx(rx), + .tx_data(tx_data), + .tx(tx), + .rx_data(rx_data), + .busy_flag(busy_flag), + .receive_flag(receive_flag), + .int_req(int_req), + .access_addr(rs_data), + .reg_w_en(reg_w_en)); // // LED4 LED4(.in_data(led_in_data), // .begin_flag(led_begin_flag),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 67113ee..c8c2487 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -25,6 +25,9 @@ `else `include "user_project_wrapper.v" `include "user_proj_example.v" + `include "jacaranda-8/UART/UART.v" + `include "jacaranda-8/UART/rx.v" + `include "jacaranda-8/UART/tx.v" `include "jacaranda-8/alu.v" `include "jacaranda-8/cpu.v" `include "jacaranda-8/decoder.v"