commit 39c95b09b22464805cb6e902bad759844741a3af
author Cra2yPierr0t <uchiyama.kazuhide@gmail.com> Wed Oct 13 21:56:29 2021 +0900
committer Cra2yPierr0t <uchiyama.kazuhide@gmail.com> Wed Oct 13 21:56:29 2021 +0900
tree 52b2d8c1d7b2d3a7d2da9fe78d6064ded3373413
parent a4fbe59bb5d1ca5b10a06e620c9ab675ad442971

LSIになってsubが復活！！！

verilog/rtl/jacaranda-8/alu.v

diff --git a/verilog/rtl/jacaranda-8/alu.v b/verilog/rtl/jacaranda-8/alu.v
index ef2c075..81ef874 100644
--- a/verilog/rtl/jacaranda-8/alu.v
+++ b/verilog/rtl/jacaranda-8/alu.v
@@ -16,6 +16,7 @@
             4'b0101: execute = rd >> rs;
             4'b0110: execute = $signed(rd) >>> $signed(rs);
             4'b0111: execute = (rd == rs);
+            4'b1000: execute = rd - rs;
             default: execute = 8'b0000_0000;
             endcase
         end

verilog/rtl/jacaranda-8/alu_controller.v

diff --git a/verilog/rtl/jacaranda-8/alu_controller.v b/verilog/rtl/jacaranda-8/alu_controller.v
index 8b342b2..8394ba8 100644
--- a/verilog/rtl/jacaranda-8/alu_controller.v
+++ b/verilog/rtl/jacaranda-8/alu_controller.v
@@ -8,6 +8,7 @@
         begin
             case(opcode)
                 4'b0001: alu_control = 4'b0000;
+                4'b0010: alu_control = 4'b1000;
                 4'b0011: alu_control = 4'b0001;
                 4'b0100: alu_control = 4'b0010;
                 4'b0101: alu_control = 4'b0011;