LSIになってsubが復活！！！

openlane/computer/config.tcl

diff --git a/openlane/computer/config.tcl b/openlane/computer/config.tcl
index 60b9c89..3d31ce5 100644
--- a/openlane/computer/config.tcl
+++ b/openlane/computer/config.tcl
@@ -44,7 +44,7 @@
 set ::env(CLOCK_PERIOD) 10
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1000 2000"
+set ::env(DIE_AREA) "0 0 1500 2000"
 
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 

verilog/rtl/jacaranda-8/alu.v

diff --git a/verilog/rtl/jacaranda-8/alu.v b/verilog/rtl/jacaranda-8/alu.v
index ef2c075..81ef874 100644
--- a/verilog/rtl/jacaranda-8/alu.v
+++ b/verilog/rtl/jacaranda-8/alu.v
@@ -16,6 +16,7 @@
             4'b0101: execute = rd >> rs;
             4'b0110: execute = $signed(rd) >>> $signed(rs);
             4'b0111: execute = (rd == rs);
+            4'b1000: execute = rd - rs;
             default: execute = 8'b0000_0000;
             endcase
         end

verilog/rtl/jacaranda-8/alu_controller.v

diff --git a/verilog/rtl/jacaranda-8/alu_controller.v b/verilog/rtl/jacaranda-8/alu_controller.v
index 8b342b2..8394ba8 100644
--- a/verilog/rtl/jacaranda-8/alu_controller.v
+++ b/verilog/rtl/jacaranda-8/alu_controller.v
@@ -8,6 +8,7 @@
         begin
             case(opcode)
                 4'b0001: alu_control = 4'b0000;
+                4'b0010: alu_control = 4'b1000;
                 4'b0011: alu_control = 4'b0001;
                 4'b0100: alu_control = 4'b0010;
                 4'b0101: alu_control = 4'b0011;