| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/computer,computer,computer,flow_completed,7h7m54s,0h12m55s,4147.4358974358975,7.8,2073.7179487179487,2.73,4987.37,16175,0,0,0,0,0,0,0,133,0,0,-1,2496822,223610,-120.49,-144.17,-96.55,-87.86,-113.53,-136651.11,-450115.16,-54711.54,-231012.81,-199600.59,1801829379.0,3.02,5.52,8.3,0.0,0.0,-1,9613,14566,639,5519,0,0,0,13351,0,0,0,0,0,0,0,4,4936,5123,42,2188,109600,0,111788,7.488953793155096,133.53,20,AREA 0,5,50,1,153.6,153.18,0.04,0.0,sky130_fd_sc_hd,4,3 |
