commit 15c50d65061f205b9147eaa0545ddc1ddfca3734
author Yuki Azuma <yuhki.yasuda@gmail.com> Sat Oct 09 18:30:48 2021 +0900
committer Yuki Azuma <yuhki.yasuda@gmail.com> Sat Oct 09 18:30:48 2021 +0900
tree 698adc15876c378a2819e92ed958b036e766e561
parent d4e9331a9b9448419639472ff010824e1f8b3206

fix

verilog/dv/jacaranda_test/jacaranda_test.c

diff --git a/verilog/dv/jacaranda_test/jacaranda_test.c b/verilog/dv/jacaranda_test/jacaranda_test.c
index e673d9d..64e5d7d 100644
--- a/verilog/dv/jacaranda_test/jacaranda_test.c
+++ b/verilog/dv/jacaranda_test/jacaranda_test.c
@@ -32,5 +32,9 @@
     reg_la0_data = 0x00 << 8 | 0b11000000; // ldih 0
     reg_la0_data = 0x01 << 8 | 0b11010000; // ldil 0
     reg_la0_data = 0x02 << 8 | 0b10110011; // jmp r3
+
+    reg_la0_data = 0 << 16;
+
+    while(1) {}
 }
 

verilog/dv/jacaranda_test/jacaranda_test_tb.v

diff --git a/verilog/dv/jacaranda_test/jacaranda_test_tb.v b/verilog/dv/jacaranda_test/jacaranda_test_tb.v
index 2c25a43..caeba66 100644
--- a/verilog/dv/jacaranda_test/jacaranda_test_tb.v
+++ b/verilog/dv/jacaranda_test/jacaranda_test_tb.v
@@ -46,7 +46,7 @@
 		$dumpvars(0, jacaranda_test_tb);
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (30) begin
+		repeat (5) begin
 			repeat (1000) @(posedge clock);
 			    $display("+1000 cycles");
 		end