Fix undeclared wire in cpu_core

verilog/rtl/cpu_core.v

diff --git a/verilog/rtl/cpu_core.v b/verilog/rtl/cpu_core.v
index 908c959..350b22a 100644
--- a/verilog/rtl/cpu_core.v
+++ b/verilog/rtl/cpu_core.v
@@ -257,7 +257,7 @@
 assign debug_reg[15] = wdata;
 assign debug_rdata = debug_reg[debug_sel];
 assign debug_stopped = stopped;
-assign stopped_mod = debug_mode[1] ? debug_mode[0] : stopped;
+wire stopped_mod = debug_mode[1] ? debug_mode[0] : stopped;
 
 // sequential logic
 always @ (posedge clk) begin