commit ee00b8160c2fbc56860129b5a2f3e0279fbb578d
author Tamas Hubai <mpw@htamas.net> Tue Oct 26 18:36:26 2021 +0200
committer Tamas Hubai <mpw@htamas.net> Tue Oct 26 18:44:55 2021 +0200
tree 123325da29382eb7cff77f38ee1e1eef5ad130ab
parent 361442e1e9b14ce5415262285ef82362ef3e4c39

Fix undeclared wire in cpu_core

verilog/rtl/cpu_core.v

diff --git a/verilog/rtl/cpu_core.v b/verilog/rtl/cpu_core.v
index 908c959..350b22a 100644
--- a/verilog/rtl/cpu_core.v
+++ b/verilog/rtl/cpu_core.v
@@ -257,7 +257,7 @@
 assign debug_reg[15] = wdata;
 assign debug_rdata = debug_reg[debug_sel];
 assign debug_stopped = stopped;
-assign stopped_mod = debug_mode[1] ? debug_mode[0] : stopped;
+wire stopped_mod = debug_mode[1] ? debug_mode[0] : stopped;
 
 // sequential logic
 always @ (posedge clk) begin