Add list of verilog files to user_project config

openlane/user_project/config.tcl

diff --git a/openlane/user_project/config.tcl b/openlane/user_project/config.tcl
index 7ac305c..ddd965f 100755
--- a/openlane/user_project/config.tcl
+++ b/openlane/user_project/config.tcl
@@ -19,12 +19,28 @@
 
 set ::env(VERILOG_FILES) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_project.v"
+	$script_dir/../../verilog/rtl/user_project.v \
+	$script_dir/../../verilog/rtl/mcu.v \
+	$script_dir/../../verilog/rtl/cpu_core.v \
+	$script_dir/../../verilog/rtl/alu.v \
+	$script_dir/../../verilog/rtl/instr_mem.v \
+	$script_dir/../../verilog/rtl/prng_wrap.v \
+	$script_dir/../../verilog/rtl/prng.v \
+	$script_dir/../../verilog/rtl/mem_mesh.v \
+	$script_dir/../../verilog/rtl/io_filter_rev.v \
+	$script_dir/../../verilog/rtl/io_filter.v \
+	$script_dir/../../verilog/rtl/pin_compress.v \
+	$script_dir/../../verilog/rtl/pin_decompress.v \
+	$script_dir/../../verilog/rtl/prog_mux.v \
+	$script_dir/../../verilog/rtl/debug_mux.v \
+	$script_dir/../../verilog/rtl/entropy_pool.v \
+	$script_dir/../../verilog/rtl/wb_mux.v \
+	$script_dir/../../verilog/rtl/io_pads.v" \
 
 set ::env(DESIGN_IS_CORE) 0
 
 set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET) "counter.clk"
+set ::env(CLOCK_NET) "mcu_inst.clk"
 set ::env(CLOCK_PERIOD) "10"
 
 set ::env(FP_SIZING) absolute