commit	a456aeae90f96ea05b684646203c8fbc85efc308	[log] [tgz]
author	Tamas Hubai <mpw@htamas.net>	Tue Oct 26 14:04:49 2021 +0200
committer	Tamas Hubai <mpw@htamas.net>	Tue Oct 26 14:04:49 2021 +0200
tree	813c900bc08345557de951de21e3ce57681628fc
parent	9d4892197408ae6e4fa411c630ab5afaf90293de [diff]

Import verilog files to rtl & tb

.gitignore[diff]
verilog/dv/tb/alu_tb.v[Added - diff]
verilog/dv/tb/cpu_core_tb.v[Added - diff]
verilog/dv/tb/debug_mux_tb.v[Added - diff]
verilog/dv/tb/entropy_pool_tb.v[Added - diff]
verilog/dv/tb/instr_mem_tb.v[Added - diff]
verilog/dv/tb/io_filter_rev_tb.v[Added - diff]
verilog/dv/tb/io_filter_tb.v[Added - diff]
verilog/dv/tb/io_pads_tb.v[Added - diff]
verilog/dv/tb/mcu_tb.v[Added - diff]
verilog/dv/tb/mem_mesh_tb.v[Added - diff]
verilog/dv/tb/pin_compress_tb.v[Added - diff]
verilog/dv/tb/pin_decompress_tb.v[Added - diff]
verilog/dv/tb/prng_tb.v[Added - diff]
verilog/dv/tb/prng_wrap_tb.v[Added - diff]
verilog/dv/tb/prog_mux_tb.v[Added - diff]
verilog/dv/tb/wb_mux_tb.v[Added - diff]
verilog/rtl/alu.v[Added - diff]
verilog/rtl/cpu_core.v[Added - diff]
verilog/rtl/debug_mux.v[Added - diff]
verilog/rtl/entropy_pool.v[Added - diff]
verilog/rtl/instr_mem.v[Added - diff]
verilog/rtl/io_filter.v[Added - diff]
verilog/rtl/io_filter_rev.v[Added - diff]
verilog/rtl/io_pads.v[Added - diff]
verilog/rtl/mcu.v[Added - diff]
verilog/rtl/mem_mesh.v[Added - diff]
verilog/rtl/pin_compress.v[Added - diff]
verilog/rtl/pin_decompress.v[Added - diff]
verilog/rtl/prng.v[Added - diff]
verilog/rtl/prng_wrap.v[Added - diff]
verilog/rtl/prog_mux.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_proj_example.v[Deleted - diff]
verilog/rtl/user_project.v[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/wb_mux.v[Added - diff]

37 files changed

tree: 813c900bc08345557de951de21e3ce57681628fc

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.