Add project documentation
diff --git a/LICENSE b/LICENSE index 261eeb9..f9d38b7 100644 --- a/LICENSE +++ b/LICENSE
@@ -1,201 +1,20 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ +Copyright (c) 2021 Tamas Hubai - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: - 1. 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diff --git a/Makefile b/Makefile index f17d771..9d8bf07 100644 --- a/Makefile +++ b/Makefile
@@ -146,6 +146,14 @@ docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \ -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY) --caravel_root $(CARAVEL_ROOT)" +ARGS?=--help +.PHONY: run-precheck-custom +run-precheck-custom: check-precheck check-pdk check-caravel + $(eval INPUT_DIRECTORY := $(shell pwd)) + cd $(PRECHECK_ROOT) && \ + docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \ + -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY) --caravel_root $(CARAVEL_ROOT) $(ARGS)" + # Install PDK using OL's Docker Image .PHONY: pdk-nonnative pdk-nonnative: skywater-pdk skywater-library skywater-timing open_pdks
diff --git a/README.md b/README.md index 3706438..2212ff4 100644 --- a/README.md +++ b/README.md
@@ -1,11 +1,27 @@ -# Caravel User Project +# TreePRAM -[](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml) + -| :exclamation: Important Note | -|-----------------------------------------| +Parallel random access machines (PRAM) are a model of computation used in theoretical computer science. They consist of +several independent processors (random access machines) communicating with each other by sharing the same memory. -## Please fill in your project documentation in this README.md file +PRAMs offer a simple model to teach and understand parallel algorithms but they are impractical to implement in +hardware. Aside from the assumption of unbounded resources they obviously require a memory block with a large number of +IO buses. Since memory blocks typically have a single input and/or output bus, applications where parallel access to +the same memory block is required are forced to use workarounds. These include running memory logic at a higher clock +frequency or adding several copies of the memory block that are kept in sync, which correspond to a lower general speed +and higher die space respectively. +The model we implement in this project offers a compromise between the simplicity of PRAMs and the practical usability +of general-purpose processors. We add one memory block per core and allow them to be either kept in sync for simple +communication or used separately to maximize data storage per unit of die area. To achieve this we extend memory write +operations to include a _spread_ parameter besides the usual address and data. Processor cores are arranged in a binary +tree and spread controls how far the memory write operation spreads in this tree. For instance, if core 0 writes 17 to +memory address 8 with a spread of 2 then 17 is written to address 8 in the memory blocks of cores 0, 1, 2 and 3. +This logic can be turned into a combinatorial circuit between processor cores and memory blocks that we call the +_memory mesh_. -Refer to [README](docs/source/index.rst) for this sample project documentation. +This repository contains a Verilog implementation of the TreePRAM model. It targets the OpenLane flow for the Skywater +130nm process and is an entry for the Google/Efabless MPW-3 shuttle. Source files live in `verilog/rtl` while the +user area of the hardened Caravel chip is available under `gds`. +
diff --git a/docs/source/_static/treepram-bg.png b/docs/source/_static/treepram-bg.png new file mode 100644 index 0000000..0cfa4ac --- /dev/null +++ b/docs/source/_static/treepram-bg.png Binary files differ
diff --git a/docs/source/_static/treepram.png b/docs/source/_static/treepram.png new file mode 100644 index 0000000..7231160 --- /dev/null +++ b/docs/source/_static/treepram.png Binary files differ
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diff --git a/info.yaml b/info.yaml index bdd53ba..d130c39 100644 --- a/info.yaml +++ b/info.yaml
@@ -1,19 +1,19 @@ --- project: - description: "A template SoC for Google sponsored Open MPW shuttles for SKY130." + description: "Implements a version of the parallel random-access machine used in theoretical computer science courses with a memory model based on a binary tree of processor cores." foundry: "SkyWater" - git_url: "https://github.com/efabless/caravel_project_example.git" - organization: "Efabless" - organization_url: "http://efabless.com" - owner: "Tim Edwards" + git_url: "https://github.com/htfab/treepram.git" + organization: "" + organization_url: "" + owner: "Tamas Hubai" process: "SKY130" - project_name: "Caravel" - project_id: "00000000" + project_name: "TreePRAM" + project_id: "00000449" tags: - "Open MPW" - - "Test Harness" - category: "Test Harness" + - "MPW-3" + category: "Processor" top_level_netlist: "caravel/verilog/gl/caravel.v" user_level_netlist: "verilog/gl/user_project_wrapper.v" version: "1.00" - cover_image: "docs/source/_static/caravel_harness.png" + cover_image: "docs/source/_static/treepram-bg.png"
