Update build configuration

openlane/user_project/config.tcl

diff --git a/openlane/user_project/config.tcl b/openlane/user_project/config.tcl
index 057b0b0..0671491 100755
--- a/openlane/user_project/config.tcl
+++ b/openlane/user_project/config.tcl
@@ -36,21 +36,21 @@
 	$script_dir/../../verilog/rtl/debug_mux.v \
 	$script_dir/../../verilog/rtl/entropy_pool.v \
 	$script_dir/../../verilog/rtl/wb_mux.v \
-	$script_dir/../../verilog/rtl/io_pads.v" \
-
+	$script_dir/../../verilog/rtl/io_pads.v"
+ 
 set ::env(DESIGN_IS_CORE) 0
 
-set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_PORT) "mcu_inst.clk"
 set ::env(CLOCK_NET) "mcu_inst.clk"
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "200"
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
+set ::env(DIE_AREA) "0 0 2236 2236"
 
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.05
+#set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.15
 
 # Maximum layer used for routing is metal 4.
 # This is because this macro will be inserted in a top level (user_project_wrapper) 

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 36c664e..c24305d 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -51,7 +51,24 @@
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_project.v"
+	$script_dir/../../verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/user_project.v \
+	$script_dir/../../verilog/rtl/mcu.v \
+	$script_dir/../../verilog/rtl/cpu_core.v \
+	$script_dir/../../verilog/rtl/alu.v \
+	$script_dir/../../verilog/rtl/instr_mem.v \
+	$script_dir/../../verilog/rtl/prng_wrap.v \
+	$script_dir/../../verilog/rtl/prng.v \
+	$script_dir/../../verilog/rtl/mem_mesh.v \
+	$script_dir/../../verilog/rtl/io_filter_rev.v \
+	$script_dir/../../verilog/rtl/io_filter.v \
+	$script_dir/../../verilog/rtl/pin_compress.v \
+	$script_dir/../../verilog/rtl/pin_decompress.v \
+	$script_dir/../../verilog/rtl/prog_mux.v \
+	$script_dir/../../verilog/rtl/debug_mux.v \
+	$script_dir/../../verilog/rtl/entropy_pool.v \
+	$script_dir/../../verilog/rtl/wb_mux.v \
+	$script_dir/../../verilog/rtl/io_pads.v"
 
 set ::env(EXTRA_LEFS) "\
 	$script_dir/../../lef/user_project.lef"

openlane/user_project_wrapper/macro.cfg

diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..08f5a95 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+mprj 342 642 N