Fix wb_ to wbs_ in net names
diff --git a/verilog/dv/tb/mcu_tb.v b/verilog/dv/tb/mcu_tb.v index 1c475c3..e027c0e 100644 --- a/verilog/dv/tb/mcu_tb.v +++ b/verilog/dv/tb/mcu_tb.v
@@ -24,11 +24,11 @@ reg clk; wire wb_clk_i = clk; reg wb_rst_i; -reg wb_stb_i; -reg wb_cyc_i; -reg wb_we_i; -reg [WB_WIDTH-1:0] wb_adr_i; -reg [WB_WIDTH-1:0] wb_dat_i; +reg wbs_stb_i; +reg wbs_cyc_i; +reg wbs_we_i; +reg [WB_WIDTH-1:0] wbs_adr_i; +reg [WB_WIDTH-1:0] wbs_dat_i; wire wbs_ack_o; wire [WB_WIDTH-1:0] wbs_dat_o; reg [LOGIC_PROBES-1:0] la_data_in; @@ -55,11 +55,11 @@ ) mcu_dut ( .wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), - .wb_stb_i(wb_stb_i), - .wb_cyc_i(wb_cyc_i), - .wb_we_i(wb_we_i), - .wb_adr_i(wb_adr_i), - .wb_dat_i(wb_dat_i), + .wbs_stb_i(wbs_stb_i), + .wbs_cyc_i(wbs_cyc_i), + .wbs_we_i(wbs_we_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), .wbs_ack_o(wbs_ack_o), .wbs_dat_o(wbs_dat_o), .la_data_in(la_data_in), @@ -79,60 +79,60 @@ initial begin $monitor("time %4t rh %1b rs %1b wwei %1b wai %32b pdi %4b pdo %4b", - $time, la_data_out[1], la_data_out[2], wb_we_i, wb_adr_i, pin_data_in, pin_data_out); + $time, la_data_out[1], la_data_out[2], wbs_we_i, wbs_adr_i, pin_data_in, pin_data_out); // power up clk = 0; wb_rst_i = 1; - wb_stb_i = 0; - wb_cyc_i = 0; - wb_we_i = 0; - wb_adr_i = 0; - wb_dat_i = 0; + wbs_stb_i = 0; + wbs_cyc_i = 0; + wbs_we_i = 0; + wbs_adr_i = 0; + wbs_dat_i = 0; la_data_in = {(LOGIC_PROBES){1'b0}}; la_oenb = {(LOGIC_PROBES){1'b1}}; pin_data_in = 4'b0000; #10 // wishbone reset off, start communications wb_rst_i = 0; - wb_stb_i = 1; - wb_cyc_i = 1; - wb_we_i = 1; + wbs_stb_i = 1; + wbs_cyc_i = 1; + wbs_we_i = 1; // programming mode - wb_adr_i = 32'b01_000000000000000000000000000000; // set programming mode - wb_dat_i = 32'b00000000000000000000000000000001; // to 1 + wbs_adr_i = 32'b01_000000000000000000000000000000; // set programming mode + wbs_dat_i = 32'b00000000000000000000000000000001; // to 1 #10 // send code for cpu core 0 - wb_adr_i = 32'b00_00000000000000000000000000_0_000; // address 0: - wb_dat_i = 32'b100_000_1_00_0011_100_0000000000001111; // read value from memory cell 15 (joined input) + wbs_adr_i = 32'b00_00000000000000000000000000_0_000; // address 0: + wbs_dat_i = 32'b100_000_1_00_0011_100_0000000000001111; // read value from memory cell 15 (joined input) #10 - wb_adr_i = 32'b00_00000000000000000000000000_0_001; // address 1: - wb_dat_i = 32'b011_000_1_11_0011_111_0000000000000001; // write value to memory cell 0, spread 1 + wbs_adr_i = 32'b00_00000000000000000000000000_0_001; // address 1: + wbs_dat_i = 32'b011_000_1_11_0011_111_0000000000000001; // write value to memory cell 0, spread 1 #10 - wb_adr_i = 32'b00_00000000000000000000000000_0_010; // address 2: - wb_dat_i = 32'b100_000_1_00_0011_011_0000000000000000; // jump to address 0 + wbs_adr_i = 32'b00_00000000000000000000000000_0_010; // address 2: + wbs_dat_i = 32'b100_000_1_00_0011_011_0000000000000000; // jump to address 0 #10 // send code for cpu core 1 - wb_adr_i = 32'b00_00000000000000000000000000_1_000; // address 0: - wb_dat_i = 32'b100_000_1_00_0011_100_0000000000000000; // read value from memory cell 0 + wbs_adr_i = 32'b00_00000000000000000000000000_1_000; // address 0: + wbs_dat_i = 32'b100_000_1_00_0011_100_0000000000000000; // read value from memory cell 0 #10 - wb_adr_i = 32'b00_00000000000000000000000000_1_001; // address 1: - wb_dat_i = 32'b011_000_1_11_0011_111_0000000011100010; // write value to memory cell 14, spread 2 (joined output) + wbs_adr_i = 32'b00_00000000000000000000000000_1_001; // address 1: + wbs_dat_i = 32'b011_000_1_11_0011_111_0000000011100010; // write value to memory cell 14, spread 2 (joined output) #10 - wb_adr_i = 32'b00_00000000000000000000000000_1_010; // address 2: - wb_dat_i = 32'b100_000_1_00_0011_011_0000000000000000; // jump to address 0 + wbs_adr_i = 32'b00_00000000000000000000000000_1_010; // address 2: + wbs_dat_i = 32'b100_000_1_00_0011_011_0000000000000000; // jump to address 0 #10 // set pin directions - wb_adr_i = 32'b01_000000000000000000000000000001; // set pin directions - wb_dat_i = 32'b00000000000000000000000011110000; // first 4 pins are inputs, next 4 pins are outputs + wbs_adr_i = 32'b01_000000000000000000000000000001; // set pin directions + wbs_dat_i = 32'b00000000000000000000000011110000; // first 4 pins are inputs, next 4 pins are outputs #10 // exit programming mode - wb_adr_i = 32'b01_000000000000000000000000000000; // set programming mode - wb_dat_i = 32'b00000000000000000000000000000000; // to 0 + wbs_adr_i = 32'b01_000000000000000000000000000000; // set programming mode + wbs_dat_i = 32'b00000000000000000000000000000000; // to 0 #10 // stop wishbone communications - wb_we_i = 0; - wb_cyc_i = 0; - wb_stb_i = 0; + wbs_we_i = 0; + wbs_cyc_i = 0; + wbs_stb_i = 0; // set input pins pin_data_in = 4'b0011; // wait for data to appear on output pins
diff --git a/verilog/dv/tb/wb_mux_tb.v b/verilog/dv/tb/wb_mux_tb.v index 484bc15..98e742b 100644 --- a/verilog/dv/tb/wb_mux_tb.v +++ b/verilog/dv/tb/wb_mux_tb.v
@@ -12,11 +12,11 @@ parameter IO_PINS = 16; parameter WB_WIDTH = 32; -reg wb_stb_i; -reg wb_cyc_i; -reg wb_we_i; -reg [WB_WIDTH-1:0] wb_adr_i; -reg [WB_WIDTH-1:0] wb_dat_i; +reg wbs_stb_i; +reg wbs_cyc_i; +reg wbs_we_i; +reg [WB_WIDTH-1:0] wbs_adr_i; +reg [WB_WIDTH-1:0] wbs_dat_i; wire wbs_ack_o; wire [WB_WIDTH-1:0] wbs_dat_o; wire prog_we; @@ -41,11 +41,11 @@ .IO_PINS(IO_PINS), .WB_WIDTH(WB_WIDTH) ) wb_mux_dut ( - .wb_stb_i(wb_stb_i), - .wb_cyc_i(wb_cyc_i), - .wb_we_i(wb_we_i), - .wb_adr_i(wb_adr_i), - .wb_dat_i(wb_dat_i), + .wbs_stb_i(wbs_stb_i), + .wbs_cyc_i(wbs_cyc_i), + .wbs_we_i(wbs_we_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), .wbs_ack_o(wbs_ack_o), .wbs_dat_o(wbs_dat_o), .prog_we(prog_we), @@ -68,45 +68,45 @@ $time, wbs_ack_o, wbs_dat_o, prog_we, prog_sel, prog_waddr, prog_wdata, pads_we, pads_waddr, pads_wdata, debug_sel, debug_addr, debug_we, debug_wdata, entropy_word); // before cycle - wb_stb_i = 0; - wb_cyc_i = 0; - wb_we_i = 0; - wb_adr_i = 0; - wb_dat_i = 32'b11111111111111111111111111111111; + wbs_stb_i = 0; + wbs_cyc_i = 0; + wbs_we_i = 0; + wbs_adr_i = 0; + wbs_dat_i = 32'b11111111111111111111111111111111; debug_rdata = 16'b1111000010101010; #10 // prog read (no effect) - wb_stb_i = 1; - wb_cyc_i = 1; - wb_adr_i = 32'b00_0000000000000000000_101_11011011; + wbs_stb_i = 1; + wbs_cyc_i = 1; + wbs_adr_i = 32'b00_0000000000000000000_101_11011011; #10 // prog write - wb_we_i = 1; + wbs_we_i = 1; #10 // pads read (no effect) - wb_we_i = 0; - wb_adr_i = 32'b01_000000000000000000000000000001; + wbs_we_i = 0; + wbs_adr_i = 32'b01_000000000000000000000000000001; #10 // pads write - wb_we_i = 1; + wbs_we_i = 1; #10 // debug read - wb_we_i = 0; - wb_adr_i = 32'b10_0000000000000000000000_010_01010; + wbs_we_i = 0; + wbs_adr_i = 32'b10_0000000000000000000000_010_01010; #10 // debug write - wb_we_i = 1; + wbs_we_i = 1; #10 // entropy read (no effect) - wb_we_i = 0; - wb_adr_i = 32'b11_000000000000000000000000000000; + wbs_we_i = 0; + wbs_adr_i = 32'b11_000000000000000000000000000000; #10 // entropy write - wb_we_i = 1; + wbs_we_i = 1; #10 // after cycle - wb_stb_i = 0; - wb_cyc_i = 0; + wbs_stb_i = 0; + wbs_cyc_i = 0; #10 $stop; end
diff --git a/verilog/rtl/mcu.v b/verilog/rtl/mcu.v index f488b00..f5d3288 100644 --- a/verilog/rtl/mcu.v +++ b/verilog/rtl/mcu.v
@@ -49,11 +49,11 @@ )( input wb_clk_i, // wishbone clock input wb_rst_i, // wb reset, active high - input wb_stb_i, // wb strobe - input wb_cyc_i, // wb cycle - input wb_we_i, // wb write enable - input [WB_WIDTH-1:0] wb_adr_i, // wb address - input [WB_WIDTH-1:0] wb_dat_i, // wb input data + input wbs_stb_i, // wb strobe + input wbs_cyc_i, // wb cycle + input wbs_we_i, // wb write enable + input [WB_WIDTH-1:0] wbs_adr_i, // wb address + input [WB_WIDTH-1:0] wbs_dat_i, // wb input data output wbs_ack_o, // wb acknowledge output [WB_WIDTH-1:0] wbs_dat_o, // wb output data input [LOGIC_PROBES-1:0] la_data_in, // logic analyzer probes input @@ -346,11 +346,11 @@ .IO_PINS(IO_PINS), .WB_WIDTH(WB_WIDTH) ) wb_mux_inst ( - .wb_stb_i(wb_stb_i), - .wb_cyc_i(wb_cyc_i), - .wb_we_i(wb_we_i), - .wb_adr_i(wb_adr_i), - .wb_dat_i(wb_dat_i), + .wbs_stb_i(wbs_stb_i), + .wbs_cyc_i(wbs_cyc_i), + .wbs_we_i(wbs_we_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), .wbs_ack_o(wbs_ack_o), .wbs_dat_o(wbs_dat_o), .prog_we(prog_we),
diff --git a/verilog/rtl/user_project.v b/verilog/rtl/user_project.v index 3b1b0ed..81e5d2e 100644 --- a/verilog/rtl/user_project.v +++ b/verilog/rtl/user_project.v
@@ -52,11 +52,11 @@ ) mcu_inst ( .wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), - .wb_stb_i(wb_stb_i), - .wb_cyc_i(wb_cyc_i), - .wb_we_i(wb_we_i), - .wb_adr_i(wb_adr_i), - .wb_dat_i(wb_dat_i), + .wbs_stb_i(wbs_stb_i), + .wbs_cyc_i(wbs_cyc_i), + .wbs_we_i(wbs_we_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), .wbs_ack_o(wbs_ack_o), .wbs_dat_o(wbs_dat_o), .la_data_in(la_data_in),
diff --git a/verilog/rtl/wb_mux.v b/verilog/rtl/wb_mux.v index e24244e..ccf755b 100644 --- a/verilog/rtl/wb_mux.v +++ b/verilog/rtl/wb_mux.v
@@ -35,11 +35,11 @@ // wishbone interface //input wb_clk_i, // wb clock //input wb_rst_i, // wb reset, active high - input wb_stb_i, // wb strobe signal - input wb_cyc_i, // wb cycle signal, sending on the bus requires wb_stb_i && wb_cyc_i - input wb_we_i, // wb write enable signal, 0=input 1=output - input [WB_WIDTH-1:0] wb_adr_i, // wb address - input [WB_WIDTH-1:0] wb_dat_i, // wb input data + input wbs_stb_i, // wb strobe signal + input wbs_cyc_i, // wb cycle signal, sending on the bus requires wbs_stb_i && wbs_cyc_i + input wbs_we_i, // wb write enable signal, 0=input 1=output + input [WB_WIDTH-1:0] wbs_adr_i, // wb address + input [WB_WIDTH-1:0] wbs_dat_i, // wb input data output wbs_ack_o, // wb acknowledge output [WB_WIDTH-1:0] wbs_dat_o, // wb output data // programmer interface @@ -62,36 +62,36 @@ ); // minimal wishbone logic -wire valid = wb_stb_i && wb_cyc_i; +wire valid = wbs_stb_i && wbs_cyc_i; assign wbs_ack_o = valid; // interface selection -wire[1:0] interface = wb_adr_i[WB_WIDTH-2 +: 2]; +wire[1:0] interface = wbs_adr_i[WB_WIDTH-2 +: 2]; wire if_prog = valid && interface == 2'b00; wire if_pads = valid && interface == 2'b01; wire if_debug = valid && interface == 2'b10; wire if_entropy = valid && interface == 2'b11; // programmer interface -assign prog_we = if_prog && wb_we_i; -assign {prog_sel, prog_waddr} = prog_we ? wb_adr_i[WB_WIDTH-3:0] : 0; -assign prog_wdata = prog_we ? wb_dat_i : 0; +assign prog_we = if_prog && wbs_we_i; +assign {prog_sel, prog_waddr} = prog_we ? wbs_adr_i[WB_WIDTH-3:0] : 0; +assign prog_wdata = prog_we ? wbs_dat_i : 0; // pads interface -assign pads_we = if_pads && wb_we_i; -assign pads_waddr = pads_we ? wb_adr_i[WB_WIDTH-3:0] : 0; -assign pads_wdata = pads_we ? wb_dat_i : 0; +assign pads_we = if_pads && wbs_we_i; +assign pads_waddr = pads_we ? wbs_adr_i[WB_WIDTH-3:0] : 0; +assign pads_wdata = pads_we ? wbs_dat_i : 0; // debugger interface, input -assign {debug_sel, debug_addr} = if_debug ? wb_adr_i[WB_WIDTH-3:0] : 0; -assign debug_we = if_debug && wb_we_i; -assign debug_wdata = debug_we ? wb_dat_i : 0; +assign {debug_sel, debug_addr} = if_debug ? wbs_adr_i[WB_WIDTH-3:0] : 0; +assign debug_we = if_debug && wbs_we_i; +assign debug_wdata = debug_we ? wbs_dat_i : 0; // debugger interface, output -assign wbs_dat_o = (if_debug && !wb_we_i) ? debug_rdata : 0; +assign wbs_dat_o = (if_debug && !wbs_we_i) ? debug_rdata : 0; // entropy pool interface -assign entropy_word = (if_entropy && wb_we_i) ? wb_dat_i : 0; +assign entropy_word = (if_entropy && wbs_we_i) ? wbs_dat_i : 0; endmodule