| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/user_project,user_project,user_project,flow_completed,9h11m37s,-1,94292.37199477419,4.529036256,26401.864158536777,28.56,3576.64,119575,0,0,0,0,0,0,-1,-1,0,-1,-1,9832963,1305890,-92.69,-193.9,-1,0.0,-1,-7229.88,-15467.29,-1,0.0,-1,7486395277.0,6.36,49.02,46.33,12.09,4.8,-1,78633,140664,3560,65591,0,0,0,95299,0,0,0,0,0,0,0,4,22320,18583,37,1552,63407,0,64959,32.25806451612903,31,30,DELAY 1,5,28,1,153.6,153.18,0.28800000000000003,0.0,sky130_fd_sc_hd,4,4 |
