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mpw-003
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slot-026
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0ae7f0121712222f94a1333485329d56d291355d
commit
0ae7f0121712222f94a1333485329d56d291355d
[
log
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author
Tamas Hubai <mpw@htamas.net>
Tue Oct 26 22:35:32 2021 +0200
committer
Tamas Hubai <mpw@htamas.net>
Tue Oct 26 22:35:32 2021 +0200
tree
cc9fa2ebbe475005f75da03b50e28deec735a6de
parent
bbaa5c74a828be158f86ec48a82ac4d24f941497
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diff
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Refactor other parameters to wires
verilog/rtl/cpu_core.v
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diff
]
verilog/rtl/mcu.v
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diff
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verilog/rtl/prng.v
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diff
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verilog/rtl/prng_wrap.v
[
diff
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4 files changed
tree: cc9fa2ebbe475005f75da03b50e28deec735a6de
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
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