Reconfigure design parameters
diff --git a/Makefile b/Makefile
index 188e997..9d8bf07 100644
--- a/Makefile
+++ b/Makefile
@@ -146,10 +146,18 @@
docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY) --caravel_root $(CARAVEL_ROOT)"
+ARGS?=--help
+.PHONY: run-precheck-custom
+run-precheck-custom: check-precheck check-pdk check-caravel
+ $(eval INPUT_DIRECTORY := $(shell pwd))
+ cd $(PRECHECK_ROOT) && \
+ docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY) --caravel_root $(CARAVEL_ROOT) $(ARGS)"
+
# Install PDK using OL's Docker Image
.PHONY: pdk-nonnative
pdk-nonnative: skywater-pdk skywater-library skywater-timing open_pdks
- docker run --rm -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/openlane:current sh -c "cd $(CARAVEL_ROOT); make build-pdk; make gen-sources"
+ docker run --rm -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/openlane:mpw-3a sh -c "cd $(CARAVEL_ROOT); make build-pdk; make gen-sources"
# Clean
.PHONY: clean
diff --git a/openlane/user_project/config.tcl b/openlane/user_project/config.tcl
index 82334ea..54e39fc 100755
--- a/openlane/user_project/config.tcl
+++ b/openlane/user_project/config.tcl
@@ -33,13 +33,12 @@
set ::env(CLOCK_PERIOD) "10"
#set ::env(BASE_SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1200 1200"
+set ::env(FP_SIZING) relative
+set ::env(FP_CORE_UTIL) 25
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.02
+set ::env(PL_TARGET_DENSITY) 0.27
# Maximum layer used for routing is metal 4.
# This is because this macro will be inserted in a top level (user_project_wrapper)
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 699b764..aa32844 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -4,16 +4,16 @@
`default_nettype none
// width of cell grid
-`define WIDTH 8
+`define WIDTH 12
// height of cell grid
-`define HEIGHT 8
+`define HEIGHT 12
// size of width/height field, i.e. clog2(max(WIDTH, HEIGHT))
-`define ADDRSIZE 3
+`define ADDRSIZE 4
// number of input pins = number of output pins
-`define IOPAIRS 8
+`define IOPAIRS 12
// x coordinate of input pins
`define X_IN 0
