eFabless
diff --git a/CMOS OPAMP-SPECS-Madhuri Kadam.pdf b/CMOS OPAMP-SPECS-Madhuri Kadam.pdf new file mode 100644 index 0000000..226f8d8 --- /dev/null +++ b/CMOS OPAMP-SPECS-Madhuri Kadam.pdf Binary files differ
diff --git a/OPAMP_Layout_Files/bsim4v5.out b/OPAMP_Layout_Files/bsim4v5.out new file mode 100644 index 0000000..eb31760 --- /dev/null +++ b/OPAMP_Layout_Files/bsim4v5.out
@@ -0,0 +1,5 @@ +BSIM4v5: Berkeley Short Channel IGFET Model-4 +Developed by Xuemei (Jane) Xi, Mohan Dunga, Prof. Ali Niknejad and Prof. Chenming Hu in 2003. + +++++++++++ BSIM4v5 PARAMETER CHECKING BELOW ++++++++++ +Model = x0:sky130_fd_pr__pfet_01v8__model.5
diff --git a/OPAMP_Layout_Files/mimcapt.ext b/OPAMP_Layout_Files/mimcapt.ext new file mode 100644 index 0000000..38b97c7 --- /dev/null +++ b/OPAMP_Layout_Files/mimcapt.ext
@@ -0,0 +1,15 @@ +timestamp 1629110570 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 1e+06 +resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__cap_mim_m3_1 w=w l=l +node "top" 0 -25.6608 -699 -401 mim 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 419478 2758 0 0 0 0 +node "bot" 0 2220.13 -747 -444 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1301576 5086 0 0 0 0 0 0 +node "m2_n747_n444#" 0 3810.03 -747 -444 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1189184 4362 0 0 0 0 0 0 0 0 +substrate "$SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "bot" "top" 3484.33 +cap "bot" "m2_n747_n444#" 10516.9 +cap "top" "m2_n747_n444#" 830.6 +device csubckt sky130_fd_pr__cap_mim_m3_1 -699 -401 -698 -400 w=997 l=997 "None" "top" 1432 0 "bot" 0 0
diff --git a/OPAMP_Layout_Files/mimcapt.mag b/OPAMP_Layout_Files/mimcapt.mag new file mode 100644 index 0000000..bf23f60 --- /dev/null +++ b/OPAMP_Layout_Files/mimcapt.mag
@@ -0,0 +1,22 @@ +magic +tech sky130A +timestamp 1629110570 +<< metal2 >> +rect -747 -444 346 644 +<< metal3 >> +rect -747 -91 346 644 +rect -747 -444 350 -91 +rect 40 -802 350 -444 +<< mimcap >> +rect -699 61 298 596 +rect -699 -301 -609 61 +rect -255 -301 298 61 +rect -699 -401 298 -301 +<< mimcapcontact >> +rect -609 -301 -255 61 +<< metal4 >> +rect -651 61 -198 124 +rect -651 -301 -609 61 +rect -255 -301 -198 61 +rect -651 -802 -198 -301 +<< end >>
diff --git a/OPAMP_Layout_Files/mimcapt.spice b/OPAMP_Layout_Files/mimcapt.spice new file mode 100644 index 0000000..3a476e6 --- /dev/null +++ b/OPAMP_Layout_Files/mimcapt.spice
@@ -0,0 +1,9 @@ +* SPICE3 file created from mimcapt.ext - technology: sky130A + +.option scale=10000u + +X0 top bot sky130_fd_pr__cap_mim_m3_1 l=997 w=997 +C0 bot m2_n747_n444# 10.52fF +C1 top bot 3.48fF +C2 bot $SUB 2.22fF +C3 m2_n747_n444# $SUB 3.81fF **FLOATING
diff --git a/OPAMP_Layout_Files/opamp1.ext b/OPAMP_Layout_Files/opamp1.ext new file mode 100644 index 0000000..6dbd0e6 --- /dev/null +++ b/OPAMP_Layout_Files/opamp1.ext
@@ -0,0 +1,36 @@ +timestamp 1628848859 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 1e+06 +resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__nfet_01v8 l=l w=w +parameters sky130_fd_pr__pfet_01v8 l=l w=w +node "vo" 3369 2842.93 3208 -1954 ndif 0 0 0 0 0 0 0 0 200799 2400 507424 5428 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 760717 9306 0 0 0 0 0 0 0 0 0 0 0 0 +node "vg" 5709 5656.42 80 -757 pdif 0 0 0 0 0 0 0 0 200799 2400 507424 5428 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 184108 6018 0 0 846689 10722 0 0 0 0 0 0 0 0 0 0 0 0 +node "vinm" 2286 2159.11 3161 -547 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 211757 6454 0 0 69105 1052 0 0 0 0 0 0 0 0 0 0 0 0 +node "vinp" 2271 2112.99 -313 -647 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 209897 6406 0 0 69105 1052 0 0 0 0 0 0 0 0 0 0 0 0 +node "a_80_n503#" 6680 5055.44 80 -503 pdif 0 0 0 0 0 0 0 0 0 0 1347188 13502 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1574855 15078 0 0 0 0 0 0 0 0 0 0 0 0 +node "vbias" 1242 1075.18 2119 559 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81549 2994 0 0 24957 636 0 0 0 0 0 0 0 0 0 0 0 0 +node "w_n634_n1455#" 10411 116483 -634 -1455 nw 0 0 0 0 9706890 17938 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +node "vdd" 9366 144353 -634 183 nw 0 0 0 0 11965920 18524 0 0 344372 2694 359432 2724 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 723314 3450 724950 3498 0 0 0 0 0 0 0 0 0 0 +substrate "gnd" 0 0 1498 -2451 ppd 0 0 0 0 0 0 0 0 395604 4788 398796 4804 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 762400 5412 1076193 6440 0 0 0 0 0 0 0 0 0 0 +cap "w_n634_n1455#" "vinm" 15.54 +cap "vdd" "a_80_n503#" 619.912 +cap "vo" "a_80_n503#" 944.862 +cap "vbias" "a_80_n503#" 24.1011 +cap "vdd" "vbias" 4.6472 +cap "w_n634_n1455#" "vinp" 15.54 +cap "a_80_n503#" "vinm" 19.6275 +cap "vg" "vinp" 17.6458 +cap "w_n634_n1455#" "vg" 439.93 +cap "vo" "vinm" 17.0537 +cap "a_80_n503#" "vinp" 21.45 +cap "w_n634_n1455#" "a_80_n503#" 288.796 +cap "vg" "a_80_n503#" 944.862 +cap "w_n634_n1455#" "vo" 432.715 +device msubckt sky130_fd_pr__nfet_01v8 3208 -2010 3209 -2009 l=56 w=999 "gnd" "vg" 112 0 "gnd" 999 0 "vo" 999 0 +device msubckt sky130_fd_pr__nfet_01v8 1505 -2003 1506 -2002 l=56 w=999 "gnd" "vg" 112 0 "gnd" 999 0 "vg" 999 0 +device msubckt sky130_fd_pr__pfet_01v8 3212 -547 3213 -546 l=52 w=2512 "w_n634_n1455#" "vinm" 104 0 "vo" 2512 0 "a_80_n503#" 2512 0 +device msubckt sky130_fd_pr__pfet_01v8 80 -555 81 -554 l=52 w=2512 "w_n634_n1455#" "vinp" 104 0 "vg" 2512 0 "a_80_n503#" 2512 0 +device msubckt sky130_fd_pr__pfet_01v8 2380 652 2381 653 l=48 w=1004 "vdd" "vbias" 96 0 "a_80_n503#" 1004 0 "vdd" 1004 0
diff --git a/OPAMP_Layout_Files/opamp1.mag b/OPAMP_Layout_Files/opamp1.mag new file mode 100644 index 0000000..9a0d135 --- /dev/null +++ b/OPAMP_Layout_Files/opamp1.mag
@@ -0,0 +1,367 @@ +magic +tech sky130A +timestamp 1628848859 +<< nwell >> +rect -634 183 7076 1735 +rect -634 -1455 7076 -196 +<< nmos >> +rect 1505 -2003 2504 -1947 +rect 3208 -2010 4207 -1954 +<< pmos >> +rect 2380 652 3384 700 +rect 80 -555 2592 -503 +rect 3212 -547 5724 -495 +<< ndiff >> +rect 1505 -1812 2504 -1746 +rect 1505 -1887 1569 -1812 +rect 1793 -1887 2208 -1812 +rect 2432 -1887 2504 -1812 +rect 1505 -1947 2504 -1887 +rect 3208 -1819 4207 -1753 +rect 3208 -1894 3272 -1819 +rect 3496 -1894 3911 -1819 +rect 4135 -1894 4207 -1819 +rect 3208 -1954 4207 -1894 +rect 1505 -2078 2504 -2003 +rect 1505 -2171 1573 -2078 +rect 1797 -2171 2189 -2078 +rect 2413 -2171 2504 -2078 +rect 1505 -2201 2504 -2171 +rect 3208 -2085 4207 -2010 +rect 3208 -2178 3276 -2085 +rect 3500 -2178 3892 -2085 +rect 4116 -2178 4207 -2085 +rect 3208 -2208 4207 -2178 +<< pdiff >> +rect 2380 996 3384 1058 +rect 2380 808 2432 996 +rect 2632 984 3384 996 +rect 2632 808 3152 984 +rect 2380 796 3152 808 +rect 3352 796 3384 984 +rect 2380 700 3384 796 +rect 2380 580 3384 652 +rect 2380 568 3144 580 +rect 2380 380 2432 568 +rect 2632 392 3144 568 +rect 3344 392 3384 580 +rect 2632 380 3384 392 +rect 2380 341 3384 380 +rect 80 -344 2592 -297 +rect 80 -356 1004 -344 +rect 80 -463 122 -356 +rect 674 -451 1004 -356 +rect 1556 -348 2592 -344 +rect 1556 -451 1997 -348 +rect 2549 -451 2592 -348 +rect 674 -463 2592 -451 +rect 80 -503 2592 -463 +rect 3212 -336 5724 -289 +rect 3212 -348 4136 -336 +rect 3212 -455 3254 -348 +rect 3806 -443 4136 -348 +rect 4688 -340 5724 -336 +rect 4688 -443 5129 -340 +rect 5681 -443 5724 -340 +rect 3806 -455 5724 -443 +rect 3212 -495 5724 -455 +rect 80 -610 2592 -555 +rect 80 -614 2001 -610 +rect 80 -717 122 -614 +rect 674 -618 2001 -614 +rect 674 -717 1012 -618 +rect 80 -725 1012 -717 +rect 1564 -713 2001 -618 +rect 2553 -713 2592 -610 +rect 1564 -725 2592 -713 +rect 80 -757 2592 -725 +rect 3212 -602 5724 -547 +rect 3212 -606 5133 -602 +rect 3212 -709 3254 -606 +rect 3806 -610 5133 -606 +rect 3806 -709 4144 -610 +rect 3212 -717 4144 -709 +rect 4696 -705 5133 -610 +rect 5685 -705 5724 -602 +rect 4696 -717 5724 -705 +rect 3212 -749 5724 -717 +<< ndiffc >> +rect 1569 -1887 1793 -1812 +rect 2208 -1887 2432 -1812 +rect 3272 -1894 3496 -1819 +rect 3911 -1894 4135 -1819 +rect 1573 -2171 1797 -2078 +rect 2189 -2171 2413 -2078 +rect 3276 -2178 3500 -2085 +rect 3892 -2178 4116 -2085 +<< pdiffc >> +rect 2432 808 2632 996 +rect 3152 796 3352 984 +rect 2432 380 2632 568 +rect 3144 392 3344 580 +rect 122 -463 674 -356 +rect 1004 -451 1556 -344 +rect 1997 -451 2549 -348 +rect 3254 -455 3806 -348 +rect 4136 -443 4688 -336 +rect 5129 -443 5681 -340 +rect 122 -717 674 -614 +rect 1012 -725 1564 -618 +rect 2001 -713 2553 -610 +rect 3254 -709 3806 -606 +rect 4144 -717 4696 -610 +rect 5133 -705 5685 -602 +<< psubdiff >> +rect 1498 -2276 2500 -2249 +rect 1498 -2392 1561 -2276 +rect 1789 -2279 2500 -2276 +rect 1789 -2392 2189 -2279 +rect 1498 -2395 2189 -2392 +rect 2417 -2395 2500 -2279 +rect 1498 -2451 2500 -2395 +rect 3201 -2283 4203 -2256 +rect 3201 -2399 3264 -2283 +rect 3492 -2286 4203 -2283 +rect 3492 -2399 3892 -2286 +rect 3201 -2402 3892 -2399 +rect 4120 -2402 4203 -2286 +rect 3201 -2452 4203 -2402 +<< nsubdiff >> +rect 2380 1387 3384 1441 +rect 2380 1383 3116 1387 +rect 2380 1195 2444 1383 +rect 2644 1199 3116 1383 +rect 3316 1199 3384 1387 +rect 2644 1195 3384 1199 +rect 2380 1098 3384 1195 +<< psubdiffcont >> +rect 1561 -2392 1789 -2276 +rect 2189 -2395 2417 -2279 +rect 3264 -2399 3492 -2283 +rect 3892 -2402 4120 -2286 +<< nsubdiffcont >> +rect 2444 1195 2644 1383 +rect 3116 1199 3316 1387 +<< poly >> +rect 2119 688 2380 700 +rect 2119 596 2156 688 +rect 2256 652 2380 688 +rect 3384 652 3475 700 +rect 2256 596 2296 652 +rect 2119 559 2296 596 +rect -313 -424 -66 -392 +rect -313 -575 -281 -424 +rect -90 -471 -66 -424 +rect -90 -503 29 -471 +rect 5886 -392 6133 -384 +rect 5886 -455 5934 -392 +rect 5782 -495 5934 -455 +rect -90 -555 80 -503 +rect 2592 -555 2635 -503 +rect 3161 -547 3212 -495 +rect 5724 -543 5934 -495 +rect 6125 -543 6133 -392 +rect 5724 -547 6133 -543 +rect -90 -575 29 -555 +rect -313 -591 29 -575 +rect -313 -647 -66 -591 +rect 5782 -575 6133 -547 +rect 5886 -639 6133 -575 +rect 2554 -1933 3148 -1910 +rect 2554 -1947 2719 -1933 +rect 1397 -2003 1505 -1947 +rect 2504 -1982 2719 -1947 +rect 2768 -1954 3148 -1933 +rect 2768 -1982 3208 -1954 +rect 2504 -2001 3208 -1982 +rect 2504 -2003 2601 -2001 +rect 3100 -2010 3208 -2001 +rect 4207 -2010 4304 -1954 +<< polycont >> +rect 2156 596 2256 688 +rect -281 -575 -90 -424 +rect 5934 -543 6125 -392 +rect 2719 -1982 2768 -1933 +<< locali >> +rect 2381 1387 3387 1447 +rect 2381 1383 3112 1387 +rect 2381 1195 2444 1383 +rect 2644 1203 3112 1383 +rect 2644 1199 3116 1203 +rect 3316 1199 3387 1387 +rect 2644 1195 3387 1199 +rect 2381 996 3387 1195 +rect 2381 812 2428 996 +rect 2632 984 3387 996 +rect 2381 808 2432 812 +rect 2632 808 3152 984 +rect 3352 980 3387 984 +rect 2381 796 3152 808 +rect 3356 796 3387 980 +rect 2381 728 3387 796 +rect 2115 688 2292 696 +rect 2115 596 2156 688 +rect 2256 596 2292 688 +rect 2115 555 2292 596 +rect 2381 580 3383 620 +rect 2381 568 3144 580 +rect 2381 380 2432 568 +rect 2632 392 3144 568 +rect 3344 392 3383 580 +rect 2632 380 3383 392 +rect 2381 364 3383 380 +rect 2365 332 3439 364 +rect 2365 244 2592 332 +rect 2323 -196 2592 244 +rect 3212 252 3439 332 +rect 3212 183 3487 252 +rect 3218 -196 3487 183 +rect 2300 -247 2592 -196 +rect 2300 -292 2587 -247 +rect 90 -336 2587 -292 +rect 3216 -284 3503 -196 +rect 3216 -336 5717 -284 +rect 90 -344 2585 -336 +rect 90 -356 1004 -344 +rect -321 -424 -50 -392 +rect -321 -575 -281 -424 +rect -90 -575 -50 -424 +rect 90 -463 122 -356 +rect 674 -451 1004 -356 +rect 1556 -348 2585 -344 +rect 1556 -451 1997 -348 +rect 2549 -451 2585 -348 +rect 674 -463 2585 -451 +rect 90 -483 2585 -463 +rect 3222 -348 4136 -336 +rect 3222 -455 3254 -348 +rect 3806 -443 4136 -348 +rect 4688 -340 5717 -336 +rect 4688 -443 5129 -340 +rect 5681 -443 5717 -340 +rect 3806 -455 5717 -443 +rect 3222 -475 5717 -455 +rect 5870 -392 6141 -384 +rect 5870 -543 5934 -392 +rect 6125 -543 6141 -392 +rect -321 -647 -50 -575 +rect 94 -610 2589 -570 +rect 94 -614 2001 -610 +rect 94 -717 122 -614 +rect 674 -618 2001 -614 +rect 674 -717 1012 -618 +rect 94 -725 1012 -717 +rect 1564 -713 2001 -618 +rect 2553 -713 2589 -610 +rect 1564 -725 2589 -713 +rect 94 -761 2589 -725 +rect 3226 -602 5721 -562 +rect 3226 -606 5133 -602 +rect 3226 -709 3254 -606 +rect 3806 -610 5133 -606 +rect 3806 -709 4144 -610 +rect 3226 -717 4144 -709 +rect 4696 -705 5133 -610 +rect 5685 -705 5721 -602 +rect 5870 -639 6141 -543 +rect 4696 -717 5721 -705 +rect 3226 -753 5721 -717 +rect 2340 -876 2499 -761 +rect 2332 -989 2499 -876 +rect 3296 -878 3440 -753 +rect 3296 -934 3452 -878 +rect 2332 -1523 2486 -989 +rect 2332 -1595 2821 -1523 +rect 2332 -1632 2828 -1595 +rect 2332 -1779 2486 -1632 +rect 1535 -1801 2486 -1779 +rect 1535 -1812 2477 -1801 +rect 1535 -1887 1569 -1812 +rect 1793 -1887 2208 -1812 +rect 2432 -1887 2477 -1812 +rect 1535 -1913 2477 -1887 +rect 2700 -1933 2828 -1632 +rect 3298 -1786 3452 -934 +rect 3238 -1819 4180 -1786 +rect 3238 -1894 3272 -1819 +rect 3496 -1894 3911 -1819 +rect 4135 -1894 4180 -1819 +rect 3238 -1920 4180 -1894 +rect 2700 -1982 2719 -1933 +rect 2768 -1982 2828 -1933 +rect 2700 -2008 2828 -1982 +rect 1524 -2078 2477 -2029 +rect 1524 -2171 1573 -2078 +rect 1797 -2171 2189 -2078 +rect 2413 -2171 2477 -2078 +rect 1524 -2276 2477 -2171 +rect 1524 -2396 1561 -2276 +rect 1789 -2279 2477 -2276 +rect 1790 -2395 2189 -2279 +rect 2417 -2395 2477 -2279 +rect 1790 -2396 2193 -2395 +rect 2411 -2396 2477 -2395 +rect 1524 -2429 2477 -2396 +rect 3227 -2085 4180 -2036 +rect 3227 -2178 3276 -2085 +rect 3500 -2178 3892 -2085 +rect 4116 -2178 4180 -2085 +rect 3227 -2283 4180 -2178 +rect 3227 -2399 3264 -2283 +rect 3492 -2286 4180 -2283 +rect 3497 -2396 3889 -2286 +rect 3492 -2399 3892 -2396 +rect 3227 -2402 3892 -2399 +rect 4120 -2402 4180 -2286 +rect 3227 -2436 4180 -2402 +<< viali >> +rect 2444 1195 2640 1383 +rect 3112 1203 3116 1387 +rect 3116 1203 3316 1387 +rect 2428 812 2432 996 +rect 2432 812 2632 996 +rect 3152 796 3352 980 +rect 3352 796 3356 980 +rect 1561 -2392 1789 -2279 +rect 1789 -2392 1790 -2279 +rect 1561 -2396 1790 -2392 +rect 2193 -2395 2411 -2279 +rect 2193 -2396 2411 -2395 +rect 3268 -2396 3492 -2286 +rect 3492 -2396 3497 -2286 +rect 3889 -2396 3892 -2286 +rect 3892 -2396 4118 -2286 +<< metal1 >> +rect 2341 1387 3415 1431 +rect 2341 1383 3112 1387 +rect 2341 1195 2444 1383 +rect 2640 1203 3112 1383 +rect 3316 1203 3415 1387 +rect 2640 1195 3415 1203 +rect 2341 996 3415 1195 +rect 2341 812 2428 996 +rect 2632 980 3415 996 +rect 2632 812 3152 980 +rect 2341 796 3152 812 +rect 3356 796 3415 980 +rect 2341 756 3415 796 +rect 1444 -2049 2554 -2042 +rect 1435 -2279 4258 -2049 +rect 1435 -2396 1561 -2279 +rect 1790 -2396 2193 -2279 +rect 2411 -2286 4258 -2279 +rect 2411 -2396 3268 -2286 +rect 3497 -2396 3889 -2286 +rect 4118 -2396 4258 -2286 +rect 1435 -2420 4258 -2396 +rect 1444 -2426 2554 -2420 +rect 3148 -2433 4258 -2420 +<< labels >> +rlabel locali 2787 -1993 2806 -1929 1 vg +rlabel metal1 1819 -2413 1875 -2275 1 gnd +rlabel locali 3354 -1615 3404 -1483 1 vo +rlabel locali -281 -647 -106 -591 1 vinp +rlabel locali 5941 -631 6116 -575 1 vinm +rlabel metal1 2459 1098 2636 1162 1 vdd +rlabel locali 2148 559 2256 588 1 vbias +<< end >>
diff --git a/OPAMP_Layout_Files/opamp1.spice b/OPAMP_Layout_Files/opamp1.spice new file mode 100644 index 0000000..d517da1 --- /dev/null +++ b/OPAMP_Layout_Files/opamp1.spice
@@ -0,0 +1,17 @@ +* SPICE3 file created from opamp2.ext - technology: sky130A + +.option scale=10000u + +X0 vo vg gnd gnd sky130_fd_pr__nfet_01v8 w=999 l=56 +X1 vg vg gnd gnd sky130_fd_pr__nfet_01v8 w=999 l=56 +X2 vdd vbias a_80_n503# vdd sky130_fd_pr__pfet_01v8 w=1004 l=48 +X3 a_80_n503# vinp vg w_n634_n1455# sky130_fd_pr__pfet_01v8 w=2512 l=52 +X4 a_80_n503# vinm vo w_n634_n1455# sky130_fd_pr__pfet_01v8 w=2512 l=52 +C0 vo gnd 2.84fF +C1 vg gnd 5.66fF +C2 vinm gnd 2.16fF +C3 vinp gnd 2.11fF +C4 a_80_n503# gnd 5.06fF +C5 w_n634_n1455# gnd 116.48fF +C6 vdd gnd 144.35fF +
diff --git a/OPAMP_Layout_Files/opamp1_ac.spice b/OPAMP_Layout_Files/opamp1_ac.spice new file mode 100644 index 0000000..0acb0a1 --- /dev/null +++ b/OPAMP_Layout_Files/opamp1_ac.spice
@@ -0,0 +1,54 @@ +* SPICE3 file created from opamp1.ext - technology: sky130A + +.lib "sky130_fd_pr/models/sky130.lib.spice" tt + +X0 vo vg gnd gnd sky130_fd_pr__nfet_01v8 w=9.99 l=.56 +X1 vg vg gnd gnd sky130_fd_pr__nfet_01v8 w=9.99 l=.56 +X2 vdd vbias a_80_n503# vdd sky130_fd_pr__pfet_01v8 w=10.04 l=.48 +X3 a_80_n503# vinp vg w_n634_n1455# sky130_fd_pr__pfet_01v8 w=25.12 l=.52 +X4 a_80_n503# vinm vo w_n634_n1455# sky130_fd_pr__pfet_01v8 w=25.12 l=.52 +C0 vo gnd 2.84fF +C1 vg gnd 5.66fF +C2 vinm gnd 2.16fF +C3 vinp gnd 2.11fF +C4 a_80_n503# gnd 5.06fF +C5 w_n634_n1455# gnd 116.48fF +C6 vdd gnd 144.35fF + +******* DC supply info****** +VDD vdd GND 5 +VBIAS vbias 0 3.9 + +*******Transient analysis AC Source******** +*VINP vinp 0 SIN(3.9 1m 10k 0 0 0) +*VINM vinm 0 SIN(3.9 1m 10k 0 0 180) + +*******AC analysis AC Source****** +VINP vinp 0 dc 3.9 ac 1 +VINM vinm 0 dc 3.9 ac -1 + +*******Tran command******* +*.tran 0.1us 1000us +********Transient Plot ****** +.control +run +*plot V(vinp) V(vinm) +*plot V(vo) +*plot V(vdd) V(vbias) + +******AC Command***** +ac dec 100 1 100meg +*Magnitude dB plot for v(vo) on log scale +plot vdb(vo) xlog + +*Phase degrees plot for v(vo) on log scale +let outd = 57.29*vp(vo) +settype phase outd +plot outd xlimit 1 100meg ylabel 'phase' +let pm = outd + 180 +settype phase pm +plot pm xlimit 1 100meg ylabel 'Phase Margin' + +.endc + +.end \ No newline at end of file
diff --git a/OPAMP_Layout_Files/opamp1_tran.spice b/OPAMP_Layout_Files/opamp1_tran.spice new file mode 100644 index 0000000..12c99cc --- /dev/null +++ b/OPAMP_Layout_Files/opamp1_tran.spice
@@ -0,0 +1,40 @@ +* SPICE3 file created from opamp1.ext - technology: sky130A + +.lib "sky130_fd_pr/models/sky130.lib.spice" tt + +X0 vo vg gnd gnd sky130_fd_pr__nfet_01v8 w=9.99 l=.56 +X1 vg vg gnd gnd sky130_fd_pr__nfet_01v8 w=9.99 l=.56 +X2 vdd vbias a_80_n503# vdd sky130_fd_pr__pfet_01v8 w=10.04 l=.48 +X3 a_80_n503# vinp vg w_n634_n1455# sky130_fd_pr__pfet_01v8 w=25.12 l=.52 +X4 a_80_n503# vinm vo w_n634_n1455# sky130_fd_pr__pfet_01v8 w=25.12 l=.52 +C0 vo gnd 2.84fF +C1 vg gnd 5.66fF +C2 vinm gnd 2.16fF +C3 vinp gnd 2.11fF +C4 a_80_n503# gnd 5.06fF +C5 w_n634_n1455# gnd 116.48fF +C6 vdd gnd 144.35fF + +******* DC supply info****** +VDD vdd GND 5 +VBIAS vbias 0 3.9 + +*******Transient analysis AC Source******** +VINP vinp 0 SIN(3.9 1m 10k 0 0 0) +VINM vinm 0 SIN(3.9 1m 10k 0 0 180) + +*******Tran command******* +.tran 0.1us 1000us + +********Transient Plot ****** +.control +run +plot V(vinp) V(vinm) +plot V(vo) +plot V(vdd) V(vbias) + + + +.endc + +.end \ No newline at end of file
diff --git a/OPAMP_Layout_Files/opamp2.ext b/OPAMP_Layout_Files/opamp2.ext new file mode 100644 index 0000000..912bbeb --- /dev/null +++ b/OPAMP_Layout_Files/opamp2.ext
@@ -0,0 +1,52 @@ +timestamp 1629199385 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 1e+06 +resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__nfet_01v8 l=l w=w +parameters sky130_fd_pr__pfet_01v8 l=l w=w +parameters sky130_fd_pr__res_generic_nd l=l w=w +parameters sky130_fd_pr__cap_mim_m3_1 w=w l=l +node "top" 0 87.142 7741 -365 mim 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 310558 2282 0 0 0 0 +node "vout" 0 12276 7693 -413 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1215886 4666 0 0 0 0 0 0 +node "li_7595_39#" 14 712.361 7595 39 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10670 414 0 0 0 0 0 0 0 0 0 0 0 0 +node "top" 1098 6049.24 4757 79 ndc 0 0 0 0 0 0 0 0 380 78 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 220616 8486 39015 1088 0 0 0 0 0 0 0 0 0 0 +node "a_4676_9#" 1676 0 4676 9 rnd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8170 724 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +node "vo" 6349 11585.3 3104 100 ndif 0 0 0 0 0 0 0 0 201199 2480 507424 5428 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 185137 6174 0 0 1228665 18880 0 0 0 0 0 0 0 0 0 0 0 0 +node "vg" 5709 5656.42 -24 1297 pdif 0 0 0 0 0 0 0 0 200799 2400 507424 5428 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 184108 6018 0 0 846689 10722 0 0 0 0 0 0 0 0 0 0 0 0 +node "vinm" 2286 2159.11 3057 1507 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 211757 6454 0 0 69105 1052 0 0 0 0 0 0 0 0 0 0 0 0 +node "vinp" 2271 2112.99 -417 1407 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 209897 6406 0 0 69105 1052 0 0 0 0 0 0 0 0 0 0 0 0 +node "vout" 2653 9229.42 6948 1552 ndif 0 0 0 0 0 0 0 0 516600 5450 322072 2666 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1355710 15930 16461 540 0 0 0 0 0 0 0 0 0 0 +node "a_n24_1551#" 6680 5055.44 -24 1551 pdif 0 0 0 0 0 0 0 0 0 0 1347188 13502 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1574855 15078 0 0 0 0 0 0 0 0 0 0 0 0 +node "vbias" 4737 10030.2 2205 2706 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 490148 14000 0 0 49053 892 0 0 0 0 0 0 0 0 0 0 0 0 +node "w_n738_599#" 11445 91229.1 -738 599 nw 0 0 0 0 7558171 16386 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +node "vdd" 14068 207163 -738 2237 nw 0 0 0 0 16703366 24594 0 0 344372 2694 688616 5404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2246985 15504 724950 3498 0 0 0 0 0 0 0 0 0 0 +substrate "gnd" 0 0 1394 -397 ppd 0 0 0 0 0 0 0 0 944964 10264 842668 10200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1725804 11220 2791599 24240 1202081 4596 0 0 0 0 0 0 0 0 +equiv "gnd" "gnd" +cap "vo" "vinm" 17.0537 +cap "top" "top" 652.319 +cap "vo" "a_n24_1551#" 944.862 +cap "vout" "vdd" 439.46 +cap "vg" "w_n738_599#" 439.93 +cap "vinm" "a_n24_1551#" 19.6275 +cap "vg" "vinp" 17.6458 +cap "vo" "top" 135.352 +cap "top" "vout" 3486.82 +cap "vout" "vout" 473.184 +cap "vdd" "a_n24_1551#" 619.912 +cap "vg" "a_n24_1551#" 944.862 +cap "vinp" "w_n738_599#" 15.54 +cap "vo" "w_n738_599#" 758.267 +cap "vinm" "w_n738_599#" 15.54 +cap "w_n738_599#" "a_n24_1551#" 288.796 +cap "vinp" "a_n24_1551#" 21.45 +device csubckt sky130_fd_pr__cap_mim_m3_1 7741 -365 7742 -364 w=997 l=997 "None" "top" 1432 0 "vout" 1004 0 +device rsubckt sky130_fd_pr__res_generic_nd 4676 9 4677 10 l=51 w=20 "gnd" "a_4676_9#" 0 0 "vo" 80 0 "top" 78 0 +device msubckt sky130_fd_pr__nfet_01v8 3104 44 3105 45 l=56 w=999 "gnd" "vg" 112 0 "gnd" 999 0 "vo" 999 0 +device msubckt sky130_fd_pr__nfet_01v8 1401 51 1402 52 l=56 w=999 "gnd" "vg" 112 0 "gnd" 999 0 "vg" 999 0 +device msubckt sky130_fd_pr__nfet_01v8 6948 1499 6949 1500 l=53 w=2520 "gnd" "vo" 106 0 "gnd" 2520 0 "vout" 2520 0 +device msubckt sky130_fd_pr__pfet_01v8 3108 1507 3109 1508 l=52 w=2512 "w_n738_599#" "vinm" 104 0 "vo" 2512 0 "a_n24_1551#" 2512 0 +device msubckt sky130_fd_pr__pfet_01v8 -24 1499 -23 1500 l=52 w=2512 "w_n738_599#" "vinp" 104 0 "vg" 2512 0 "a_n24_1551#" 2512 0 +device msubckt sky130_fd_pr__pfet_01v8 7848 2722 7849 2723 l=50 w=1016 "vdd" "vbias" 100 0 "vout" 1016 0 "vdd" 1016 0 +device msubckt sky130_fd_pr__pfet_01v8 2276 2706 2277 2707 l=48 w=1004 "vdd" "vbias" 96 0 "a_n24_1551#" 1004 0 "vdd" 1004 0
diff --git a/OPAMP_Layout_Files/opamp2.mag b/OPAMP_Layout_Files/opamp2.mag new file mode 100644 index 0000000..966b4a6 --- /dev/null +++ b/OPAMP_Layout_Files/opamp2.mag
@@ -0,0 +1,617 @@ +magic +tech sky130A +timestamp 1629199385 +<< nwell >> +rect 6930 3789 9989 3797 +rect -738 2237 9989 3789 +rect 6930 2227 9989 2237 +rect -738 1128 6196 1858 +rect -738 599 3981 1128 +<< nmos >> +rect 6948 1499 9468 1552 +rect 1401 51 2400 107 +rect 3104 44 4103 100 +<< pmos >> +rect 2276 2706 3280 2754 +rect 7848 2722 8864 2772 +rect -24 1499 2488 1551 +rect 3108 1507 5620 1559 +<< ndiff >> +rect 6948 1729 9468 1757 +rect 6948 1724 8920 1729 +rect 6948 1626 7006 1724 +rect 7481 1719 8920 1724 +rect 7481 1626 7951 1719 +rect 6948 1621 7951 1626 +rect 8426 1631 8920 1719 +rect 9395 1631 9468 1729 +rect 8426 1621 9468 1631 +rect 6948 1552 9468 1621 +rect 6948 1421 9468 1499 +rect 6948 1411 7946 1421 +rect 6948 1313 7001 1411 +rect 7476 1323 7946 1411 +rect 8421 1323 8920 1421 +rect 9395 1323 9468 1421 +rect 7476 1313 9468 1323 +rect 6948 1281 9468 1313 +rect 1401 242 2400 308 +rect 1401 167 1465 242 +rect 1689 167 2104 242 +rect 2328 167 2400 242 +rect 1401 107 2400 167 +rect 3104 235 4103 301 +rect 3104 160 3168 235 +rect 3392 160 3807 235 +rect 4031 160 4103 235 +rect 3104 100 4103 160 +rect 1401 -24 2400 51 +rect 1401 -117 1469 -24 +rect 1693 -117 2085 -24 +rect 2309 -117 2400 -24 +rect 1401 -147 2400 -117 +rect 3104 -31 4103 44 +rect 3104 -124 3172 -31 +rect 3396 -124 3788 -31 +rect 4012 -124 4103 -31 +rect 3104 -154 4103 -124 +<< pdiff >> +rect 2276 3050 3280 3112 +rect 2276 2862 2328 3050 +rect 2528 3038 3280 3050 +rect 2528 2862 3048 3038 +rect 2276 2850 3048 2862 +rect 3248 2850 3280 3038 +rect 7848 3030 8864 3096 +rect 2276 2754 3280 2850 +rect 7848 2883 7910 3030 +rect 8244 2883 8462 3030 +rect 8796 2883 8864 3030 +rect 7848 2772 8864 2883 +rect 2276 2634 3280 2706 +rect 2276 2622 3040 2634 +rect 2276 2434 2328 2622 +rect 2528 2446 3040 2622 +rect 3240 2446 3280 2634 +rect 2528 2434 3280 2446 +rect 2276 2395 3280 2434 +rect 7848 2625 8864 2722 +rect 7848 2610 8477 2625 +rect 7848 2463 7910 2610 +rect 8244 2478 8477 2610 +rect 8811 2478 8864 2625 +rect 8244 2463 8864 2478 +rect 7848 2405 8864 2463 +rect -24 1710 2488 1757 +rect -24 1698 900 1710 +rect -24 1591 18 1698 +rect 570 1603 900 1698 +rect 1452 1706 2488 1710 +rect 1452 1603 1893 1706 +rect 2445 1603 2488 1706 +rect 570 1591 2488 1603 +rect -24 1551 2488 1591 +rect 3108 1718 5620 1765 +rect 3108 1706 4032 1718 +rect 3108 1599 3150 1706 +rect 3702 1611 4032 1706 +rect 4584 1714 5620 1718 +rect 4584 1611 5025 1714 +rect 5577 1611 5620 1714 +rect 3702 1599 5620 1611 +rect 3108 1559 5620 1599 +rect -24 1444 2488 1499 +rect -24 1440 1897 1444 +rect -24 1337 18 1440 +rect 570 1436 1897 1440 +rect 570 1337 908 1436 +rect -24 1329 908 1337 +rect 1460 1341 1897 1436 +rect 2449 1341 2488 1444 +rect 1460 1329 2488 1341 +rect -24 1297 2488 1329 +rect 3108 1452 5620 1507 +rect 3108 1448 5029 1452 +rect 3108 1345 3150 1448 +rect 3702 1444 5029 1448 +rect 3702 1345 4040 1444 +rect 3108 1337 4040 1345 +rect 4592 1349 5029 1444 +rect 5581 1349 5620 1452 +rect 4592 1337 5620 1349 +rect 3108 1305 5620 1337 +<< ndiffc >> +rect 7006 1626 7481 1724 +rect 7951 1621 8426 1719 +rect 8920 1631 9395 1729 +rect 7001 1313 7476 1411 +rect 7946 1323 8421 1421 +rect 8920 1323 9395 1421 +rect 1465 167 1689 242 +rect 2104 167 2328 242 +rect 3168 160 3392 235 +rect 3807 160 4031 235 +rect 4686 79 4706 99 +rect 1469 -117 1693 -24 +rect 2085 -117 2309 -24 +rect 4757 79 4776 99 +rect 3172 -124 3396 -31 +rect 3788 -124 4012 -31 +<< pdiffc >> +rect 2328 2862 2528 3050 +rect 3048 2850 3248 3038 +rect 7910 2883 8244 3030 +rect 8462 2883 8796 3030 +rect 2328 2434 2528 2622 +rect 3040 2446 3240 2634 +rect 7910 2463 8244 2610 +rect 8477 2478 8811 2625 +rect 18 1591 570 1698 +rect 900 1603 1452 1710 +rect 1893 1603 2445 1706 +rect 3150 1599 3702 1706 +rect 4032 1611 4584 1718 +rect 5025 1611 5577 1714 +rect 18 1337 570 1440 +rect 908 1329 1460 1436 +rect 1897 1341 2449 1444 +rect 3150 1345 3702 1448 +rect 4040 1337 4592 1444 +rect 5029 1349 5581 1452 +<< psubdiff >> +rect 6942 1215 9464 1254 +rect 6942 1117 6996 1215 +rect 7471 1117 7951 1215 +rect 8426 1117 8925 1215 +rect 9400 1117 9464 1215 +rect 6942 1078 9464 1117 +rect 1394 -222 2396 -195 +rect 1394 -338 1457 -222 +rect 1685 -225 2396 -222 +rect 1685 -338 2085 -225 +rect 1394 -341 2085 -338 +rect 2313 -341 2396 -225 +rect 1394 -397 2396 -341 +rect 3097 -229 4099 -202 +rect 3097 -345 3160 -229 +rect 3388 -232 4099 -229 +rect 3388 -345 3788 -232 +rect 3097 -348 3788 -345 +rect 4016 -348 4099 -232 +rect 3097 -398 4099 -348 +<< nsubdiff >> +rect 2276 3441 3280 3495 +rect 2276 3437 3012 3441 +rect 2276 3249 2340 3437 +rect 2540 3253 3012 3437 +rect 3212 3253 3280 3441 +rect 2540 3249 3280 3253 +rect 2276 3152 3280 3249 +<< psubdiffcont >> +rect 6996 1117 7471 1215 +rect 7951 1117 8426 1215 +rect 8925 1117 9400 1215 +rect 1457 -338 1685 -222 +rect 2085 -341 2313 -225 +rect 3160 -345 3388 -229 +rect 3788 -348 4016 -232 +<< nsubdiffcont >> +rect 2340 3249 2540 3437 +rect 3012 3253 3212 3441 +<< poly >> +rect 5131 2848 5328 2946 +rect 5131 2774 5164 2848 +rect 3328 2754 5164 2774 +rect 2205 2706 2276 2754 +rect 3280 2731 5164 2754 +rect 5293 2774 5328 2848 +rect 5293 2772 7808 2774 +rect 5293 2731 7848 2772 +rect 3280 2722 7848 2731 +rect 8864 2722 8956 2772 +rect 3280 2706 7808 2722 +rect 3328 2697 7808 2706 +rect -417 1630 -170 1662 +rect -417 1479 -385 1630 +rect -194 1583 -170 1630 +rect -194 1551 -75 1583 +rect 5782 1662 6029 1670 +rect 5782 1599 5830 1662 +rect 5678 1559 5830 1599 +rect -194 1499 -24 1551 +rect 2488 1499 2531 1551 +rect 3057 1507 3108 1559 +rect 5620 1511 5830 1559 +rect 6021 1511 6029 1662 +rect 5620 1507 6029 1511 +rect -194 1479 -75 1499 +rect -417 1463 -75 1479 +rect -417 1407 -170 1463 +rect 5678 1479 6029 1507 +rect 6558 1588 6914 1614 +rect 6558 1506 6584 1588 +rect 6684 1552 6914 1588 +rect 6684 1506 6948 1552 +rect 6558 1499 6948 1506 +rect 9468 1499 9511 1552 +rect 6558 1484 6914 1499 +rect 6558 1480 6862 1484 +rect 5782 1415 6029 1479 +rect 2450 121 3044 144 +rect 2450 107 2615 121 +rect 1293 51 1401 107 +rect 2400 72 2615 107 +rect 2664 100 3044 121 +rect 2664 72 3104 100 +rect 2400 53 3104 72 +rect 2400 51 2497 53 +rect 2996 44 3104 53 +rect 4103 44 4200 100 +<< polycont >> +rect 5164 2731 5293 2848 +rect -385 1479 -194 1630 +rect 5830 1511 6021 1662 +rect 6584 1506 6684 1588 +rect 2615 72 2664 121 +<< ndiffres >> +rect 4676 99 4716 109 +rect 4676 79 4686 99 +rect 4706 79 4716 99 +rect 4676 38 4716 79 +rect 4745 99 4786 110 +rect 4745 79 4757 99 +rect 4776 79 4786 99 +rect 4745 70 4786 79 +rect 4746 38 4786 70 +rect 4676 9 4786 38 +<< locali >> +rect 2277 3492 3283 3501 +rect 2277 3451 8109 3492 +rect 2277 3441 8119 3451 +rect 2277 3437 3008 3441 +rect 2277 3249 2340 3437 +rect 2540 3257 3008 3437 +rect 2540 3253 3012 3257 +rect 3212 3253 8119 3441 +rect 2540 3249 8119 3253 +rect 2277 3246 8119 3249 +rect 2277 3050 3283 3246 +rect 7864 3118 8119 3246 +rect 2277 2866 2324 3050 +rect 2528 3038 3283 3050 +rect 2277 2862 2328 2866 +rect 2528 2862 3048 3038 +rect 3248 3034 3283 3038 +rect 2277 2850 3048 2862 +rect 3252 2850 3283 3034 +rect 7844 3030 8867 3118 +rect 2277 2782 3283 2850 +rect 5131 2848 5328 2946 +rect 5131 2731 5164 2848 +rect 5293 2731 5328 2848 +rect 7844 2883 7910 3030 +rect 8244 2883 8462 3030 +rect 8796 2883 8867 3030 +rect 7844 2823 8867 2883 +rect 5131 2697 5328 2731 +rect 2277 2634 3279 2674 +rect 2277 2622 3040 2634 +rect 2277 2434 2328 2622 +rect 2528 2446 3040 2622 +rect 3240 2446 3279 2634 +rect 2528 2434 3279 2446 +rect 2277 2418 3279 2434 +rect 7849 2625 8873 2681 +rect 7849 2610 8477 2625 +rect 7849 2463 7910 2610 +rect 8244 2478 8477 2610 +rect 8811 2622 8873 2625 +rect 8811 2478 8878 2622 +rect 8244 2463 8878 2478 +rect 2261 2386 3335 2418 +rect 7849 2407 8878 2463 +rect 2261 2298 2488 2386 +rect 2219 1858 2488 2298 +rect 3108 2306 3335 2386 +rect 3108 2237 3383 2306 +rect 3114 1858 3383 2237 +rect 8590 2181 8878 2407 +rect 8590 2180 9655 2181 +rect 9867 2180 9984 2185 +rect 8590 1992 9984 2180 +rect 2196 1807 2488 1858 +rect 2196 1762 2483 1807 +rect -14 1718 2483 1762 +rect 3112 1770 3399 1858 +rect 3112 1718 5613 1770 +rect 8923 1763 9211 1992 +rect 9629 1989 9984 1992 +rect -14 1710 2481 1718 +rect -14 1698 900 1710 +rect -425 1630 -154 1662 +rect -425 1479 -385 1630 +rect -194 1479 -154 1630 +rect -14 1591 18 1698 +rect 570 1603 900 1698 +rect 1452 1706 2481 1710 +rect 1452 1603 1893 1706 +rect 2445 1603 2481 1706 +rect 570 1591 2481 1603 +rect -14 1571 2481 1591 +rect 3118 1706 4032 1718 +rect 3118 1599 3150 1706 +rect 3702 1611 4032 1706 +rect 4584 1714 5613 1718 +rect 4584 1611 5025 1714 +rect 5577 1611 5613 1714 +rect 6952 1729 9469 1763 +rect 6952 1724 8920 1729 +rect 3702 1599 5613 1611 +rect 3118 1579 5613 1599 +rect 5766 1662 6037 1670 +rect 5766 1511 5830 1662 +rect 6021 1511 6037 1662 +rect 6952 1626 7006 1724 +rect 7481 1719 8920 1724 +rect 7481 1626 7951 1719 +rect 6952 1621 7951 1626 +rect 8426 1631 8920 1719 +rect 9395 1631 9469 1729 +rect 8426 1621 9469 1631 +rect -425 1407 -154 1479 +rect -10 1444 2485 1484 +rect -10 1440 1897 1444 +rect -10 1337 18 1440 +rect 570 1436 1897 1440 +rect 570 1337 908 1436 +rect -10 1329 908 1337 +rect 1460 1341 1897 1436 +rect 2449 1341 2485 1444 +rect 1460 1329 2485 1341 +rect -10 1293 2485 1329 +rect 3122 1452 5617 1492 +rect 3122 1448 5029 1452 +rect 3122 1345 3150 1448 +rect 3702 1444 5029 1448 +rect 3702 1345 4040 1444 +rect 3122 1337 4040 1345 +rect 4592 1349 5029 1444 +rect 5581 1349 5617 1452 +rect 5766 1415 6037 1511 +rect 6558 1588 6714 1619 +rect 6952 1592 9469 1621 +rect 6558 1506 6584 1588 +rect 6684 1506 6714 1588 +rect 4592 1337 5617 1349 +rect 3122 1301 5617 1337 +rect 2236 1178 2395 1293 +rect 2228 1065 2395 1178 +rect 3192 1176 3336 1301 +rect 3192 1120 3348 1176 +rect 2228 531 2382 1065 +rect 3194 781 3348 1120 +rect 4670 997 4717 1002 +rect 6558 997 6714 1506 +rect 6942 1421 9464 1460 +rect 6942 1411 7946 1421 +rect 6942 1313 7001 1411 +rect 7476 1323 7946 1411 +rect 8421 1323 8920 1421 +rect 9395 1323 9464 1421 +rect 7476 1313 9464 1323 +rect 6942 1217 9464 1313 +rect 6942 1215 7000 1217 +rect 7471 1215 9464 1217 +rect 6942 1117 6996 1215 +rect 7471 1212 7951 1215 +rect 7471 1119 7947 1212 +rect 7471 1117 7951 1119 +rect 8426 1117 8925 1215 +rect 9400 1212 9464 1215 +rect 9405 1119 9464 1212 +rect 9400 1117 9464 1119 +rect 6942 1078 9464 1117 +rect 4670 924 6718 997 +rect 4670 781 4717 924 +rect 8618 824 8830 825 +rect 9867 824 9984 1989 +rect 8618 805 9984 824 +rect 7774 792 8238 795 +rect 7723 789 8238 792 +rect 3194 642 4718 781 +rect 6354 775 8238 789 +rect 6354 735 7824 775 +rect 8176 735 8238 775 +rect 8618 765 8643 805 +rect 8770 765 9984 805 +rect 8618 744 9984 765 +rect 8618 738 8850 744 +rect 8618 735 8830 738 +rect 6354 716 8238 735 +rect 2228 459 2717 531 +rect 2228 422 2724 459 +rect 2228 275 2382 422 +rect 1431 253 2382 275 +rect 1431 242 2373 253 +rect 1431 167 1465 242 +rect 1689 167 2104 242 +rect 2328 167 2373 242 +rect 1431 141 2373 167 +rect 2596 121 2724 422 +rect 3194 268 3348 642 +rect 3134 235 4076 268 +rect 3134 160 3168 235 +rect 3392 160 3807 235 +rect 4031 160 4076 235 +rect 3134 134 4076 160 +rect 2596 72 2615 121 +rect 2664 72 2724 121 +rect 4675 99 4717 642 +rect 6364 622 6401 716 +rect 7723 712 8238 716 +rect 7774 710 8238 712 +rect 6369 112 6396 622 +rect 4792 111 6401 112 +rect 4675 89 4686 99 +rect 2596 46 2724 72 +rect 4676 79 4686 89 +rect 4706 89 4717 99 +rect 4746 99 6401 111 +rect 4706 79 4716 89 +rect 4676 69 4716 79 +rect 4746 79 4757 99 +rect 4776 79 6401 99 +rect 4746 76 6401 79 +rect 4746 71 4809 76 +rect 4746 70 4808 71 +rect 7595 39 7692 149 +rect 1420 -24 2373 25 +rect 1420 -117 1469 -24 +rect 1693 -117 2085 -24 +rect 2309 -117 2373 -24 +rect 1420 -222 2373 -117 +rect 1420 -342 1457 -222 +rect 1685 -225 2373 -222 +rect 1686 -341 2085 -225 +rect 2313 -341 2373 -225 +rect 1686 -342 2089 -341 +rect 2307 -342 2373 -341 +rect 1420 -375 2373 -342 +rect 3123 -31 4076 18 +rect 3123 -124 3172 -31 +rect 3396 -124 3788 -31 +rect 4012 -124 4076 -31 +rect 3123 -229 4076 -124 +rect 3123 -345 3160 -229 +rect 3388 -232 4076 -229 +rect 3393 -342 3785 -232 +rect 3388 -345 3788 -342 +rect 3123 -348 3788 -345 +rect 4016 -348 4076 -232 +rect 3123 -382 4076 -348 +<< viali >> +rect 2340 3249 2536 3437 +rect 3008 3257 3012 3441 +rect 3012 3257 3212 3441 +rect 2324 2866 2328 3050 +rect 2328 2866 2528 3050 +rect 3048 2850 3248 3034 +rect 3248 2850 3252 3034 +rect 7000 1215 7471 1217 +rect 7000 1119 7471 1215 +rect 7947 1119 7951 1212 +rect 7951 1119 8423 1212 +rect 8929 1119 9400 1212 +rect 9400 1119 9405 1212 +rect 7824 735 8176 775 +rect 8643 765 8770 805 +rect 1457 -338 1685 -225 +rect 1685 -338 1686 -225 +rect 1457 -342 1686 -338 +rect 2089 -341 2307 -225 +rect 2089 -342 2307 -341 +rect 3164 -342 3388 -232 +rect 3388 -342 3393 -232 +rect 3785 -342 3788 -232 +rect 3788 -342 4014 -232 +<< metal1 >> +rect 2237 3441 3311 3485 +rect 2237 3437 3008 3441 +rect 2237 3249 2340 3437 +rect 2536 3257 3008 3437 +rect 3212 3257 3311 3441 +rect 2536 3249 3311 3257 +rect 2237 3050 3311 3249 +rect 2237 2866 2324 3050 +rect 2528 3034 3311 3050 +rect 2528 2866 3048 3034 +rect 2237 2850 3048 2866 +rect 3252 2850 3311 3034 +rect 2237 2810 3311 2850 +rect 6908 1239 9498 1450 +rect 4356 1217 9498 1239 +rect 4356 1119 7000 1217 +rect 7471 1212 9498 1217 +rect 7471 1119 7947 1212 +rect 8423 1119 8929 1212 +rect 9405 1119 9498 1212 +rect 4356 1097 9498 1119 +rect 4356 1057 7009 1097 +rect 1340 5 2450 12 +rect 1331 -222 4154 5 +rect 4364 -222 4477 1057 +rect 6802 149 6850 1057 +rect 8618 805 8795 828 +rect 7782 775 8241 795 +rect 7782 735 7824 775 +rect 8176 735 8241 775 +rect 8618 765 8643 805 +rect 8770 765 8795 805 +rect 8618 735 8795 765 +rect 7782 710 8241 735 +rect 6800 146 7548 149 +rect 6800 144 7553 146 +rect 6800 116 7685 144 +rect 6800 62 7620 116 +rect 7667 62 7685 116 +rect 6800 43 7685 62 +rect 6802 19 6850 43 +rect 7516 42 7685 43 +rect 1331 -225 4477 -222 +rect 1331 -342 1457 -225 +rect 1686 -342 2089 -225 +rect 2307 -232 4477 -225 +rect 2307 -342 3164 -232 +rect 3393 -342 3785 -232 +rect 4014 -342 4477 -232 +rect 1331 -366 4477 -342 +rect 1340 -372 2450 -366 +rect 3044 -377 4477 -366 +rect 3044 -379 4154 -377 +<< via1 >> +rect 7620 62 7667 116 +<< metal2 >> +rect 8765 678 8790 685 +rect 7788 675 8242 678 +rect 8480 675 8790 678 +rect 7693 668 8790 675 +rect 7693 667 8788 668 +rect 7693 146 8786 667 +rect 7593 116 8786 146 +rect 7593 62 7620 116 +rect 7667 62 8786 116 +rect 7593 42 8786 62 +rect 7693 -413 8786 42 +<< metal3 >> +rect 8620 678 8788 823 +rect 8480 675 8790 678 +rect 7693 322 8790 675 +rect 7693 -413 8786 322 +<< mimcap >> +rect 7741 532 8738 632 +rect 7741 170 7831 532 +rect 8185 170 8738 532 +rect 7741 -365 8738 170 +<< mimcapcontact >> +rect 7831 170 8185 532 +<< metal4 >> +rect 7787 678 8238 793 +rect 7787 663 8242 678 +rect 7789 532 8242 663 +rect 7789 170 7831 532 +rect 8185 170 8242 532 +rect 7789 107 8242 170 +<< labels >> +rlabel locali 2683 61 2702 125 1 vg +rlabel metal1 1715 -359 1771 -221 1 gnd +rlabel locali 3250 439 3300 571 1 vo +rlabel locali -385 1407 -210 1463 1 vinp +rlabel locali 5837 1423 6012 1479 1 vinm +rlabel metal1 2355 3152 2532 3216 1 vdd +rlabel locali 5164 2878 5280 2917 1 vbias +rlabel locali 9876 1436 9970 1481 1 vout +rlabel locali 6713 736 6783 766 1 top +rlabel metal4 7931 716 8004 729 1 top +rlabel metal3 8671 744 8728 759 1 vout +rlabel metal2 7615 126 7660 144 1 gnd +<< end >>
diff --git a/OPAMP_Layout_Files/opamp2.spice b/OPAMP_Layout_Files/opamp2.spice new file mode 100644 index 0000000..db267bc --- /dev/null +++ b/OPAMP_Layout_Files/opamp2.spice
@@ -0,0 +1,24 @@ +* SPICE3 file created from opamp2.ext - technology: sky130A + +.option scale=10000u + +X0 a_n24_1551# vinm vo w_n738_599# sky130_fd_pr__pfet_01v8 w=2512 l=52 +X1 a_n24_1551# vinp vg w_n738_599# sky130_fd_pr__pfet_01v8 w=2512 l=52 +X2 top vout sky130_fd_pr__cap_mim_m3_1 l=997 w=997 +X3 vdd vbias vout vdd sky130_fd_pr__pfet_01v8 w=1016 l=50 +X4 vg vg gnd gnd sky130_fd_pr__nfet_01v8 w=999 l=56 +X5 vout vo gnd gnd sky130_fd_pr__nfet_01v8 w=2520 l=53 +X6 vo top gnd sky130_fd_pr__res_generic_nd w=20 l=51 +X7 vdd vbias a_n24_1551# vdd sky130_fd_pr__pfet_01v8 w=1004 l=48 +X8 vo vg gnd gnd sky130_fd_pr__nfet_01v8 w=999 l=56 +C0 top vout 3.49fF +C1 top gnd 6.14fF +C2 vout gnd 21.51fF +C3 vo gnd 11.59fF +C4 vg gnd 5.66fF +C5 vinm gnd 2.16fF +C6 vinp gnd 2.11fF +C7 a_n24_1551# gnd 5.06fF +C8 vbias gnd 10.03fF +C9 w_n738_599# gnd 91.23fF +C10 vdd gnd 207.16fF
diff --git a/OPAMP_Layout_Files/opamp2_ac.spice b/OPAMP_Layout_Files/opamp2_ac.spice new file mode 100644 index 0000000..85f1896 --- /dev/null +++ b/OPAMP_Layout_Files/opamp2_ac.spice
@@ -0,0 +1,61 @@ +* SPICE3 file created from opamp2.ext - technology: sky130A + +.lib "sky130_fd_pr/models/sky130.lib.spice" tt + +X0 a_n24_1551# vinm vo w_n738_599# sky130_fd_pr__pfet_01v8 w=25.12 l=.52 +X1 a_n24_1551# vinp vg w_n738_599# sky130_fd_pr__pfet_01v8 w=25.12 l=.52 +X2 top vout sky130_fd_pr__cap_mim_m3_1 l=9.97 w=9.97 +X3 vdd vbias vout vdd sky130_fd_pr__pfet_01v8 w=10.16 l=.50 +X4 vg vg gnd gnd sky130_fd_pr__nfet_01v8 w=9.99 l=.56 +X5 vout vo gnd gnd sky130_fd_pr__nfet_01v8 w=25.20 l=.53 +X6 vo top gnd sky130_fd_pr__res_generic_nd w=2.0 l=.51 +X7 vdd vbias a_n24_1551# vdd sky130_fd_pr__pfet_01v8 w=10.04 l=.48 +X8 vo vg gnd gnd sky130_fd_pr__nfet_01v8 w=9.99 l=.56 +C0 top vout 3.49fF +C1 top gnd 6.14fF +C2 vout gnd 21.51fF +C3 vo gnd 11.59fF +C4 vg gnd 5.66fF +C5 vinm gnd 2.16fF +C6 vinp gnd 2.11fF +C7 a_n24_1551# gnd 5.06fF +C8 vbias gnd 10.03fF +C9 w_n738_599# gnd 91.23fF +C10 vdd gnd 207.16fF + +******* DC supply info****** +VDD vdd GND 5 +VBIAS vbias 0 3.9 + +*******Transient analysis AC Source******** +*VINP vinp 0 SIN(3.9 1m 10k 0 0 0) +*VINM vinm 0 SIN(3.9 1m 10k 0 0 180) + +*******AC analysis AC Source****** +VINP vinp 0 dc 3.9 ac 1 +VINM vinm 0 dc 3.9 ac -1 + +*******Tran command******* +*.tran 0.1us 1000us +********Transient Plot ****** +.control +run +*plot V(vinp) V(vinm) +*plot V(vo) +*plot V(vdd) V(vbias) + +******AC Command***** +ac dec 100 1 1000meg +*Magnitude dB plot for v(vout) on log scale +plot vdb(vout) xlog + +*Phase degrees plot for v(vout) on log scale +let outd = 57.29*vp(vout) +settype phase outd +plot outd xlimit 1 1000meg ylabel 'phase' +let pm = outd + 180 +settype phase pm +plot pm xlimit 1 1000meg ylabel 'Phase Margin' + +.endc +.end
diff --git a/OPAMP_Layout_Files/opamp2_tran.spice b/OPAMP_Layout_Files/opamp2_tran.spice new file mode 100644 index 0000000..7807a93 --- /dev/null +++ b/OPAMP_Layout_Files/opamp2_tran.spice
@@ -0,0 +1,62 @@ +* SPICE3 file created from opamp2.ext - technology: sky130A + +.lib "sky130_fd_pr/models/sky130.lib.spice" tt + +X0 a_n24_1551# vinm vo w_n738_599# sky130_fd_pr__pfet_01v8 w=25.12 l=.52 +X1 a_n24_1551# vinp vg w_n738_599# sky130_fd_pr__pfet_01v8 w=25.12 l=.52 +X2 top vout sky130_fd_pr__cap_mim_m3_1 l=9.97 w=9.97 +X3 vdd vbias vout vdd sky130_fd_pr__pfet_01v8 w=10.16 l=.50 +X4 vg vg gnd gnd sky130_fd_pr__nfet_01v8 w=9.99 l=.56 +X5 vout vo gnd gnd sky130_fd_pr__nfet_01v8 w=25.20 l=.53 +X6 vo top gnd sky130_fd_pr__res_generic_nd w=2.0 l=.51 +X7 vdd vbias a_n24_1551# vdd sky130_fd_pr__pfet_01v8 w=10.04 l=.48 +X8 vo vg gnd gnd sky130_fd_pr__nfet_01v8 w=9.99 l=.56 +C0 top vout 3.49fF +C1 top gnd 6.14fF +C2 vout gnd 21.51fF +C3 vo gnd 11.59fF +C4 vg gnd 5.66fF +C5 vinm gnd 2.16fF +C6 vinp gnd 2.11fF +C7 a_n24_1551# gnd 5.06fF +C8 vbias gnd 10.03fF +C9 w_n738_599# gnd 91.23fF +C10 vdd gnd 207.16fF + +******* DC supply info****** +VDD vdd GND 5 +VBIAS vbias 0 3.9 + +*******Transient analysis AC Source******** +VINP vinp 0 SIN(3.9 1m 10k 0 0 0) +VINM vinm 0 SIN(3.9 1m 10k 0 0 180) + +*******AC analysis AC Source****** +*VINP vinp 0 dc 3.9 ac 1 +*VINM vinm 0 dc 3.9 ac -1 + +*******Tran command******* +.tran 0.1us 1000us +********Transient Plot ****** +.control +run +plot V(vinp) V(vinm) +plot V(vout) +plot V(vo) +plot V(vdd) V(vbias) + +******AC Command***** +*ac dec 100 1 1000meg +*Magnitude dB plot for v(vout) on log scale +*plot vdb(vout) xlog + +*Phase degrees plot for v(vout) on log scale +*let outd = 57.29*vp(vout) +*settype phase outd +*plot outd xlimit 1 1000meg ylabel 'phase' +*let pm = outd + 180 +*settype phase pm +*plot pm xlimit 1 1000meg ylabel 'Phase Margin' + +.endc +.end
diff --git a/OPAMP_Layout_Files/res.ext b/OPAMP_Layout_Files/res.ext new file mode 100644 index 0000000..6d55d19 --- /dev/null +++ b/OPAMP_Layout_Files/res.ext
@@ -0,0 +1,13 @@ +timestamp 1628868150 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 1e+06 +resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__res_generic_nd l=l w=w +node "b" 132 88 -80 -60 ndc 0 0 0 0 0 0 0 0 400 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 0 0 0 0 0 0 0 0 0 0 0 0 +node "a" 132 88 -80 10 ndc 0 0 0 0 0 0 0 0 400 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 0 0 0 0 0 0 0 0 0 0 0 0 +node "a_n90_n70#" 1689 0 -90 -70 rnd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8070 722 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "$SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "b" "a" 44 +device rsubckt sky130_fd_pr__res_generic_nd -90 -70 -89 -69 l=50 w=20 "$SUB" "a_n90_n70#" 0 0 "b" 80 0 "a" 80 0
diff --git a/OPAMP_Layout_Files/res.mag b/OPAMP_Layout_Files/res.mag new file mode 100644 index 0000000..74afb22 --- /dev/null +++ b/OPAMP_Layout_Files/res.mag
@@ -0,0 +1,29 @@ +magic +tech sky130A +timestamp 1628868150 +<< ndiffc >> +rect -80 10 -60 30 +rect -80 -60 -60 -40 +<< ndiffres >> +rect -90 30 10 40 +rect -90 10 -80 30 +rect -60 10 10 30 +rect -90 0 10 10 +rect -19 -30 10 0 +rect -90 -40 10 -30 +rect -90 -60 -80 -40 +rect -60 -60 10 -40 +rect -90 -70 10 -60 +<< locali >> +rect -90 30 -50 40 +rect -90 10 -80 30 +rect -60 10 -50 30 +rect -90 0 -50 10 +rect -90 -40 -50 -30 +rect -90 -60 -80 -40 +rect -60 -60 -50 -40 +rect -90 -70 -50 -60 +<< labels >> +rlabel locali -79 4 -68 9 1 a +rlabel locali -78 -67 -67 -62 1 b +<< end >>
diff --git a/OPAMP_Layout_Files/res.spice b/OPAMP_Layout_Files/res.spice new file mode 100644 index 0000000..e9c93cf --- /dev/null +++ b/OPAMP_Layout_Files/res.spice
@@ -0,0 +1,19 @@ +* SPICE3 file created from res.ext - technology: sky130A + +.lib "sky130_fd_pr/models/sky130.lib.spice" tt + +X0 b a SUB sky130_fd_pr__res_generic_nd w=20 l=50 + +Va a 0 dc 3.3 + +Vb b 0 dc 0 + +.tran 0.1us 20us +.control +run + +plot V(a)/(-Va#branch) + +.endc + +.end
diff --git a/OPAMP_Layout_Files/sky130A.tech b/OPAMP_Layout_Files/sky130A.tech new file mode 100644 index 0000000..9248cda --- /dev/null +++ b/OPAMP_Layout_Files/sky130A.tech
@@ -0,0 +1,6327 @@ +#------------------------------------------------------------------------ +# Copyright (c) 2020 R. Timothy Edwards +# Revisions: See below +# +# This file is an Open Source foundry process describing +# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication +# process. The file may be distributed under the terms +# of the Apache 2.0 license agreement. +# +#------------------------------------------------------------------------ +# This file is designed to be used with magic versions +# 8.3.24 or newer. +#------------------------------------------------------------------------ +tech + format 35 + sky130A +end + +version + version 1.0.85-0-g32cdb20 + description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC" +end + +#------------------------------------------------------------------------ +# Status 7/10/20: Rev 1 (alpha): +# First public release +# Status 8/14/20: Rev 2 (alpha): +# Started updating with new device/model naming convention +#------------------------------------------------------------------------ + +#------------------------------------------------------------------------ +# Supported device types +#------------------------------------------------------------------------ +# device name magic ID layer description +#------------------------------------------------------------------------ +# sky130_fd_pr__nfet_01v8 nfet standard nFET +# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell** +# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell +# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell +# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET +# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET +# sky130_fd_pr__pfet_01v8 pfet standard pFET +# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell** +# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell +# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET +# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET +# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET +# sky130_fd_pr__nfet_03v3_nvt --- native nFET +# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET +# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET +# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET +# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode +# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode +# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff +# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode +# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode +# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode +# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode +# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode +# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell +# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN +# sky130_fd_pr__pnp_05v0 nbase PNP +# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate +# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate +# sky130_fd_pr__res_generic_nd rdn n+ diff resistor +# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor +# sky130_fd_pr__res_generic_pd rdp p+ diff resistor +# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor +# sky130_fd_pr__res_generic_l1 rli local interconnect resistor +# sky130_fd_pr__res_generic_po npres n+ poly resistor +# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq) +# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq) +# sky130_fd_pr__cap_var_lvt varactor low Vt varactor +# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor +# sky130_fd_pr__cap_var mvvaractor thickox varactor +# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell) +# +# (*) Note that ppres may extract into some generic type called +# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are +# allowed, and these are created from fixed layouts like the types below. +# +# (**) nFET and pFET in standard cells are the same as devices +# outside of the standard cell except for the DRC rule for +# FET to diffusion contact spacing (which is 0.05um, not 0.055um) +# +#------------------------------------------------------------- +# The following devices are not extracted but are represented +# only by script-generated subcells in the PDK. +#------------------------------------------------------------- +# sky130_fd_pr__esd_nfet_01v8 ESD nFET +# sky130_fd_pr__esd_nfet_g5v0d10v5 ESD thickox nFET +# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET +# sky130_fd_pr__esd_pfet_g5v0d10v5 ESD thickox pFET +# sky130_fd_pr__special_nfet_pass_flash flash nFET device +# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode +# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode +# sky130_fd_pr__cap_vpp_* Vpp cap +# sky130_fd_pr__ind_* inductor +# sky130_fd_pr__fuse_m4 metal fuse device +#-------------------------------------------------------------- + +#----------------------------------------------------- +# Tile planes +#----------------------------------------------------- + +planes + dwell,dw + well,w + active,a + locali,li1,li + metal1,m1 + metal2,m2 + metal3,m3 + cap1,c1 + metal4,m4 + cap2,c2 + metal5,m5 + metali,mi + block,b + comment,c +end + +#----------------------------------------------------- +# Tile types +#----------------------------------------------------- + +types +# Deep nwell + dwell dnwell,dnw + +# Wells + well nwell,nw + well pwell,pw + well rpw,rpwell + -well obswell + well pbase,npn + well nbase,pnp + +# Transistors + active nmos,ntransistor,nfet + -active scnmos,scntransistor,scnfet + -active npd,npdfet,sramnfet + -active npass,npassfet,srampassfet + active pmos,ptransistor,pfet + -active scpmos,scptransistor,scpfet + -active scpmoshvt,scpfethvt + -active ppu,ppufet,srampfet + active nnmos,nntransistor + active mvnmos,mvntransistor,mvnfet + active mvpmos,mvptransistor,mvpfet + active mvnnmos,mvnntransistor,mvnnfet,nnfet + active varactor,varact,var + active mvvaractor,mvvaract,mvvar + + active pmoslvt,pfetlvt + active pmosmvt,pfetmvt + active pmoshvt,pfethvt + active nmoslvt,nfetlvt + active varactorhvt,varacthvt,varhvt + -active nsonos,sonos + active sramnvar,corenvar,corenvaractor + active srampvar,corepvar,corepvaractor + +# Diffusions + active ndiff,ndiffusion,ndif + active pdiff,pdiffusion,pdif + active mvndiff,mvndiffusion,mvndif + active mvpdiff,mvpdiffusion,mvpdif + active ndiffc,ndcontact,ndc + active pdiffc,pdcontact,pdc + active mvndiffc,mvndcontact,mvndc + active mvpdiffc,mvpdcontact,mvpdc + active psubdiff,psubstratepdiff,ppdiff,ppd,psd + active nsubdiff,nsubstratendiff,nndiff,nnd,nsd + active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd + active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd + active psubdiffcont,psubstratepcontact,psc + active nsubdiffcont,nsubstratencontact,nsc + active mvpsubdiffcont,mvpsubstratepcontact,mvpsc + active mvnsubdiffcont,mvnsubstratencontact,mvnsc + -active obsactive + -active mvobsactive + +# Poly + active poly,p,polysilicon + active polycont,pc,pcontact,polycut,polyc + active xpolycontact,xpolyc,xpc + +# Resistors + active npolyres,npres,mrp1 + active ppolyres,ppres,xhrpoly + active xpolyres,xpres,xres,uhrpoly + active ndiffres,rnd,rdn,rndiff + active pdiffres,rpd,rdp,rpdiff + active mvndiffres,mvrnd,mvrdn,mvrndiff + active mvpdiffres,mvrpd,mvrdp,mvrpdiff + active rmp + +# Diodes +active pdiode,pdi + active ndiode,ndi + active nndiode,nndi + active pdiodec,pdic + active ndiodec,ndic + active nndiodec,nndic + active mvpdiode,mvpdi + active mvndiode,mvndi + active mvpdiodec,mvpdic + active mvndiodec,mvndic + active pdiodelvt,pdilvt + active pdiodehvt,pdihvt + active ndiodelvt,ndilvt + active pdiodelvtc,pdilvtc + active pdiodehvtc,pdihvtc + active ndiodelvtc,ndilvtc + +# Local Interconnect + locali locali,li1,li + -locali corelocali,coreli1,coreli + locali rlocali,rli1,rli + locali viali,vial,mcon,lic,licon,m1c,v0 + -locali obsli1,obsli + -locali obsli1c,obslic,obslicon + +# Metal 1 + metal1 metal1,m1,met1 + metal1 rmetal1,rm1,rmet1 + metal1 via1,m2contact,m2cut,m2c,via,v,v1 + -metal1 obsm1 + metal1 padl + -metal1 m1fill + +# Metal 2 + metal2 metal2,m2,met2 + metal2 rmetal2,rm2,rmet2 + metal2 via2,m3contact,m3cut,m3c,v2 + -metal2 obsm2 + -metal2 m2fill + +# Metal 3 + metal3 metal3,m3,met3 + metal3 rmetal3,rm3,rmet3 + -metal3 obsm3 + metal3 via3,v3 + -metal3 m3fill + + cap1 mimcap,mim,capm + cap1 mimcapcontact,mimcapc,mimcc,capmc + +# Metal 4 + metal4 metal4,m4,met4 + metal4 rmetal4,rm4,rmet4 + -metal4 obsm4 + metal4 via4,v4 + -metal4 m4fill + + cap2 mimcap2,mim2,capm2 + cap2 mimcap2contact,mimcap2c,mim2cc,capm2c + +# Metal 5 + metal5 metal5,m5,met5 + metal5 rm5,rmetal5,rmet5 + -metal5 obsm5 + -metal5 m5fill + + metal5 mrdlcontact,mrdlc + metali metalrdl,mrdl,metrdl + -metali obsmrdl + +# Miscellaneous + -block glass + -block fillblock + comment comment + -comment obscomment +# fixed resistor width identifiers + -comment res0p35 + -comment res0p69 + -comment res1p41 + -comment res2p85 + -comment res5p73 + +end + +#----------------------------------------------------- +# Magic contact types +#----------------------------------------------------- + +contact + pc poly locali + ndc ndiff locali + pdc pdiff locali + nsc nsd locali + psc psd locali + ndic ndiode locali + ndilvtc ndiodelvt locali + nndic nndiode locali + pdic pdiode locali + pdilvtc pdiodelvt locali + pdihvtc pdiodehvt locali + xpc xpc locali + + mvndc mvndiff locali + mvpdc mvpdiff locali + mvnsc mvnsd locali + mvpsc mvpsd locali + mvndic mvndiode locali + mvpdic mvpdiode locali + + lic locali metal1 + obslic obsli metal1 + + via1 metal1 metal2 + via2 metal2 metal3 + via3 metal3 metal4 + via4 metal4 metal5 + stackable + + # MiM cap contacts are not stackable! + mimcc mimcap metal4 + mim2cc mimcap2 metal5 + + padl m1 m2 m3 m4 m5 glass + + mrdlc metal5 mrdl +end + +#----------------------------------------------------- +# Layer aliases +#----------------------------------------------------- + +aliases + + allwellplane nwell + allnwell nwell,obswell,pnp + + allnfets nfet,npass,npd,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos + allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,pfethvt,pfetlvt,pfetmvt + allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar + allfetsstd nfet,mvnfet,mvnnfet,nfetlvt,pfet,mvpfet,pfethvt,pfetlvt,pfetmvt + allfetsspecial scnfet,scpfet,scpfethvt + allfetscore npass,npd,nsonos,ppu,corenvar,corepvar + allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar + + allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt + allnactive allnactivenonfet,allnfets + allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets + allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar + + allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt + allpactive allpactivenonfet,allpfets + allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets + allpactivetap *psd,*mvpsd,corepvar + + allactivenonfet allnactivenonfet,allpactivenonfet + allactive allactivenonfet,allfets + + allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres + + allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos + allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt + alldifflv allndifflv,allpdifflv + allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt + allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt + alldifflvnonfet allndifflvnonfet,allpdifflvnonfet + + allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet + allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet + alldiffmv allndiffmv,allpdiffmv + allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet + allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet + alldiffmvnontap allndiffmvnontap,allpdiffmvnontap + allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres + allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres + alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet + + alldiffnonfet alldifflvnonfet,alldiffmvnonfet + alldiff alldifflv,alldiffmv + + allpolyres mrp1,xhrpoly,uhrpoly,rmp + allpolynonfet *poly,allpolyres,xpc + allpolynonres *poly,allfets,xpc + + allpoly allpolynonfet,allfets + allpolynoncap *poly,xpc,allfets,allpolyres + + allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc + allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc + allndiffcontmv mvndc,mvnsc,mvndic + allpdiffcontmv mvpdc,mvpsc,mvpdic + allndiffcont allndiffcontlv,allndiffcontmv + allpdiffcont allpdiffcontlv,allpdiffcontmv + alldiffcontlv allndiffcontlv,allpdiffcontlv + alldiffcontmv allndiffcontmv,allpdiffcontmv + alldiffcont alldiffcontlv,alldiffcontmv + + allcont alldiffcont,pc + + allres allpolyres,allactiveres + + allli *locali,coreli,rli + allm1 *m1,rm1 + allm2 *m2,rm2 + allm3 *m3,rm3 + allm4 *m4,rm4 + allm5 *m5,rm5 + + allpad padl + + psub pwell + +end + +#----------------------------------------------------- +# Layer drawing styles +#----------------------------------------------------- + +styles + styletype mos + dnwell cwell + nwell nwell + pwell pwell + rpwell pwell ptransistor_stripes + ndiff ndiffusion + pdiff pdiffusion + nsd ndiff_in_nwell + psd pdiff_in_pwell + nfet ntransistor ntransistor_stripes + scnfet ntransistor ntransistor_stripes + npass ntransistor ntransistor_stripes + npd ntransistor ntransistor_stripes + pfet ptransistor ptransistor_stripes + scpfet ptransistor ptransistor_stripes + scpfethvt ptransistor ptransistor_stripes implant2 + ppu ptransistor ptransistor_stripes + var polysilicon ndiff_in_nwell + ndc ndiffusion metal1 contact_X'es + pdc pdiffusion metal1 contact_X'es + nsc ndiff_in_nwell metal1 contact_X'es + psc pdiff_in_pwell metal1 contact_X'es + corenvar polysilicon ndiff_in_nwell + corepvar polysilicon pdiff_in_pwell + + pnp nwell ntransistor_stripes + npn pwell ptransistor_stripes + + pfetlvt ptransistor ptransistor_stripes implant1 + pfetmvt ptransistor ptransistor_stripes implant3 + pfethvt ptransistor ptransistor_stripes implant2 + nfetlvt ntransistor ntransistor_stripes implant1 + nsonos ntransistor implant3 + varhvt polysilicon ndiff_in_nwell implant2 + + mvndiff ndiffusion hvndiff_mask + mvpdiff pdiffusion hvpdiff_mask + mvnsd ndiff_in_nwell hvndiff_mask + mvpsd pdiff_in_pwell hvpdiff_mask + mvnfet ntransistor ntransistor_stripes hvndiff_mask + mvnnfet ntransistor ndiff_in_nwell hvndiff_mask + mvpfet ptransistor ptransistor_stripes + mvvar polysilicon ndiff_in_nwell hvndiff_mask + mvndc ndiffusion metal1 contact_X'es hvndiff_mask + mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask + mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask + mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask + + poly polysilicon + pc polysilicon metal1 contact_X'es + npolyres polysilicon silicide_block nselect2 + ppolyres polysilicon silicide_block pselect2 + xpc polysilicon pselect2 metal1 contact_X'es + rmp polysilicon poly_resist_stripes + + res0p35 implant1 + res0p69 implant1 + res1p41 implant1 + res2p85 implant1 + res5p73 implant1 + + pdiode pdiffusion pselect2 + ndiode ndiffusion nselect2 + pdiodec pdiffusion pselect2 metal1 contact_X'es + ndiodec ndiffusion nselect2 metal1 contact_X'es + + nndiode ndiffusion nselect2 implant3 + ndiodelvt ndiffusion nselect2 implant1 + pdiodelvt pdiffusion pselect2 implant1 + pdiodehvt pdiffusion pselect2 implant2 + pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es + pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es + ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es + + mvpdiode pdiffusion pselect2 hvpdiff_mask + mvndiode ndiffusion nselect2 hvndiff_mask + mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask + mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask + nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask + + locali metal1 + coreli metal1 + rli metal1 poly_resist_stripes + lic metal1 metal2 via1arrow + obsli metal1 + obslic metal1 metal2 via1arrow + + metal1 metal2 + m1fill metal2 + rm1 metal2 poly_resist_stripes + obsm1 metal2 + m2c metal2 metal3 via2arrow + metal2 metal3 + m2fill metal3 + rm2 metal3 poly_resist_stripes + obsm2 metal3 + m3c metal3 metal4 via3alt + metal3 metal4 + m3fill metal4 + rm3 metal4 poly_resist_stripes + obsm3 metal4 + mimcap metal3 mems + mimcc metal3 contact_X'es mems + mimcap2 metal4 mems + mim2cc metal4 contact_X'es mems + via3 metal4 metal5 via4 + metal4 metal5 + m4fill metal5 + rm4 metal5 poly_resist_stripes + obsm4 metal5 + via4 metal5 metal6 via5 + metal5 metal6 + m5fill metal6 + rm5 metal6 poly_resist_stripes + obsm5 metal6 + mrdlc metal6 metal7 via6 + metalrdl metal7 + obsmrdl metal7 + + glass overglass + mrp1 poly_resist poly_resist_stripes + xhrpoly poly_resist silicide_block + uhrpoly poly_resist + ndiffres ndiffusion ndop_stripes + pdiffres pdiffusion pdop_stripes + mvndiffres ndiffusion hvndiff_mask ndop_stripes + mvpdiffres pdiffusion hvpdiff_mask pdop_stripes + comment comment + error_p error_waffle + error_s error_waffle + error_ps error_waffle + fillblock cwell + + obswell cwell + obsactive implant4 + + padl metal6 via6 overglass + + magnet substrate_field_implant + rotate via3alt + fence via5 +end + +#----------------------------------------------------- +# Special paint/erase rules +#----------------------------------------------------- + +compose + compose nfet poly ndiff + compose pfet poly pdiff + compose var poly nsd + + compose mvnfet poly mvndiff + compose mvpfet poly mvpdiff + compose mvvar poly mvnsd + + paint obslic locali via1 + paint obslic obsm1 obsli,obsm1 + + paint ndc nwell pdc + paint nfet nwell pfet + paint scnfet nwell scpfet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + paint npd nwell ppu + + paint pdc pwell ndc + paint pfet pwell nfet + paint scpfet pwell scnfet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + paint ppu pwell npd + + paint pdc coreli pdc + paint ndc coreli ndc + paint pc coreli pc + paint nsc coreli nsc + paint psc coreli psc + paint viali coreli viali + + paint coreli pdc pdc + paint coreli ndc ndc + paint coreli pc pc + paint coreli nsc nsc + paint coreli psc psc + paint coreli viali viali + + paint m4 obsm4 m4 + paint m5 obsm5 m5 +end + +#----------------------------------------------------- +# Electrical connectivity +#----------------------------------------------------- + +connect + *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp + pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn + *li,coreli *li,coreli + *m1,m1fill,obslic *m1,m1fill,obslic + *m2,m2fill *m2,m2fill + *m3,m3fill *m3,m3fill + *m4,m4fill *m4,m4fill + *m5,m5fill *m5,m5fill + *mimcap *mimcap + *mimcap2 *mimcap2 + allnactivenonfet allnactivenonfet + allpactivenonfet allpactivenonfet + *poly,xpc,allfets *poly,xpc,allfets + # RDL connects to m5 (i.e., padl) through glass cut + *mrdl *mrdl + glass metrdl +end + +#----------------------------------------------------- +# CIF/GDS output layer definitions +#----------------------------------------------------- +# NOTE: All values in this section MUST be multiples of 25 +# or else magic will scale below the allowed layout grid size + +cifoutput + +#---------------------------------------------------------------- +style gdsii +# NOTE: This section is used for actual GDS output +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + +#---------------------------------------------------------------- +# Create a temp layer from the cell bounding box for use in +# generating ID layers. Note that "boundary", unlike "bbox", +# requires the FIXED_BBOX property (abutment box) in the cell. +#---------------------------------------------------------------- + templayer CELLBOUND + boundary + +#---------------------------------------------------------------- +# BOUND +#---------------------------------------------------------------- + layer BOUND CELLBOUND + calma 235 4 + +# Create a boundary outside of an abutment box, so that layers +# can be made to stretch to the abutment box edges. First strink +# so that any box that would be so small as to interact with +# itself will be removed. + + templayer CELLRING CELLBOUND + shrink 345 + grow 545 + and-not CELLBOUND + +#---------------------------------------------------------------- +# DNWELL +#---------------------------------------------------------------- + + layer DNWELL dnwell,pnp + calma 64 18 + + layer PWRES rpw + and dnwell + calma 64 13 + +#---------------------------------------------------------------- +# NWELL +#---------------------------------------------------------------- + + layer NWELL allnwell + bloat-all rpw dnwell + and-not rpw,pwell + calma 64 20 + + layer WELLTXT + labels allnwell noport + calma 64 16 + + layer WELLPIN + labels allnwell port + calma 64 5 + +#---------------------------------------------------------------- +# SUB (text/port only) +#---------------------------------------------------------------- + + layer SUBTXT + labels pwell noport + calma 122 16 + + layer SUBPIN + labels pwell port + calma 64 59 + +#---------------------------------------------------------------- +# DIFF +#---------------------------------------------------------------- + + layer DIFF allnactivenontap,allpactivenontap,allactiveres + labels allnactivenontap,allpactivenontap + calma 65 20 + +#---------------------------------------------------------------- +# TAP +#---------------------------------------------------------------- + + layer TAP allnactivetap,allpactivetap + labels allnactivetap,allpactivetap + calma 65 44 + +#---------------------------------------------------------------- +# PPLUS, NPLUS (PSDM, NSDM) +#---------------------------------------------------------------- + + templayer basePPLUS pdiffres,mvpdiffres + grow 15 + or xhrpoly,uhrpoly,xpc + grow 110 + bloat-or allpactivetap * 125 allnactivenontap 0 + bloat-or allpactivenontap * 125 allnactivetap 0 + + templayer baseNPLUS ndiffres,mvndiffres + grow 125 + bloat-or allnactivetap * 125 allpactivenontap 0 + bloat-or allnactivenontap * 125 allpactivetap 0 + + templayer extendPPLUS basePPLUS,CELLRING + bridge 380 380 + and-not baseNPLUS + and-not CELLRING + + layer PPLUS basePPLUS,extendPPLUS + grow 185 + shrink 185 + close 265000 + calma 94 20 + + templayer extendNPLUS baseNPLUS,CELLRING + bridge 380 380 + and-not basePPLUS + and-not CELLRING + + layer NPLUS baseNPLUS,extendNPLUS + grow 185 + shrink 185 + close 265000 + calma 93 44 + +#---------------------------------------------------------------- +# LVTN +#---------------------------------------------------------------- + + layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + calma 125 44 + +#---------------------------------------------------------------- +# HVTR +#---------------------------------------------------------------- + + layer HVTR pfetmvt + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + calma 18 20 + +#---------------------------------------------------------------- +# HVTP +#---------------------------------------------------------------- + + layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + calma 78 44 + +#---------------------------------------------------------------- +# SONOS +#---------------------------------------------------------------- + + layer SONOS nsonos + grow 100 + grow-min 410 + bridge 500 410 + grow 250 + shrink 250 + calma 80 20 + +#---------------------------------------------------------------- +# SONOS requires COREID around area (areaid.ce). Also, the +# coreli layer indicates a cell needing COREID. Also, devices +# npd, npass, and ppu indicate a COREID cell. +#---------------------------------------------------------------- + + layer COREID + bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND + calma 81 2 + +#---------------------------------------------------------------- +# STDCELL applies to all cells containing scnfet or scpfet. +#---------------------------------------------------------------- + + layer STDCELL scnfet + bloat-all scpfet,scpfethvt,scnfet CELLBOUND + calma 81 4 + +#---------------------------------------------------------------- +# NPNID and PNPID apply to bipolar transistors +#---------------------------------------------------------------- + + layer NPNID + bloat-all npn dnwell + calma 82 20 + + templayer pnparea pnp + grow 400 + + layer PNPID + bloat-all pnparea *psd + or pnparea + calma 82 44 + +#---------------------------------------------------------------- +# RPM +#---------------------------------------------------------------- + + layer RPM + bloat-all xhrpoly xpc + grow 200 + grow-min 1270 + grow 420 + shrink 420 + calma 86 20 + +#---------------------------------------------------------------- +# URPM (2kOhms/sq. poly implant) +#---------------------------------------------------------------- + + layer URPM + bloat-all uhrpoly xpc + grow 200 + grow-min 1270 + grow 420 + shrink 420 + calma 79 20 + +#---------------------------------------------------------------- +# LDNTM (Tip implant for SONOS FETs) +#---------------------------------------------------------------- + + layer LDNTM + bloat-all nsonos *ndiff + grow 185 + grow 345 + shrink 345 + calma 11 44 + +#---------------------------------------------------------------- +# HVNTM (Tip implant for MV ndiff devices) +#---------------------------------------------------------------- + + templayer hvntm_block *mvpsd + grow 185 + + layer HVNTM + bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff + bloat-all mvvaractor *mvnsd + and-not hvntm_block + grow 185 + grow 345 + shrink 345 + and-not hvntm_block + calma 125 20 + +#---------------------------------------------------------------- +# POLY +#---------------------------------------------------------------- + + layer POLY allpoly + calma 66 20 + + layer POLYTXT + labels allpoly noport + calma 66 16 + + layer POLYPIN + labels allpoly port + calma 66 5 + +#---------------------------------------------------------------- +# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26) +#---------------------------------------------------------------- + + templayer thkox_area alldiffmv,mvvar + grow 185 + bloat-all alldiffmv nwell + grow 345 + shrink 345 + + templayer large_ptap_mv thkox_area + shrink 420 + grow 420 + + templayer small_ptap_mv thkox_area + and-not large_ptap_mv + # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um) + grow-min 840 + + templayer baseTHKOX thkox_area,small_ptap_mv + bridge 700 600 + grow 345 + shrink 345 + + templayer extendTHKOX baseTHKOX,CELLRING + grow 345 + shrink 345 + and-not CELLRING + + layer THKOX baseTHKOX,extendTHKOX + calma 75 20 + +#---------------------------------------------------------------- +# CONT (LICON) +#---------------------------------------------------------------- + + layer CONT allcont + squares-grid 0 170 170 + calma 66 44 + + # Contact for pres is different than other LICON contacts + # See rules LICON 1b, 1c (width/length) and 2b (spacing) + templayer xpc_horiz xpc + shrink 1007 + grow 1007 + + layer CONT xpc + and-not xpc_horiz + # Force long edge vertical for contacts narrower than 2um + # Minimum space is 350 but 520 satisfies no. of contacts rule + slots 80 190 520 80 2000 350 + calma 66 44 + + layer CONT xpc + and xpc_horiz + # Force long edge vertical for contacts wider than 2um + # Minimum space is 350 but 520 satisfies no. of contacts rule + slots 80 2000 350 80 190 520 + calma 66 44 + +#---------------------------------------------------------------- +# NPC (Nitride poly cut) +# surrounds CONT (LICON) on poly only (i.e., pc) +#---------------------------------------------------------------- + + layer NPC pc + squares-grid 0 170 170 + grow 100 + bridge 270 270 + grow 130 + shrink 130 + calma 95 20 + + # NPC is also generated on xhrpoly and uhrpoly resistors + + layer NPC xpc,xhrpoly,uhrpoly + # xpc surrounds precision_resistor by 0.095um + grow 95 + grow 130 + shrink 130 + calma 95 20 + +#---------------------------------------------------------------- +# Device markers +#---------------------------------------------------------------- + + layer DIFFRES rdn,mvrdn,rdp,mvrdp + calma 65 13 + + layer POLYRES mrp1 + calma 66 13 + + # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers + layer POLYSHORT rmp + calma 66 15 + + # POLYRES extends to edge of contact cut + layer POLYRES xhrpoly,uhrpoly + grow 60 + and xpc + or xhrpoly,uhrpoly + calma 66 13 + + layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt + # To be done: Expand to include anode, cathode, and guard ring + calma 81 23 + +#---------------------------------------------------------------- +# LI +#---------------------------------------------------------------- + layer LI allli + calma 67 20 + + layer LITXT + labels *locali,coreli noport + calma 67 16 + + layer LIPIN + labels *locali,coreli port + calma 67 5 + + layer LIRES rli + labels rli + calma 67 13 + +#---------------------------------------------------------------- +# MCON +#---------------------------------------------------------------- + layer MCON lic + squares-grid 0 170 190 + calma 67 44 + +#---------------------------------------------------------------- +# MET1 +#---------------------------------------------------------------- + layer MET1 allm1,m1fill + calma 68 20 + + layer MET1TXT + labels allm1 noport + calma 68 16 + + layer MET1PIN + labels allm1 port + calma 68 5 + + layer MET1RES rm1 + labels rm1 + calma 68 13 + +#---------------------------------------------------------------- +# VIA1 +#---------------------------------------------------------------- + layer VIA1 via1 + squares-grid 55 150 170 + calma 68 44 + +#---------------------------------------------------------------- +# MET2 +#---------------------------------------------------------------- + layer MET2 allm2,m2fill + calma 69 20 + + layer MET2TXT + labels allm2 noport + calma 69 16 + + layer MET2PIN + labels allm2 port + calma 69 5 + + layer MET2RES rm2 + labels rm2 + calma 69 13 + +#---------------------------------------------------------------- +# VIA2 +#---------------------------------------------------------------- + layer VIA2 via2 + squares-grid 40 200 200 + calma 69 44 + +#---------------------------------------------------------------- +# MET3 +#---------------------------------------------------------------- + layer MET3 allm3,m3fill + calma 70 20 + + layer MET3TXT + labels allm3 noport + calma 70 16 + + layer MET3PIN + labels allm3 port + calma 70 5 + + layer MET3RES rm3 + labels rm3 + calma 70 13 + +#---------------------------------------------------------------- +# VIA3 +#---------------------------------------------------------------- + layer VIA3 via3 + or mimcc + squares-grid 60 200 200 + calma 70 44 + +#---------------------------------------------------------------- +# MET4 +#---------------------------------------------------------------- + layer MET4 allm4,m4fill + calma 71 20 + + layer MET4TXT + labels allm4 noport + calma 71 16 + + layer MET4PIN + labels allm4 port + calma 71 5 + + layer MET4RES rm4 + labels rm4 + calma 71 13 + +#---------------------------------------------------------------- +# VIA4 +#---------------------------------------------------------------- + layer VIA4 via4 + or mim2cc + squares-grid 190 800 800 + calma 71 44 + +#---------------------------------------------------------------- +# MET5 +#---------------------------------------------------------------- + layer MET5 allm5,m5fill + calma 72 20 + + layer MET5TXT + labels allm5 noport + calma 72 16 + + layer MET5PIN + labels allm5 port + calma 72 5 + + layer MET5RES rm5 + labels rm5 + calma 72 13 + + +#---------------------------------------------------------------- +# RDL +#---------------------------------------------------------------- + layer RDL *metrdl + calma 74 20 + + layer RDLTXT + labels *metrdl noport + calma 74 16 + + layer RDLPIN + labels *metrdl port + calma 74 5 + + layer PI1 *metrdl + and padl,glass + # Test only---needs GDS layer number + + layer UBM *metrdl + shrink 50000 + grow 40000 + # Test only---needs GDS layer number + + layer PI2 *metrdl + shrink 50000 + grow 25000 + # Test only---needs GDS layer number + + +#---------------------------------------------------------------- +# GLASS +#---------------------------------------------------------------- + layer GLASS glass + calma 76 20 + +#---------------------------------------------------------------- +# CAPM +#---------------------------------------------------------------- + layer CAPM *mimcap + labels mimcap + calma 89 44 + + layer CAPM2 *mimcap2 + labels mimcap2 + calma 97 44 + +#---------------------------------------------------------------- +# Chip top level marker for DRC latchup rules to check 15um +# distance to taps (otherwise 6um is used) +#---------------------------------------------------------------- + + layer LOWTAPDENSITY + bbox top + # Clear 200um for pads + 50um for required high tap density + # in critical area. + shrink 250000 + calma 81 14 + +#---------------------------------------------------------------- +# FILLBLOCK +#---------------------------------------------------------------- + layer FILLOBSM1 fillblock + calma 62 24 + + layer FILLOBSM2 fillblock + calma 105 52 + + layer FILLOBSM3 fillblock + calma 107 24 + + layer FILLOBSM4 fillblock + calma 112 4 + + render DNWELL cwell -0.1 0.1 + render NWELL nwell 0.0 0.2062 + render DIFF ndiffusion 0.2062 0.12 + render TAP pdiffusion 0.2062 0.12 + render POLY polysilicon 0.3262 0.18 + render CONT via 0.5062 0.43 + render LI metal1 0.9361 0.10 + render MCON via 1.0361 0.34 + render MET1 metal2 1.3761 0.36 + render VIA1 via 1.7361 0.27 + render MET2 metal3 2.0061 0.36 + render VIA2 via 2.3661 0.42 + render MET3 metal4 2.7861 0.845 + render VIA3 via 3.6311 0.39 + render MET4 metal5 4.0211 0.845 + render VIA4 via 4.8661 0.505 + render MET5 metal6 5.3711 1.26 + render CAPM metal8 2.4661 0.2 + render CAPM2 metal9 3.7311 0.2 + render RDL metal7 11.8834 4.0 + +#---------------------------------------------------------------- +style drc +#---------------------------------------------------------------- +# NOTE: This style is used for DRC only, not for GDS output +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + + # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside + templayer dnwell_shrink dnwell + shrink 1030 + + templayer nwell_missing dnwell + grow 400 + and-not dnwell_shrink + and-not nwell + + templayer pwell_in_dnwell dnwell + and-not nwell + + # SONOS nFET devices must be in deep nwell + templayer dnwell_missing nsonos + and-not dnwell + + # SONOS nFET devices must be in cell with abutment box + templayer abutment_box + boundary + + templayer bbox_missing nsonos + and-not abutment_box + + # Make sure nwell covers varactor poly + templayer var_poly_no_nwell + bloat-all varactor,mvvaractor *poly + grow 150 + and-not nwell + + # Define MiM cap bottom plate for spacing rule + templayer mim_bottom + bloat-all *mimcap *metal3 + + # Define MiM2 cap bottom plate for spacing rule + templayer mim2_bottom + bloat-all *mimcap2 *metal4 + + # Note that metal fill is performed by the foundry and so is not + # an option for a cifoutput style. + + # Check latchup rule (15um minimum from tap LICON center to any + # non-tap diffusion. Note that to count as a tap, the diffusion + # must be contacted to LI + + templayer ptap_reach psc,mvpsc + and-not dnwell + # grow total is 15um. grow in 0.84um increments to ensure that + # no nwell ring is crossed + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 635 + and-not nwell,dnwell + + templayer ptap_missing *ndiff,*mvndiff + and-not dnwell + and-not ptap_reach + + templayer ntap_reach nsc,mvnsc + # grow total is 15um. grow in 1.27um increments to ensure that + # no nwell ring is crossed. There is no difference between + # ntaps in and out of deep nwell. + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 945 + and nwell,pnp + + templayer ntap_missing *pdiff,*mvpdiff + and-not pwell_in_dnwell + and-not ntap_reach + + templayer dptap_reach psc,mvpsc + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 635 + and-not nwell + and dnwell + + templayer dptap_missing *ndiff,*mvndiff + and dnwell + and-not dptap_reach + + templayer pdiff_crosses_dnwell dnwell + grow 20 + and-not dnwell + and allpdifflv,allpdiffmv + + # MV nwell must be 2um from any other nwell + templayer mvnwell + bloat-all alldiffmv nwell + grow-min 840 + bridge 700 600 + + # Simple spacing checks to lvnwell must use CIF-DRC rule + templayer allmvdiffnowell *mvndiff,*mvpsd + + templayer lvnwell nwell + and-not mvnwell + + templayer nwell_with_tap + bloat-all nsc,mvnsc nwell,pnp + + templayer nwell_missing_tap nwell,pnp + and-not nwell_with_tap + + templayer tap_with_licon + bloat-all psc,mvpsc psd,mvpsd + bloat-all nsc,mvnsc nsd,mvnsd + + templayer tap_missing_licon psd,nsd,mvpsd,mvnsd + and-not tap_with_licon + + # Make sure varactor nwell contains no P diffusion + templayer pdiff_in_varactor_well + bloat-all varactor,mvvaractor nwell + and allpactive + + # HVNTM spacing requires recreating HVNTM + templayer hvntm_block *mvpsd + grow 185 + + templayer hvntm_generate + bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff + bloat-all mvvaractor *mvnsd + and-not hvntm_block + grow 185 + grow 345 + shrink 345 + and-not hvntm_block + + templayer m1_small_hole allm1,obsm1,obslic + close 140000 + + templayer m1_hole_empty m1_small_hole + and-not allm1,obsm1,obslic + + templayer m2_small_hole allm2,obsm2 + close 140000 + + templayer m2_hole_empty m2_small_hole + and-not allm2,obsm2 + + templayer m1_huge allm1 + shrink 1500 + grow 1500 + + templayer m1_large_halo m1_huge + grow 280 + and-not m1_huge + and allm1 + + templayer m2_huge allm2 + shrink 1500 + grow 1500 + + templayer m2_large_halo m2_huge + grow 280 + and-not m2_huge + and allm2 + + templayer m3_huge allm3 + shrink 1500 + grow 1500 + + templayer m3_large_halo m3_huge + grow 400 + and-not m3_huge + and allm3 + + templayer m4_huge allm4 + shrink 1500 + grow 1500 + + templayer m4_large_halo m4_huge + grow 400 + and-not m4_huge + and allm4 + + +#---------------------------------------------------------------- +style wafflefill +#---------------------------------------------------------------- +# Style used by scripts for automatically generating fill layers +# NOTE: Be sure to generate output on flattened layout. +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + +#---------------------------------------------------------------- +# Generate and retain a layer representing the bounding box +#---------------------------------------------------------------- + templayer topbox + bbox top + +#---------------------------------------------------------------- +# Generate guard-band around nwells to keep FOM from crossing +# Spacing from LV nwell = Diff/Tap 9 = 0.34um +# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25) +# Enclosure by nwell = Diff/Tap 8 = 0.18um +#---------------------------------------------------------------- + + templayer mvnwell + bloat-all alldiffmv nwell + + templayer lvnwell nwell + and-not mvnwell + + templayer well_shrink mvnwell + shrink 250 + or lvnwell + shrink 180 + templayer well_guardband nwell + grow 340 + and-not well_shrink + +#--------------------------------------------------- +# Diffusion and poly keep-out areas +#--------------------------------------------------- + templayer obstruct_fom alldiff,allpoly,rpw + grow 500 + or well_guardband + + templayer obstruct_poly alldiff,allpoly,rpw + grow 1000 + +#--------------------------------------------------- +# FOM and POLY fill +#--------------------------------------------------- + templayer fomfill_pass1 topbox + slots 0 4080 1320 0 4080 1320 1360 0 + and-not obstruct_fom + and topbox + shrink 2035 + grow 2035 + +#--------------------------------------------------- + + templayer obstruct_poly_pass1 fomfill_pass1 + grow 300 + or obstruct_poly + templayer polyfill_pass1 topbox + slots 0 720 360 0 720 360 240 0 + and-not obstruct_poly_pass1 + and topbox + shrink 355 + grow 355 + +#--------------------------------------------------- + + templayer obstruct_fom_pass2 fomfill_pass1 + grow 1290 + or polyfill_pass1 + grow 300 + or obstruct_fom + templayer fomfill_pass2 topbox + slots 0 2500 1320 0 2500 1320 1360 0 + and-not obstruct_fom_pass2 + and topbox + shrink 1245 + grow 1245 + +#--------------------------------------------------- + + templayer obstruct_poly_coarse polyfill_pass1 + grow 60 + or fomfill_pass1,fomfill_pass2 + grow 300 + or obstruct_poly + templayer polyfill_coarse topbox + slots 0 720 360 0 720 360 240 120 + and-not obstruct_poly_coarse + and topbox + shrink 355 + grow 355 + +#--------------------------------------------------- + templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse + grow 60 + or fomfill_pass1,fomfill_pass2 + grow 300 + or obstruct_poly + templayer polyfill_medium topbox + slots 0 540 360 0 540 360 240 100 + and-not obstruct_poly_medium + and topbox + shrink 265 + grow 265 + +#--------------------------------------------------- + templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium + grow 60 + or fomfill_pass1,fomfill_pass2 + grow 300 + or obstruct_poly + templayer polyfill_fine topbox + slots 0 480 360 0 480 360 240 200 + and-not obstruct_poly_fine + and topbox + shrink 235 + grow 235 + +#--------------------------------------------------- + + templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2 + grow 1290 + or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine + grow 300 + or obstruct_fom + templayer fomfill_coarse topbox + slots 0 1500 1320 0 1500 1320 1360 0 + and-not obstruct_fom_coarse + and topbox + shrink 745 + grow 745 + +#--------------------------------------------------- + + templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse + grow 1290 + or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine + grow 300 + or obstruct_fom + templayer fomfill_fine topbox + slots 0 500 400 0 500 400 160 0 + and-not obstruct_fom_fine + and topbox + shrink 245 + grow 245 + +#--------------------------------------------------- + templayer fomfill + or fomfill_pass1 + or fomfill_pass2 + or fomfill_coarse + or fomfill_fine + + templayer polyfill + or polyfill_pass1 + or polyfill_coarse + or polyfill_medium + or polyfill_fine + + layer FOMMASK fomfill + calma 23 0 + layer POLYMASK polyfill + calma 28 0 + +#--------------------------------------------------- +# MET1 fill +#--------------------------------------------------- + + templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock + grow 3000 + templayer met1fill_coarse topbox + slots 0 2000 200 0 2000 200 700 0 + and-not obstruct_m1_coarse + and topbox + shrink 995 + grow 995 + + templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock + grow 2800 + or met1fill_coarse + grow 200 + templayer met1fill_medium topbox + slots 0 1000 200 0 1000 200 700 0 + and-not obstruct_m1_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock + grow 300 + or met1fill_coarse,met1fill_medium + grow 200 + templayer met1fill_fine topbox + slots 0 580 200 0 580 200 700 0 + and-not obstruct_m1_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock + grow 100 + or met1fill_coarse,met1fill_medium,met1fill_fine + grow 200 + templayer met1fill_veryfine topbox + slots 0 300 200 0 300 200 100 50 + and-not obstruct_m1_veryfine + and topbox + shrink 145 + grow 145 + + layer MET1MASK met1fill_coarse + or met1fill_medium + or met1fill_fine + or met1fill_veryfine + calma 36 0 + +#--------------------------------------------------- +# MET2 fill +#--------------------------------------------------- + templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock + grow 3000 + templayer met2fill_coarse topbox + slots 0 2000 200 0 2000 200 700 350 + and-not obstruct_m2 + and topbox + shrink 995 + grow 995 + + templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock + grow 2800 + or met2fill_coarse + grow 200 + templayer met2fill_medium topbox + slots 0 1000 200 0 1000 200 700 350 + and-not obstruct_m2_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock + grow 300 + or met2fill_coarse,met2fill_medium + grow 200 + templayer met2fill_fine topbox + slots 0 580 200 0 580 200 700 350 + and-not obstruct_m2_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock + grow 100 + or met2fill_coarse,met2fill_medium,met2fill_fine + grow 200 + templayer met2fill_veryfine topbox + slots 0 300 200 0 300 200 100 100 + and-not obstruct_m2_veryfine + and topbox + shrink 145 + grow 145 + + layer MET2MASK met2fill_coarse + or met2fill_medium + or met2fill_fine + or met2fill_veryfine + calma 41 0 + +#--------------------------------------------------- +# MET3 fill +#--------------------------------------------------- + templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock + grow 3000 + templayer met3fill_coarse topbox + slots 0 2000 300 0 2000 300 700 700 + and-not obstruct_m3 + and topbox + shrink 995 + grow 995 + + templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock + grow 2700 + or met3fill_coarse + grow 300 + templayer met3fill_medium topbox + slots 0 1000 300 0 1000 300 700 700 + and-not obstruct_m3_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock + grow 200 + or met3fill_coarse,met3fill_medium + grow 300 + templayer met3fill_fine topbox + slots 0 580 300 0 580 300 700 700 + and-not obstruct_m3_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock + # Note: Adding 0.1 to waffle rule to clear wide spacing rule + grow 100 + or met3fill_coarse,met3fill_medium,met3fill_fine + grow 300 + templayer met3fill_veryfine topbox + slots 0 400 300 0 400 300 150 200 + and-not obstruct_m3_veryfine + and topbox + shrink 195 + grow 195 + + layer MET3MASK met3fill_coarse + or met3fill_medium + or met3fill_fine + or met3fill_veryfine + calma 34 0 + +#--------------------------------------------------- +# MET4 fill +#--------------------------------------------------- + templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock + grow 3000 + templayer met4fill_coarse topbox + slots 0 2000 300 0 2000 300 700 1050 + and-not obstruct_m4 + and topbox + shrink 995 + grow 995 + + templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock + grow 2700 + or met4fill_coarse + grow 300 + templayer met4fill_medium topbox + slots 0 1000 300 0 1000 300 700 1050 + and-not obstruct_m4_medium + shrink 495 + grow 495 + + templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock + grow 200 + or met4fill_coarse,met4fill_medium + grow 300 + templayer met4fill_fine topbox + slots 0 580 300 0 580 300 700 1050 + and-not obstruct_m4_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock + # Note: Adding 0.1 to waffle rule to clear wide spacing rule + grow 100 + or met4fill_coarse,met4fill_medium,met4fill_fine + grow 300 + templayer met4fill_veryfine topbox + slots 0 400 300 0 400 300 150 300 + and-not obstruct_m4_veryfine + and topbox + shrink 195 + grow 195 + + layer MET4MASK met4fill_coarse + or met4fill_medium + or met4fill_fine + or met4fill_veryfine + calma 51 0 + +#--------------------------------------------------- +# MET5 fill +#--------------------------------------------------- + templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock + grow 3000 + templayer met5fill_gen topbox + slots 0 3000 1600 0 3000 1600 1000 100 + and-not obstruct_m5 + and topbox + shrink 1495 + grow 1495 + + layer MET5MASK met5fill_gen + calma 59 0 + +end + +#----------------------------------------------------------------------- +cifinput +#----------------------------------------------------------------------- +# NOTE: All values in this section MUST be multiples of 25 +# or else magic will scale below the allowed layout grid size +#----------------------------------------------------------------------- + +style sky130 + scalefactor 10 nanometers + gridlimit 5 + + options ignore-unknown-layer-labels no-reconnect-labels + + ignore NPC + ignore SEALID + ignore CAPID + ignore LDNTM + ignore HVNTM + ignore POLYMOD + ignore LOWTAPDENSITY + + layer pnp NWELL,WELLTXT,WELLPIN + and PNPID + labels NWELL + labels WELLTXT text + labels WELLPIN port + + layer nwell NWELL,WELLTXT,WELLPIN + and-not PNPID + labels NWELL + labels WELLTXT text + labels WELLPIN port + + layer pwell SUBTXT,SUBPIN + labels SUBTXT text + labels SUBPIN port + + # Always draw pwell under p-tap + layer pwell TAP + and-not NWELL + + layer dnwell DNWELL + labels DNWELL + + layer npn DNWELL + and-not NWELL + and NPNID + + layer rpw PWRES + and DNWELL + labels PWRES + + templayer ndiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and-not NWELL + and-not PPLUS + and-not DIODE + and-not DIFFRES + and-not THKOX + and NPLUS + copyup ndifcheck + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + labels TAPPIN port + + layer ndiff ndiffarea + + # Copy ndiff areas up for contact checks + templayer xndifcheck ndifcheck + copyup ndifcheck + + templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and-not NWELL + and-not PPLUS + and-not DIODE + and-not DIFFRES + and THKOX + and NPLUS + copyup ndifcheck + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + + layer mvndiff mvndiffarea + + # Copy ndiff areas up for contact checks + templayer mvxndifcheck mvndifcheck + copyup mvndifcheck + + layer ndiode DIFF + and NPLUS + and DIODE + and-not NWELL + and-not POLY + and-not PPLUS + and-not THKOX + and-not LVTN + labels DIFF + + layer ndiodelvt DIFF + and NPLUS + and DIODE + and-not NWELL + and-not POLY + and-not PPLUS + and-not THKOX + and LVTN + labels DIFF + + templayer ndiodearea DIODE + and NPLUS + and-not THKOX + and-not NWELL + copyup DIODE,NPLUS + + layer ndiffres DIFFRES + and NPLUS + and-not THKOX + labels DIFF + + templayer pdiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and NWELL + and-not NPLUS + and-not DIODE + and-not THKOX + and PPLUS + copyup pdifcheck + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + + layer pdiff pdiffarea + + layer mvndiode DIFF + and NPLUS + and DIODE + and THKOX + and-not POLY + and-not PPLUS + and-not LVTN + labels DIFF + + layer nndiode DIFF + and NPLUS + and DIODE + and THKOX + and-not POLY + and-not PPLUS + and LVTN + labels DIFF + + templayer mvndiodearea DIODE + and NPLUS + and THKOX + and-not NWELL + copyup DIODE,NPLUS + + layer mvndiffres DIFFRES + and NPLUS + and THKOX + labels DIFF + + templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and NWELL + and-not NPLUS + and THKOX + and-not DIODE + and-not DIFFRES + and PPLUS + copyup mvpdifcheck + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + + layer mvpdiff mvpdiffarea + + # Copy pdiff areas up for contact checks + templayer xpdifcheck pdifcheck + copyup pdifcheck + + layer pdiode DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and-not HVTP + and DIODE + labels DIFF + + layer pdiodelvt DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not THKOX + and LVTN + and-not HVTP + and DIODE + labels DIFF + + layer pdiodehvt DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and HVTP + and DIODE + labels DIFF + + templayer pdiodearea DIODE + and PPLUS + and-not THKOX + copyup DIODE,PPLUS + + # Define pfet areas as known pdiff, regardless of the presence of a well. + + templayer pfetarea DIFF + and-not NPLUS + and-not THKOX + and POLY + + layer pfet pfetarea + and-not LVTN + and-not HVTP + and-not STDCELL + and-not COREID + labels DIFF + + layer scpfet pfetarea + and-not LVTN + and-not HVTP + and STDCELL + labels DIFF + + layer scpfethvt pfetarea + and-not LVTN + and HVTP + and STDCELL + labels DIFF + + layer ppu pfetarea + and-not LVTN + and HVTP + and COREID + labels DIFF + + layer pfetlvt pfetarea + and LVTN + labels DIFF + + layer pfetmvt pfetarea + and HVTR + labels DIFF + + layer pfethvt pfetarea + and HVTP + and-not STDCELL + and-not COREID + labels DIFF + + # Always force nwell under pfet (nwell encloses pdiff by 0.18) + layer nwell pfetarea + grow 180 + + # Copy mvpdiff areas up for contact checks + templayer mvxpdifcheck mvpdifcheck + copyup mvpdifcheck + + layer mvpdiode DIFF + and PPLUS + and-not POLY + and-not NPLUS + and THKOX + and DIODE + labels DIFF + + templayer mvpdiodearea DIODE + and PPLUS + and THKOX + copyup DIODE,PPLUS + + # Define pfet areas as known pdiff, + # regardless of the presence of a + # well. + + templayer mvpfetarea DIFF + and-not NPLUS + and THKOX + and POLY + + layer mvpfet mvpfetarea + labels DIFF + + layer pdiff DIFF,DIFFTXT,DIFFPIN + and-not NPLUS + and-not POLY + and-not THKOX + and-not DIODE + and-not DIFFRES + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + + layer pdiffres DIFFRES + and PPLUS + and NWELL + and-not THKOX + labels DIFF + + layer nfet DIFF + and POLY + and-not PPLUS + and NPLUS + and-not THKOX + and-not LVTN + and-not SONOS + and-not STDCELL + labels DIFF + + layer scnfet DIFF + and POLY + and-not PPLUS + and NPLUS + and-not NWELL + and-not THKOX + and-not LVTN + and-not SONOS + and STDCELL + labels DIFF + + layer npass DIFF + and POLY + and-not PPLUS + and NPLUS + and-not NWELL + and COREID + labels DIFF + + layer npd DIFF + and POLY + and-not PPLUS + and NPLUS + and-not NWELL + and COREID + # Shrink-grow operation eliminates the smaller npass device + shrink 70 + grow 70 + labels DIFF + + layer nfetlvt DIFF + and POLY + and-not PPLUS + and NPLUS + and-not THKOX + and LVTN + and-not SONOS + labels DIFF + + layer nsonos DIFF + and POLY + and-not PPLUS + and NPLUS + and-not THKOX + and LVTN + and SONOS + labels DIFF + + templayer nsdarea TAP + and NPLUS + and NWELL + and-not POLY + and-not PPLUS + and-not THKOX + copyup nsubcheck + + layer nsd nsdarea + labels TAP + + layer nsd TAP,TAPPIN + and NPLUS + and-not POLY + and-not THKOX + labels TAP + labels TAPPIN port + + layer corenvar TAP + and NPLUS + and POLY + and COREID + labels TAP + + templayer nsdexpand nsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer xnsubcheck nsubcheck + copyup nsubcheck + + templayer psdarea TAP + and PPLUS + and-not NWELL + and-not POLY + and-not NPLUS + and-not THKOX + and-not pfetexpand + copyup psubcheck + + layer psd psdarea + labels TAP + + layer psd TAP,TAPPIN + and PPLUS + and-not POLY + and-not THKOX + labels TAP + labels TAPPIN port + + layer corepvar TAP + and PPLUS + and POLY + and COREID + labels TAP + + templayer psdexpand psdarea + grow 500 + + layer mvpdiff DIFF,DIFFTXT,DIFFPIN + and-not NPLUS + and-not POLY + and THKOX + and mvpfetexpand + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + + layer mvpdiffres DIFFRES + and PPLUS + and NWELL + and THKOX + and-not mvrdpioedge + labels DIFF + + templayer mvnfetarea DIFF + and POLY + and-not PPLUS + and NPLUS + and-not LVTN + and THKOX + grow 1000 + + templayer mvnnfetarea DIFF,TAP + and POLY + and-not PPLUS + and NPLUS + and LVTN + and THKOX + and-not mvnfetarea + + layer mvnfet DIFF + and POLY + and-not PPLUS + and NPLUS + and THKOX + and-not mvnnfetarea + labels DIFF + + layer mvnnfet mvnnfetarea + labels DIFF + + templayer mvnsdarea TAP + and NPLUS + and NWELL + and-not POLY + and-not PPLUS + and THKOX + copyup mvnsubcheck + + layer mvnsd mvnsdarea + labels TAP + + layer mvnsd TAP,TAPPIN + and NPLUS + and THKOX + labels TAP + labels TAPPIN port + + templayer mvnsdexpand mvnsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer mvxnsubcheck mvnsubcheck + copyup mvnsubcheck + + templayer mvpsdarea DIFF + and PPLUS + and-not NWELL + and-not POLY + and-not NPLUS + and THKOX + and-not mvpfetexpand + copyup mvpsubcheck + + layer mvpsd mvpsdarea + labels DIFF + + layer mvpsd TAP,TAPPIN + and PPLUS + and THKOX + labels TAP + labels TAPPIN port + + templayer mvpsdexpand mvpsdarea + grow 500 + + # Copy psub areas up for contact checks + templayer xpsubcheck psubcheck + copyup psubcheck + + templayer mvxpsubcheck mvpsubcheck + copyup mvpsubcheck + + layer psd TAP + and-not PPLUS + and-not NPLUS + and-not POLY + and-not THKOX + and-not pfetexpand + and psdexpand + + layer nsd TAP + and-not PPLUS + and-not NPLUS + and-not POLY + and-not THKOX + and nsdexpand + + layer mvpsd TAP + and-not PPLUS + and-not NPLUS + and-not POLY + and THKOX + and-not mvpfetexpand + and mvpsdexpand + + layer mvnsd TAP + and-not PPLUS + and-not NPLUS + and-not POLY + and THKOX + and mvnsdexpand + + templayer hresarea POLY + and RPM + grow 3000 + + templayer uresarea POLY + and URPM + grow 3000 + + templayer diffresarea DIFFRES + and-not THKOX + grow 3000 + + templayer mvdiffresarea DIFFRES + and THKOX + grow 3000 + + templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea + + layer pfet POLY + and DIFF + and diffresarea + and-not NPLUS + and-not STDCELL + + layer scpfet POLY + and DIFF + and diffresarea + and-not HVTP + and-not NPLUS + and STDCELL + + layer scpfethvt POLY + and DIFF + and diffresarea + and HVTP + and-not NPLUS + and STDCELL + + templayer xpolyterm RPM,URPM + and POLY + and-not POLYRES + # add back the 0.06um contact surround in the direction of the resistor + grow 60 + and POLY + + layer xpc xpolyterm + + templayer polyarea POLY + and-not POLYRES + and-not POLYSHORT + and-not DIFF + and-not TAP + and-not RPM + and-not URPM + copyup polycheck + + layer poly polyarea,POLYTXT,POLYPIN + labels POLY + labels POLYTXT text + labels POLYPIN port + + # Copy (non-resistor) poly areas up for contact checks + templayer xpolycheck polycheck + copyup polycheck + + layer mrp1 POLY + and POLYRES + and-not RPM + and-not URPM + labels POLY + + layer rmp POLY + and POLYSHORT + labels POLY + + layer xhrpoly POLY + and POLYRES + and RPM + and-not URPM + and PPLUS + and NPC + and-not xpolyterm + labels POLY + + layer uhrpoly POLY + and POLYRES + and URPM + and-not RPM + and NPC + and-not xpolyterm + labels POLY + + templayer ndcbase CONT + and DIFF + and NPLUS + and-not NWELL + and LI + and-not THKOX + + layer ndc ndcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndcbase + labels CONT + + templayer nscbase CONT + and DIFF,TAP + and NPLUS + and NWELL + and LI + and-not THKOX + + layer nsc nscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or nscbase + labels CONT + + templayer pdcbase CONT + and DIFF + and PPLUS + and NWELL + and LI + and-not THKOX + + layer pdc pdcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdcbase + labels CONT + + templayer pdcnowell CONT + and DIFF + and PPLUS + and pfetexpand + and LI + and-not THKOX + + layer pdc pdcnowell + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdcnowell + labels CONT + + templayer pscbase CONT + and DIFF,TAP + and PPLUS + and-not NWELL + and-not pfetexpand + and LI + and-not THKOX + + layer psc pscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pscbase + labels CONT + + templayer pcbase CONT + and POLY + and-not DIFF + and-not RPM,URPM + and LI + + layer pc pcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pcbase + labels CONT + + templayer ndicbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not THKOX + and-not LVTN + + layer ndic ndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndicbase + labels CONT + + templayer ndilvtcbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not THKOX + and LVTN + + layer ndilvtc ndilvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndilvtcbase + labels CONT + + templayer pdicbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and-not HVTP + + layer pdic pdicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdicbase + labels CONT + + templayer pdilvtcbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and-not THKOX + and LVTN + and-not HVTP + + layer pdilvtc pdilvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdilvtcbase + labels CONT + + templayer pdihvtcbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and HVTP + + layer pdihvtc pdihvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdihvtcbase + labels CONT + + templayer mvndcbase CONT + and DIFF + and NPLUS + and-not NWELL + and LI + and THKOX + + layer mvndc mvndcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndcbase + labels CONT + + templayer mvnscbase CONT + and DIFF,TAP + and NPLUS + and NWELL + and LI + and THKOX + + layer mvnsc mvnscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvnscbase + labels CONT + + templayer mvpdcbase CONT + and DIFF + and PPLUS + and NWELL + and LI + and THKOX + + layer mvpdc mvpdcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdcbase + labels CONT + + templayer mvpdcnowell CONT + and DIFF + and PPLUS + and mvpfetexpand + and MET1 + and THKOX + + layer mvpdc mvpdcnowell + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdcnowell + labels CONT + + templayer mvpscbase CONT + and DIFF,TAP + and PPLUS + and-not NWELL + and-not mvpfetexpand + and LI + and THKOX + + layer mvpsc mvpscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpscbase + labels CONT + + templayer mvndicbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not LVTN + and THKOX + + layer mvndic mvndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndicbase + labels CONT + + templayer nndicbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and LVTN + and THKOX + + layer nndic nndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or nndicbase + labels CONT + + templayer mvpdicbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and THKOX + + layer mvpdic mvpdicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdicbase + labels CONT + + layer coreli LI,LITXT,LIPIN + and-not LIRES,LISHORT + and COREID + labels LI + labels LITXT text + labels LIPIN port + + layer locali LI,LITXT,LIPIN + and-not LIRES,LISHORT + and-not COREID + labels LI + labels LITXT text + labels LIPIN port + + layer rli LI + and LIRES,LISHORT + labels LIRES,LISHORT + + layer lic MCON + grow 95 + shrink 95 + shrink 85 + grow 85 + or MCON + labels MCON + + layer m1 MET1,MET1TXT,MET1PIN + and-not MET1RES,MET1SHORT + labels MET1 + labels MET1TXT text + labels MET1PIN port + + layer rm1 MET1 + and MET1RES,MET1SHORT + labels MET1RES,MET1SHORT + + layer m1fill MET1FILL + labels MET1FILL + + layer mimcap MET3 + and CAPM + labels CAPM + + layer mimcc VIA3 + and CAPM + grow 60 + grow 40 + shrink 40 + labels CAPM + + layer mimcap2 MET4 + and CAPM2 + labels CAPM2 + + layer mim2cc VIA4 + and CAPM2 + grow 190 + grow 210 + shrink 210 + labels CAPM2 + + + templayer m2cbase VIA1 + grow 55 + + layer m2c m2cbase + grow 30 + shrink 30 + shrink 130 + grow 130 + or m2cbase + + layer m2 MET2,MET2TXT,MET2PIN + and-not MET2RES,MET2SHORT + labels MET2 + labels MET2TXT text + labels MET2PIN port + + layer rm2 MET2 + and MET2RES,MET2SHORT + labels MET2RES,MET2SHORT + + layer m2fill MET2FILL + labels MET2FILL + + templayer m3cbase VIA2 + grow 40 + + layer m3c m3cbase + grow 60 + shrink 60 + shrink 140 + grow 140 + or m3cbase + + layer m3 MET3,MET3TXT,MET3PIN + and-not MET3RES,MET3SHORT + and-not CAPM + labels MET3 + labels MET3TXT text + labels MET3PIN port + + layer rm3 MET3 + and MET3RES,MET3SHORT + labels MET3RES,MET3SHORT + + layer m3fill MET3FILL + labels MET3FILL + + + templayer via3base VIA3 + and-not CAPM + grow 60 + + layer via3 via3base + grow 40 + shrink 40 + shrink 160 + grow 160 + or via3base + + layer m4 MET4,MET4TXT,MET4PIN + and-not MET4RES,MET4SHORT + and-not CAPM2 + labels MET4 + labels MET4TXT text + labels MET4PIN port + + layer rm4 MET4 + and MET4RES,MET4SHORT + labels MET4RES,MET4SHORT + + layer m4fill MET4FILL + labels MET4FILL + + layer m5 MET5,MET5TXT,MET5PIN + and-not MET5RES,MET5SHORT + labels MET5 + labels MET5TXT text + labels MET5PIN port + + layer rm5 MET5 + and MET5RES,MET5SHORT + labels MET5RES,MET5SHORT + + layer m5fill MET5FILL + labels MET5FILL + + templayer via4base VIA4 + and-not CAPM2 + grow 190 + + layer via4 via4base + grow 210 + shrink 210 + shrink 590 + grow 590 + or via4base + + layer metrdl RDL,RDLTXT,RDLPIN + labels RDL + labels RDLTXT text + labels RDLPIN port + + # Find diffusion not covered in + # NPLUS or PPLUS and pull it into + # the next layer up + + templayer gentrans DIFF + and-not PPLUS + and-not NPLUS + and POLY + copyup DIFF,POLY + + templayer gendiff DIFF,TAP + and-not PPLUS + and-not NPLUS + and-not POLY + copyup DIFF + + # Handle contacts found by copyup + + templayer ndiccopy CONT + and LI + and DIODE + and NPLUS + and-not THKOX + + layer ndic ndiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndiccopy + labels CONT + + templayer mvndiccopy CONT + and LI + and DIODE + and NPLUS + and THKOX + + layer mvndic mvndiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndiccopy + labels CONT + + templayer pdiccopy CONT + and LI + and DIODE + and PPLUS + and-not THKOX + + layer pdic pdiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdiccopy + labels CONT + + templayer mvpdiccopy CONT + and LI + and DIODE + and PPLUS + and THKOX + + layer mvpdic mvpdiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdiccopy + labels CONT + + templayer ndccopy CONT + and ndifcheck + + layer ndc ndccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndccopy + labels CONT + + templayer mvndccopy CONT + and mvndifcheck + + layer mvndc mvndccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndccopy + labels CONT + + templayer pdccopy CONT + and pdifcheck + + layer pdc pdccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdccopy + labels CONT + + templayer mvpdccopy CONT + and mvpdifcheck + + layer mvpdc mvpdccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdccopy + labels CONT + + templayer pccopy CONT + and polycheck + + layer pc pccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pccopy + labels CONT + + templayer nsccopy CONT + and nsubcheck + + layer nsc nsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or nsccopy + labels CONT + + templayer mvnsccopy CONT + and mvnsubcheck + + layer mvnsc mvnsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvnsccopy + labels CONT + + templayer psccopy CONT + and psubcheck + + layer psc psccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or psccopy + labels CONT + + templayer mvpsccopy CONT + and mvpsubcheck + + layer mvpsc mvpsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpsccopy + labels CONT + + # Find contacts not covered in + # metal and pull them into the + # next layer up + + templayer gencont CONT + and LI + and-not DIFF,TAP + and-not POLY + and-not DIODE + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + copyup CONT,LI + + templayer barecont CONT + and-not LI + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + copyup CONT + + layer glass GLASS,PADTXT,PADPIN + labels GLASS + labels PADTXT text + labels PADPIN port + + templayer boundary BOUND,STDCELL,PADCELL + boundary + + layer comment LVSTEXT + labels LVSTEXT text + + layer comment TTEXT + labels TTEXT text + + layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 + labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 + +# MOS Varactor + + layer var POLY + and TAP + and NPLUS + and NWELL + and-not THKOX + and-not HVTP + # NOTE: Else forms a varactor that is not in the vendor netlist. + and-not COREID + labels POLY + + layer varhvt POLY + and TAP + and NPLUS + and NWELL + and-not THKOX + and HVTP + labels POLY + + layer mvvar POLY + and TAP + and NPLUS + and NWELL + and THKOX + labels POLY + + calma NWELL 64 20 + calma DIFF 65 20 + calma DNWELL 64 18 + calma PWRES 64 13 + calma TAP 65 44 + # LVTN + calma LVTN 125 44 + # HVTR + calma HVTR 18 20 + # HVTP + calma HVTP 78 44 + # SONOS (TUNM) + calma SONOS 80 20 + # NPLUS = NSDM + calma NPLUS 93 44 + # PPLUS = PSDM + calma PPLUS 94 20 + # HVI + calma THKOX 75 20 + # NPC + calma NPC 95 20 + # P+ POLY MASK + calma RPM 86 20 + calma URPM 79 20 + calma LDNTM 11 44 + calma HVNTM 125 20 + # Poly resistor ID mark + calma POLYRES 66 13 + # Diffusion resistor ID mark + calma DIFFRES 65 13 + calma POLY 66 20 + calma POLYMOD 66 83 + # Diode ID mark + calma DIODE 81 23 + # Bipolar NPN mark + calma NPNID 82 20 + # Bipolar PNP mark + calma PNPID 82 44 + # Capacitor ID + calma CAPID 82 64 + # Core area ID mark + calma COREID 81 2 + # Standard cell ID mark + calma STDCELL 81 4 + # Padframe cell ID mark + calma PADCELL 81 3 + # Seal ring ID mark + calma SEALID 81 1 + # Low tap density ID mark + calma LOWTAPDENSITY 81 14 + + # LICON + calma CONT 66 44 + calma LI 67 20 + calma MCON 67 44 + + calma MET1 68 20 + calma VIA1 68 44 + calma MET2 69 20 + calma VIA2 69 44 + calma MET3 70 20 + calma VIA3 70 44 + calma MET4 71 20 + calma VIA4 71 44 + calma MET5 72 20 + calma RDL 74 20 + calma GLASS 76 20 + + calma SUBPIN 64 59 + calma PADPIN 76 5 + calma DIFFPIN 65 6 + calma TAPPIN 65 5 + calma WELLPIN 64 5 + calma LIPIN 67 5 + calma POLYPIN 66 5 + calma MET1PIN 68 5 + calma MET2PIN 69 5 + calma MET3PIN 70 5 + calma MET4PIN 71 5 + calma MET5PIN 72 5 + calma RDLPIN 74 5 + + calma LIRES 67 13 + calma MET1RES 68 13 + calma MET2RES 69 13 + calma MET3RES 70 13 + calma MET4RES 71 13 + calma MET5RES 72 13 + + calma MET1FILL 68 28 + calma MET2FILL 69 28 + calma MET3FILL 70 28 + calma MET4FILL 71 28 + calma MET5FILL 72 28 + + calma POLYSHORT 66 15 + calma LISHORT 67 15 + calma MET1SHORT 68 15 + calma MET2SHORT 69 15 + calma MET3SHORT 70 15 + calma MET4SHORT 71 15 + calma MET5SHORT 72 15 + + calma SUBTXT 122 16 + calma PADTXT 76 16 + calma DIFFTXT 65 16 + calma POLYTXT 66 16 + calma WELLTXT 64 16 + calma LITXT 67 16 + calma MET1TXT 68 16 + calma MET2TXT 69 16 + calma MET3TXT 70 16 + calma MET4TXT 71 16 + calma MET5TXT 72 16 + calma RDLPIN 74 16 + + calma BOUND 235 4 + + calma LVSTEXT 83 44 + + calma CAPM 89 44 + calma CAPM2 97 44 + + calma FILLOBSM1 62 24 + calma FILLOBSM2 105 52 + calma FILLOBSM3 107 24 + calma FILLOBSM4 112 4 + +#----------------------------------------------------------------------- + +style vendorimport + scalefactor 10 nanometers + gridlimit 5 + + options ignore-unknown-layer-labels no-reconnect-labels + + ignore NPC + ignore SEALID + ignore CAPID + ignore LDNTM + ignore HVNTM + ignore POLYMOD + ignore LOWTAPDENSITY + + layer pnp NWELL,WELLTXT,WELLPIN + and PNPID + labels NWELL + labels WELLTXT port + labels WELLPIN port + + layer nwell NWELL,WELLTXT,WELLPIN + and-not PNPID + labels NWELL + labels WELLTXT port + labels WELLPIN port + + layer pwell SUBTXT,SUBPIN + labels SUBTXT port + labels SUBPIN port + + # Always draw pwell under p-tap + layer pwell TAP + and-not NWELL + + layer dnwell DNWELL + labels DNWELL + + layer npn DNWELL + and-not NWELL + and NPNID + + layer rpw PWRES + and DNWELL + labels PWRES + + templayer ndiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and-not NWELL + and-not PPLUS + and-not DIODE + and-not DIFFRES + and-not THKOX + and NPLUS + copyup ndifcheck + labels DIFF + labels DIFFTXT port + labels DIFFPIN port + labels TAPPIN port + + layer ndiff ndiffarea + + # Copy ndiff areas up for contact checks + templayer xndifcheck ndifcheck + copyup ndifcheck + + templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and-not NWELL + and-not PPLUS + and-not DIODE + and-not DIFFRES + and THKOX + and NPLUS + copyup ndifcheck + labels DIFF + labels DIFFTXT port + labels DIFFPIN port + + layer mvndiff mvndiffarea + + # Copy ndiff areas up for contact checks + templayer mvxndifcheck mvndifcheck + copyup mvndifcheck + + layer ndiode DIFF + and NPLUS + and DIODE + and-not NWELL + and-not POLY + and-not PPLUS + and-not THKOX + and-not LVTN + labels DIFF + + layer ndiodelvt DIFF + and NPLUS + and DIODE + and-not NWELL + and-not POLY + and-not PPLUS + and-not THKOX + and LVTN + labels DIFF + + templayer ndiodearea DIODE + and NPLUS + and-not THKOX + and-not NWELL + copyup DIODE,NPLUS + + layer ndiffres DIFFRES + and NPLUS + and-not THKOX + labels DIFF + + templayer pdiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and NWELL + and-not NPLUS + and-not DIODE + and-not THKOX + and PPLUS + copyup pdifcheck + labels DIFF + labels DIFFTXT port + labels DIFFPIN port + + layer pdiff pdiffarea + + layer mvndiode DIFF + and NPLUS + and DIODE + and THKOX + and-not POLY + and-not PPLUS + and-not LVTN + labels DIFF + + layer nndiode DIFF + and NPLUS + and DIODE + and THKOX + and-not POLY + and-not PPLUS + and LVTN + labels DIFF + + templayer mvndiodearea DIODE + and NPLUS + and THKOX + and-not NWELL + copyup DIODE,NPLUS + + layer mvndiffres DIFFRES + and NPLUS + and THKOX + labels DIFF + + templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and NWELL + and-not NPLUS + and THKOX + and-not DIODE + and-not DIFFRES + and PPLUS + copyup mvpdifcheck + labels DIFF + labels DIFFTXT port + labels DIFFPIN port + + layer mvpdiff mvpdiffarea + + # Copy pdiff areas up for contact checks + templayer xpdifcheck pdifcheck + copyup pdifcheck + + layer pdiode DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and-not HVTP + and DIODE + labels DIFF + + layer pdiodelvt DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not THKOX + and LVTN + and-not HVTP + and DIODE + labels DIFF + + layer pdiodehvt DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and HVTP + and DIODE + labels DIFF + + templayer pdiodearea DIODE + and PPLUS + and-not THKOX + copyup DIODE,PPLUS + + # Define pfet areas as known pdiff, regardless of the presence of a well. + + templayer pfetarea DIFF + and-not NPLUS + and-not THKOX + and POLY + + layer pfet pfetarea + and-not LVTN + and-not HVTP + and-not STDCELL + and-not COREID + labels DIFF + + layer scpfet pfetarea + and-not LVTN + and-not HVTP + and STDCELL + labels DIFF + + layer scpfethvt pfetarea + and-not LVTN + and HVTP + and STDCELL + labels DIFF + + layer ppu pfetarea + and-not LVTN + and HVTP + and COREID + labels DIFF + + layer pfetlvt pfetarea + and LVTN + labels DIFF + + layer pfetmvt pfetarea + and HVTR + labels DIFF + + layer pfethvt pfetarea + and HVTP + and-not STDCELL + and-not COREID + labels DIFF + + # Always force nwell under pfet (nwell encloses pdiff by 0.18) + layer nwell pfetarea + grow 180 + + # Copy mvpdiff areas up for contact checks + templayer mvxpdifcheck mvpdifcheck + copyup mvpdifcheck + + layer mvpdiode DIFF + and PPLUS + and-not POLY + and-not NPLUS + and THKOX + and DIODE + labels DIFF + + templayer mvpdiodearea DIODE + and PPLUS + and THKOX + copyup DIODE,PPLUS + + # Define pfet areas as known pdiff, + # regardless of the presence of a + # well. + + templayer mvpfetarea DIFF + and-not NPLUS + and THKOX + and POLY + + layer mvpfet mvpfetarea + labels DIFF + + layer pdiff DIFF,DIFFTXT,DIFFPIN + and-not NPLUS + and-not POLY + and-not THKOX + and-not DIODE + and-not DIFFRES + labels DIFF + labels DIFFTXT port + labels DIFFPIN port + + layer pdiffres DIFFRES + and PPLUS + and NWELL + and-not THKOX + labels DIFF + + layer nfet DIFF + and POLY + and-not PPLUS + and NPLUS + and-not THKOX + and-not LVTN + and-not SONOS + and-not STDCELL + labels DIFF + + layer scnfet DIFF + and POLY + and-not PPLUS + and NPLUS + and-not NWELL + and-not THKOX + and-not LVTN + and-not SONOS + and STDCELL + labels DIFF + + layer npass DIFF + and POLY + and-not PPLUS + and NPLUS + and-not NWELL + and COREID + labels DIFF + + layer npd DIFF + and POLY + and-not PPLUS + and NPLUS + and-not NWELL + and COREID + # Shrink-grow operation eliminates the smaller npass device + shrink 70 + grow 70 + labels DIFF + + layer nfetlvt DIFF + and POLY + and-not PPLUS + and NPLUS + and-not THKOX + and LVTN + and-not SONOS + labels DIFF + + layer nsonos DIFF + and POLY + and-not PPLUS + and NPLUS + and-not THKOX + and LVTN + and SONOS + labels DIFF + + templayer nsdarea TAP + and NPLUS + and NWELL + and-not POLY + and-not PPLUS + and-not THKOX + copyup nsubcheck + + layer nsd nsdarea + labels TAP + + layer nsd TAP,TAPPIN + and NPLUS + and-not POLY + and-not THKOX + labels TAP + labels TAPPIN port + + layer corenvar TAP + and NPLUS + and POLY + and COREID + labels TAP + + templayer nsdexpand nsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer xnsubcheck nsubcheck + copyup nsubcheck + + templayer psdarea TAP + and PPLUS + and-not NWELL + and-not POLY + and-not NPLUS + and-not THKOX + and-not pfetexpand + copyup psubcheck + + layer psd psdarea + labels TAP + + layer psd TAP,TAPPIN + and PPLUS + and-not POLY + and-not THKOX + labels TAP + labels TAPPIN port + + layer corepvar TAP + and PPLUS + and POLY + and COREID + labels TAP + + templayer psdexpand psdarea + grow 500 + + layer mvpdiff DIFF,DIFFTXT,DIFFPIN + and-not NPLUS + and-not POLY + and THKOX + and mvpfetexpand + labels DIFF + labels DIFFTXT port + labels DIFFPIN port + + layer mvpdiffres DIFFRES + and PPLUS + and NWELL + and THKOX + and-not mvrdpioedge + labels DIFF + + templayer mvnfetarea DIFF + and POLY + and-not PPLUS + and NPLUS + and-not LVTN + and THKOX + grow 1000 + + templayer mvnnfetarea DIFF,TAP + and POLY + and-not PPLUS + and NPLUS + and LVTN + and THKOX + and-not mvnfetarea + + layer mvnfet DIFF + and POLY + and-not PPLUS + and NPLUS + and THKOX + and-not mvnnfetarea + labels DIFF + + layer mvnnfet mvnnfetarea + labels DIFF + + templayer mvnsdarea TAP + and NPLUS + and NWELL + and-not POLY + and-not PPLUS + and THKOX + copyup mvnsubcheck + + layer mvnsd mvnsdarea + labels TAP + + layer mvnsd TAP,TAPPIN + and NPLUS + and THKOX + labels TAP + labels TAPPIN port + + templayer mvnsdexpand mvnsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer mvxnsubcheck mvnsubcheck + copyup mvnsubcheck + + templayer mvpsdarea DIFF + and PPLUS + and-not NWELL + and-not POLY + and-not NPLUS + and THKOX + and-not mvpfetexpand + copyup mvpsubcheck + + layer mvpsd mvpsdarea + labels DIFF + + layer mvpsd TAP,TAPPIN + and PPLUS + and THKOX + labels TAP + labels TAPPIN port + + templayer mvpsdexpand mvpsdarea + grow 500 + + # Copy psub areas up for contact checks + templayer xpsubcheck psubcheck + copyup psubcheck + + templayer mvxpsubcheck mvpsubcheck + copyup mvpsubcheck + + layer psd TAP + and-not PPLUS + and-not NPLUS + and-not POLY + and-not THKOX + and-not pfetexpand + and psdexpand + + layer nsd TAP + and-not PPLUS + and-not NPLUS + and-not POLY + and-not THKOX + and nsdexpand + + layer mvpsd TAP + and-not PPLUS + and-not NPLUS + and-not POLY + and THKOX + and-not mvpfetexpand + and mvpsdexpand + + layer mvnsd TAP + and-not PPLUS + and-not NPLUS + and-not POLY + and THKOX + and mvnsdexpand + + templayer hresarea POLY + and RPM + grow 3000 + + templayer uresarea POLY + and URPM + grow 3000 + + templayer diffresarea DIFFRES + and-not THKOX + grow 3000 + + templayer mvdiffresarea DIFFRES + and THKOX + grow 3000 + + templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea + + layer pfet POLY + and DIFF + and diffresarea + and-not NPLUS + and-not STDCELL + + layer scpfet POLY + and DIFF + and diffresarea + and-not HVTP + and-not NPLUS + and STDCELL + + layer scpfethvt POLY + and DIFF + and diffresarea + and HVTP + and-not NPLUS + and STDCELL + + templayer xpolyterm RPM,URPM + and POLY + and-not POLYRES + # add back the 0.06um contact surround in the direction of the resistor + grow 60 + and POLY + + layer xpc xpolyterm + + templayer polyarea POLY + and-not POLYRES + and-not POLYSHORT + and-not DIFF + and-not TAP + and-not RPM + and-not URPM + copyup polycheck + + layer poly polyarea,POLYTXT,POLYPIN + labels POLY + labels POLYTXT port + labels POLYPIN port + + # Copy (non-resistor) poly areas up for contact checks + templayer xpolycheck polycheck + copyup polycheck + + layer mrp1 POLY + and POLYRES + and-not RPM + and-not URPM + labels POLY + + layer rmp POLY + and POLYSHORT + labels POLY + + layer xhrpoly POLY + and POLYRES + and RPM + and-not URPM + and PPLUS + and NPC + and-not xpolyterm + labels POLY + + layer uhrpoly POLY + and POLYRES + and URPM + and-not RPM + and NPC + and-not xpolyterm + labels POLY + + templayer ndcbase CONT + and DIFF + and NPLUS + and-not NWELL + and LI + and-not THKOX + + layer ndc ndcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndcbase + labels CONT + + templayer nscbase CONT + and DIFF,TAP + and NPLUS + and NWELL + and LI + and-not THKOX + + layer nsc nscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or nscbase + labels CONT + + templayer pdcbase CONT + and DIFF + and PPLUS + and NWELL + and LI + and-not THKOX + + layer pdc pdcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdcbase + labels CONT + + templayer pdcnowell CONT + and DIFF + and PPLUS + and pfetexpand + and LI + and-not THKOX + + layer pdc pdcnowell + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdcnowell + labels CONT + + templayer pscbase CONT + and DIFF,TAP + and PPLUS + and-not NWELL + and-not pfetexpand + and LI + and-not THKOX + + layer psc pscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pscbase + labels CONT + + templayer pcbase CONT + and POLY + and-not DIFF + and-not RPM,URPM + and LI + + layer pc pcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pcbase + labels CONT + + templayer ndicbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not THKOX + and-not LVTN + + layer ndic ndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndicbase + labels CONT + + templayer ndilvtcbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not THKOX + and LVTN + + layer ndilvtc ndilvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndilvtcbase + labels CONT + + templayer pdicbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and-not HVTP + + layer pdic pdicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdicbase + labels CONT + + templayer pdilvtcbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and-not THKOX + and LVTN + and-not HVTP + + layer pdilvtc pdilvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdilvtcbase + labels CONT + + templayer pdihvtcbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and HVTP + + layer pdihvtc pdihvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdihvtcbase + labels CONT + + templayer mvndcbase CONT + and DIFF + and NPLUS + and-not NWELL + and LI + and THKOX + + layer mvndc mvndcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndcbase + labels CONT + + templayer mvnscbase CONT + and DIFF,TAP + and NPLUS + and NWELL + and LI + and THKOX + + layer mvnsc mvnscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvnscbase + labels CONT + + templayer mvpdcbase CONT + and DIFF + and PPLUS + and NWELL + and LI + and THKOX + + layer mvpdc mvpdcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdcbase + labels CONT + + templayer mvpdcnowell CONT + and DIFF + and PPLUS + and mvpfetexpand + and MET1 + and THKOX + + layer mvpdc mvpdcnowell + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdcnowell + labels CONT + + templayer mvpscbase CONT + and DIFF,TAP + and PPLUS + and-not NWELL + and-not mvpfetexpand + and LI + and THKOX + + layer mvpsc mvpscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpscbase + labels CONT + + templayer mvndicbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not LVTN + and THKOX + + layer mvndic mvndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndicbase + labels CONT + + templayer nndicbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and LVTN + and THKOX + + layer nndic nndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or nndicbase + labels CONT + + templayer mvpdicbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and THKOX + + layer mvpdic mvpdicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdicbase + labels CONT + + layer coreli LI,LITXT,LIPIN + and-not LIRES,LISHORT + and COREID + labels LI + labels LITXT port + labels LIPIN port + + layer locali LI,LITXT,LIPIN + and-not LIRES,LISHORT + and-not COREID + labels LI + labels LITXT port + labels LIPIN port + + layer rli LI + and LIRES,LISHORT + labels LIRES,LISHORT + + layer lic MCON + grow 95 + shrink 95 + shrink 85 + grow 85 + or MCON + labels MCON + + layer m1 MET1,MET1TXT,MET1PIN + and-not MET1RES,MET1SHORT + labels MET1 + labels MET1TXT port + labels MET1PIN port + + layer rm1 MET1 + and MET1RES,MET1SHORT + labels MET1RES,MET1SHORT + + layer m1fill MET1FILL + labels MET1FILL + + layer mimcap MET3 + and CAPM + labels CAPM + + layer mimcc VIA3 + and CAPM + grow 60 + grow 40 + shrink 40 + labels CAPM + + layer mimcap2 MET4 + and CAPM2 + labels CAPM2 + + layer mim2cc VIA4 + and CAPM2 + grow 190 + grow 210 + shrink 210 + labels CAPM2 + + + templayer m2cbase VIA1 + grow 55 + + layer m2c m2cbase + grow 30 + shrink 30 + shrink 130 + grow 130 + or m2cbase + + layer m2 MET2,MET2TXT,MET2PIN + and-not MET2RES,MET2SHORT + labels MET2 + labels MET2TXT port + labels MET2PIN port + + layer rm2 MET2 + and MET2RES,MET2SHORT + labels MET2RES,MET2SHORT + + layer m2fill MET2FILL + labels MET2FILL + + templayer m3cbase VIA2 + grow 40 + + layer m3c m3cbase + grow 60 + shrink 60 + shrink 140 + grow 140 + or m3cbase + + layer m3 MET3,MET3TXT,MET3PIN + and-not MET3RES,MET3SHORT + and-not CAPM + labels MET3 + labels MET3TXT port + labels MET3PIN port + + layer rm3 MET3 + and MET3RES,MET3SHORT + labels MET3RES,MET3SHORT + + layer m3fill MET3FILL + labels MET3FILL + + + templayer via3base VIA3 + and-not CAPM + grow 60 + + layer via3 via3base + grow 40 + shrink 40 + shrink 160 + grow 160 + or via3base + + layer m4 MET4,MET4TXT,MET4PIN + and-not MET4RES,MET4SHORT + and-not CAPM2 + labels MET4 + labels MET4TXT port + labels MET4PIN port + + layer rm4 MET4 + and MET4RES,MET4SHORT + labels MET4RES,MET4SHORT + + layer m4fill MET4FILL + labels MET4FILL + + layer m5 MET5,MET5TXT,MET5PIN + and-not MET5RES,MET5SHORT + labels MET5 + labels MET5TXT port + labels MET5PIN port + + layer rm5 MET5 + and MET5RES,MET5SHORT + labels MET5RES,MET5SHORT + + layer m5fill MET5FILL + labels MET5FILL + + templayer via4base VIA4 + and-not CAPM2 + grow 190 + + layer via4 via4base + grow 210 + shrink 210 + shrink 590 + grow 590 + or via4base + + layer metrdl RDL,RDLTXT,RDLPIN + labels RDL + labels RDLTXT port + labels RDLPIN port + + # Find diffusion not covered in + # NPLUS or PPLUS and pull it into + # the next layer up + + templayer gentrans DIFF + and-not PPLUS + and-not NPLUS + and POLY + copyup DIFF,POLY + + templayer gendiff DIFF,TAP + and-not PPLUS + and-not NPLUS + and-not POLY + copyup DIFF + + # Handle contacts found by copyup + + templayer ndiccopy CONT + and LI + and DIODE + and NPLUS + and-not THKOX + + layer ndic ndiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndiccopy + labels CONT + + templayer mvndiccopy CONT + and LI + and DIODE + and NPLUS + and THKOX + + layer mvndic mvndiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndiccopy + labels CONT + + templayer pdiccopy CONT + and LI + and DIODE + and PPLUS + and-not THKOX + + layer pdic pdiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdiccopy + labels CONT + + templayer mvpdiccopy CONT + and LI + and DIODE + and PPLUS + and THKOX + + layer mvpdic mvpdiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdiccopy + labels CONT + + templayer ndccopy CONT + and ndifcheck + + layer ndc ndccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndccopy + labels CONT + + templayer mvndccopy CONT + and mvndifcheck + + layer mvndc mvndccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndccopy + labels CONT + + templayer pdccopy CONT + and pdifcheck + + layer pdc pdccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdccopy + labels CONT + + templayer mvpdccopy CONT + and mvpdifcheck + + layer mvpdc mvpdccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdccopy + labels CONT + + templayer pccopy CONT + and polycheck + + layer pc pccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pccopy + labels CONT + + templayer nsccopy CONT + and nsubcheck + + layer nsc nsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or nsccopy + labels CONT + + templayer mvnsccopy CONT + and mvnsubcheck + + layer mvnsc mvnsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvnsccopy + labels CONT + + templayer psccopy CONT + and psubcheck + + layer psc psccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or psccopy + labels CONT + + templayer mvpsccopy CONT + and mvpsubcheck + + layer mvpsc mvpsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpsccopy + labels CONT + + # Find contacts not covered in + # metal and pull them into the + # next layer up + + templayer gencont CONT + and LI + and-not DIFF,TAP + and-not POLY + and-not DIODE + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + copyup CONT,LI + + templayer barecont CONT + and-not LI + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + copyup CONT + + layer glass GLASS,PADTXT,PADPIN + labels GLASS + labels PADTXT port + labels PADPIN port + + templayer boundary BOUND,STDCELL,PADCELL + boundary + + layer comment LVSTEXT + labels LVSTEXT text + + layer comment TTEXT + labels TTEXT text + + layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 + labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 + +# MOS Varactor + + layer var POLY + and TAP + and NPLUS + and NWELL + and-not THKOX + and-not HVTP + # NOTE: Else forms a varactor that is not in the vendor netlist. + and-not COREID + labels POLY + + layer varhvt POLY + and TAP + and NPLUS + and NWELL + and-not THKOX + and HVTP + labels POLY + + layer mvvar POLY + and TAP + and NPLUS + and NWELL + and THKOX + labels POLY + + calma NWELL 64 20 + calma DIFF 65 20 + calma DNWELL 64 18 + calma PWRES 64 13 + calma TAP 65 44 + # LVTN + calma LVTN 125 44 + # HVTR + calma HVTR 18 20 + # HVTP + calma HVTP 78 44 + # SONOS (TUNM) + calma SONOS 80 20 + # NPLUS = NSDM + calma NPLUS 93 44 + # PPLUS = PSDM + calma PPLUS 94 20 + # HVI + calma THKOX 75 20 + # NPC + calma NPC 95 20 + # P+ POLY MASK + calma RPM 86 20 + calma URPM 79 20 + calma LDNTM 11 44 + calma HVNTM 125 20 + # Poly resistor ID mark + calma POLYRES 66 13 + # Diffusion resistor ID mark + calma DIFFRES 65 13 + calma POLY 66 20 + calma POLYMOD 66 83 + # Diode ID mark + calma DIODE 81 23 + # Bipolar NPN mark + calma NPNID 82 20 + # Bipolar PNP mark + calma PNPID 82 44 + # Capacitor ID + calma CAPID 82 64 + # Core area ID mark + calma COREID 81 2 + # Standard cell ID mark + calma STDCELL 81 4 + # Padframe cell ID mark + calma PADCELL 81 3 + # Seal ring ID mark + calma SEALID 81 1 + # Low tap density ID mark + calma LOWTAPDENSITY 81 14 + + # LICON + calma CONT 66 44 + calma LI 67 20 + calma MCON 67 44 + + calma MET1 68 20 + calma VIA1 68 44 + calma MET2 69 20 + calma VIA2 69 44 + calma MET3 70 20 + calma VIA3 70 44 + calma MET4 71 20 + calma VIA4 71 44 + calma MET5 72 20 + calma RDL 74 20 + calma GLASS 76 20 + + calma SUBPIN 64 59 + calma PADPIN 76 5 + calma DIFFPIN 65 6 + calma TAPPIN 65 5 + calma WELLPIN 64 5 + calma LIPIN 67 5 + calma POLYPIN 66 5 + calma MET1PIN 68 5 + calma MET2PIN 69 5 + calma MET3PIN 70 5 + calma MET4PIN 71 5 + calma MET5PIN 72 5 + calma RDLPIN 74 5 + + calma LIRES 67 13 + calma MET1RES 68 13 + calma MET2RES 69 13 + calma MET3RES 70 13 + calma MET4RES 71 13 + calma MET5RES 72 13 + + calma MET1FILL 68 28 + calma MET2FILL 69 28 + calma MET3FILL 70 28 + calma MET4FILL 71 28 + calma MET5FILL 72 28 + + calma POLYSHORT 66 15 + calma LISHORT 67 15 + calma MET1SHORT 68 15 + calma MET2SHORT 69 15 + calma MET3SHORT 70 15 + calma MET4SHORT 71 15 + calma MET5SHORT 72 15 + + calma SUBTXT 122 16 + calma PADTXT 76 16 + calma DIFFTXT 65 16 + calma POLYTXT 66 16 + calma WELLTXT 64 16 + calma LITXT 67 16 + calma MET1TXT 68 16 + calma MET2TXT 69 16 + calma MET3TXT 70 16 + calma MET4TXT 71 16 + calma MET5TXT 72 16 + calma RDLPIN 74 16 + + calma BOUND 235 4 + + calma LVSTEXT 83 44 + + calma CAPM 89 44 + calma CAPM2 97 44 + + calma FILLOBSM1 62 24 + calma FILLOBSM2 105 52 + calma FILLOBSM3 107 24 + calma FILLOBSM4 112 4 + +style waffleimport + # This style is for reading back and validating shapes + # generated by the "wafflefill" cifoutput style. + + scalefactor 10 nanometers + gridlimit 5 + + options ignore-unknown-layer-labels no-reconnect-labels + + layer ndiff FOMMASK + layer poly POLYMASK + layer metal1 MET1MASK + layer metal2 MET2MASK + layer metal3 MET3MASK + layer metal4 MET4MASK + layer metal5 MET5MASK + + calma FOMMASK 23 0 + calma POLYMASK 28 0 + calma MET1MASK 36 0 + calma MET2MASK 41 0 + calma MET3MASK 34 0 + calma MET4MASK 51 0 + calma MET5MASK 59 0 + +style rdlimport + # This style is for reading shapes generated with the RDL layers + + scalefactor 10 nanometers + gridlimit 5 + + options ignore-unknown-layer-labels no-reconnect-labels + + layer mrdl RDL + layer mrdlc RDLC + + calma RDL 10 0 + calma RDLC 20 0 + +end + +#----------------------------------------------------- +# Digital flow maze router cost parameters +#----------------------------------------------------- + +mzrouter +end + +#----------------------------------------------------- +# Vendor DRC rules +#----------------------------------------------------- + +drc + + style drc variants (fast),(full),(routing) + scalefactor 10 + cifstyle drc + + variants (fast),(full) + +#----------------------------- +# DNWELL +#----------------------------- + + width dnwell 3000 "Deep N-well width < %d (dnwell.2)" + spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)" + spacing dnwell allnwell 4500 surround_ok \ + "Deep N-well spacing to N-well < %d (nwell.7)" + + variants (full) + cifmaxwidth nwell_missing 0 bend_illegal \ + "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)" + cifmaxwidth dnwell_missing 0 bend_illegal \ + "SONOS nFET must be in Deep N-well (tunm.6a)" + + cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \ + "P+ diff cannot straddle Deep N-well (dnwell.5)" + variants (fast),(full) + +#----------------------------- +# NWELL +#----------------------------- + + width allnwell 840 "N-well width < %d (nwell.1)" + spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)" + + variants (full) + cifmaxwidth nwell_missing_tap 0 bend_illegal \ + "All nwells must contain metal-connected N+ taps (nwell.4)" + + cifspacing mvnwell lvnwell 2000 touching_illegal \ + "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)" + cifspacing mvnwell mvnwell 2000 touching_ok \ + "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)" + variants (fast),(full) + +#----------------------------- +# DIFF +#----------------------------- + + width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres \ + 150 "Diffusion width < %d (diff/tap.1)" + width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode,mvpdiffres 290 \ + "MV Diffusion width < %d (diff/tap.14)" + + width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)" + extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)" + extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)" + extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)" + extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)" + width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)" + spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok \ + "Diffusion spacing < %d (diff/tap.3)" + spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \ + "MV Diffusion spacing < %d (diff/tap.15a)" + spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \ + "MV Diffusion to MV tap spacing < %d (diff/tap.3)" + spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \ + touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)" + spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \ + "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)" + spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \ + "N-Diffusion spacing to N-well < %d (diff/tap.9)" + spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \ + "N-Diffusion spacing to N-well < %d (diff/tap.9)" + spacing *psd allnwell 130 touching_illegal \ + "P-tap spacing to N-well < %d (diff/tap.11)" + spacing *mvpsd allnwell 130 touching_illegal \ + "P-tap spacing to N-well < %d (diff/tap.11)" + surround *nsd allnwell 180 absence_illegal \ + "N-well overlap of N-tap < %d (diff/tap.10)" + surround *mvnsd allnwell 330 absence_illegal \ + "N-well overlap of MV N-tap < %d (diff/tap.19)" + surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \ + "N-well overlap of P-Diffusion < %d (diff/tap.8)" + surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal \ + "N-well overlap of P-Diffusion < %d (diff/tap.17)" + surround mvvar allnwell 560 absence_illegal \ + "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)" + spacing *mvndiode *mvndiode 1070 touching_ok \ + "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)" + +variants (full) + cifspacing allmvdiffnowell lvnwell 825 touching_illegal \ + "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)" +variants (fast),(full) + + spacing allnfets allpactivenonfet 270 touching_illegal \ + "nFET cannot abut P-diffusion (diff/tap.3)" + spacing allpfets allnactivenonfet 270 touching_illegal \ + "pFET cannot abut N-diffusion (diff/tap.3)" + + # Butting junction rules + edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \ + "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)" + edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \ + "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)" + edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \ + "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)" + edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \ + "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)" + + edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \ + "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)" + edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \ + "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)" + edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \ + "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)" + edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \ + "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)" + + # Sandwiched butting junction restrictions + edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)" + edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)" + + area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)" + area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)" + + angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)" + + variants (full) + cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)" + + # Latchup rules + cifmaxwidth ptap_missing 0 bend_illegal \ + "N-diff distance to P-tap must be < 15.0um (LU.2)" + cifmaxwidth dptap_missing 0 bend_illegal \ + "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)" + cifmaxwidth ntap_missing 0 bend_illegal \ + "P-diff distance to N-tap must be < 15.0um (LU.3)" + + variants (fast),(full) + +#----------------------------- +# POLY +#----------------------------- + + width allpoly 150 "poly width < %d (poly.1a)" + spacing allpoly allpoly 210 touching_ok "poly spacing < %d (poly.2)" + + spacing allpolynonfet \ + *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \ + 75 corner_ok allfets \ + "poly spacing to Diffusion < %d (poly.4)" + spacing npres *nsd 480 touching_illegal \ + "poly resistor spacing to N-tap < %d (poly.9)" + overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)" + overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \ + "N-Diffusion overhang of nFET < %d (poly.7)" + overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)" + overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (poly.7)" + overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)" + overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)" + rect_only allfets "No bends in transistors (poly.11)" + rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)" + extend xpc/a xhrpoly,uhrpoly 2160 \ + "poly contact extends poly resistor by < %d (licon.1c + li.5)" + spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \ + "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)" + + spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 780 touching_illegal \ + "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)" + spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \ + "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)" + spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 830 touching_illegal \ + "Distance from precision resistor to MV N+ diffusion < %d (rpm.3 + rpm.9)" + + angles allpoly 90 "Only 90 degree angles permitted on poly (x.2)" + +#-------------------------------------------------------------------- +# HVTP +#-------------------------------------------------------------------- + + spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,pfetlvt,pfetmvt \ + 360 touching_illegal \ + "Min. spacing between pFET and HVTP < %d (hvtp.4)" + + spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \ + "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)" + +#-------------------------------------------------------------------- +# LVTN +#-------------------------------------------------------------------- + + spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \ + allfetsnolvt 360 touching_illegal \ + "Min. spacing between FET and LVTN < %d (lvtn.3a)" + + spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \ + 740 touching_illegal \ + "Min. spacing between LVTN and HVTP < %d (lvtn.9)" + + # Spacing across S/D direction requires edge rule + edge4way allfetsnolvt allactivenonfet 415 \ + ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \ + "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)" + +#-------------------------------------------------------------------- +# NPC (Nitride poly Cut) +#-------------------------------------------------------------------- + +# Layer NPC is defined automatically around poly contacts (grow 0.1um) + +#-------------------------------------------------------------------- +# CONT (LICON, contact between poly/diff and LI) +#-------------------------------------------------------------------- + + width ndc/li 170 "N-diffusion contact width < %d (licon.1)" + width nsc/li 170 "N-tap contact width < %d (licon.1)" + width pdc/li 170 "P-diffusion contact width < %d (licon.1)" + width psc/li 170 "P-tap contact width < %d (licon.1)" + width ndic/li 170 "N-diode contact width < %d (licon.1)" + width pdic/li 170 "P-diode contact width < %d (licon.1)" + width pc/li 170 "poly contact width < %d (licon.1)" + + width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)" + area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)" + area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)" + + width mvndc/li 170 "N-diffusion contact width < %d (licon.1)" + width mvnsc/li 170 "N-tap contact width < %d (licon.1)" + width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)" + width mvpsc/li 170 "P-tap contact width < %d (licon.1)" + width mvndic/li 170 "N-diode contact width < %d (licon.1)" + width mvpdic/li 170 "P-diode contact width < %d (licon.1)" + + spacing allpdiffcont allndiffcont 170 touching_illegal \ + "Diffusion contact spacing < %d (licon.2)" + spacing allndiffcont allndiffcont 170 touching_ok \ + "Diffusion contact spacing < %d (licon.2)" + spacing allpdiffcont allpdiffcont 170 touching_ok \ + "Diffusion contact spacing < %d (licon.2)" + spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)" + + spacing pc alldiff 190 touching_illegal \ + "poly contact spacing to diffusion < %d (licon.14)" + spacing pc allpdifflv,allpdiffmv 235 touching_illegal \ + "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)" + + spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \ + "Diffusion contact to gate < %d (licon.11)" + spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \ + "Diffusion contact to standard cell gate < %d (licon.11)" + spacing ndc,pdc npd,npass,ppu 40 touching_illegal \ + "Diffusion contact to SRAM gate < %d (licon.11)" + spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \ + "Diffusion contact to gate < %d (licon.11)" + spacing nsc varactor,varhvt 250 touching_illegal \ + "Diffusion contact to varactor gate < %d (licon.10)" + spacing mvnsc mvvar 250 touching_illegal \ + "Diffusion contact to varactor gate < %d (licon.10)" + + surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \ + "N-diffusion overlap of N-diffusion contact < %d (licon.5a)" + surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \ + 40 absence_illegal \ + "P-diffusion overlap of P-diffusion contact < %d (licon.5a)" + surround ndic/a *ndi 40 absence_illegal \ + "N-diode overlap of N-diode contact < %d (licon.5a)" + surround pdic/a *pdi 40 absence_illegal \ + "P-diode overlap of N-diode contact < %d (licon.5a)" + + spacing psc/a allnactivenontap 60 touching_illegal \ + "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)" + spacing nsc/a allpactivenontap 60 touching_illegal \ + "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)" + + surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \ + "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)" + surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \ + 60 directional \ + "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)" + surround ndic/a *ndi 60 directional \ + "N-diode overlap of N-diode contact < %d in one direction (licon.5c)" + surround pdic/a *pdi 60 directional \ + "P-diode overlap of N-diode contact < %d in one direction (licon.5c)" + + surround nsc/a *nsd 120 directional \ + "N-tap overlap of N-tap contact < %d in one direction (licon.7)" + surround psc/a *psd 120 directional \ + "P-tap overlap of P-tap contact < %d in one direction (licon.7)" + + surround mvndc/a *mvndiff,mvnfet,mvrnd 40 absence_illegal \ + "N-diffusion overlap of N-diffusion contact < %d (licon.5a)" + surround mvpdc/a *mvpdiff,mvpfet,mvrpd 40 absence_illegal \ + "P-diffusion overlap of P-diffusion contact < %d (licon.5a)" + surround mvndic/a *mvndi 40 absence_illegal \ + "N-diode overlap of N-diode contact < %d (licon.5a)" + surround mvpdic/a *mvpdi 40 absence_illegal \ + "P-diode overlap of N-diode contact < %d (licon.5a)" + + spacing mvpsc/a allndiffmvnontap 60 touching_illegal \ + "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)" + spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \ + "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)" + + surround mvndc/a *mvndiff,mvnfet,mvrnd 60 directional \ + "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)" + surround mvpdc/a *mvpdiff,mvpfet,mvrpd 60 directional \ + "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)" + surround mvndic/a *mvndi 60 directional \ + "N-diode overlap of N-diode contact < %d in one direction (licon.5c)" + surround mvpdic/a *mvpdi 60 directional \ + "P-diode overlap of N-diode contact < %d in one direction (licon.5c)" + + surround mvnsc/a *mvnsd 120 directional \ + "N-tap overlap of N-tap contact < %d in one direction (licon.7)" + surround mvpsc/a *mvpsd 120 directional \ + "P-tap overlap of P-tap contact < %d in one direction (licon.7)" + + surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \ + "poly overlap of poly contact < %d (licon.8)" + surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \ + "poly overlap of poly contact < %d in one direction (licon.8a)" + + exact_overlap (allcont)/a + +#------------------------------------------------------------- +# LI - Local interconnect layer +#------------------------------------------------------------- + +variants * + + width *li 170 "Local interconnect width < %d (li.1)" + width rli 290 "Local interconnect width < %d (li.7)" + + spacing *locali,rli *locali,rli,*obsli 170 touching_ok \ + "Local interconnect spacing < %d (li.3)" + + # Local interconnect in core (SRAM) cells has more relaxed rules. There are + # no special layers for the contacts in core cells, so they must be included + # in the rule. + width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \ + "Core local interconnect width < %d (li.c1)" + + spacing coreli,pc,ndc,nsc,pdc,psc,lic allli,*obsli 140 touching_ok \ + "Core local interconnect spacing < %d (li.c2)" + + surround pc/li *li,coreli 80 directional \ + "Local interconnect overlap of poly contact < %d in one direction (li.5)" + + surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \ + *li,rli,coreli 80 directional \ + "Local interconnect overlap of diffusion contact < %d in one direction (li.5)" + + area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)" + + angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)" + angles coreli 45 \ + "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)" + +#------------------------------------------------------------- +# MCON - Contact between local interconnect and metal1 +#------------------------------------------------------------- + + width lic/m1 170 "mcon.width < %d (mcon.1)" + spacing lic/m1 lic/m1,obslic/m1 190 touching_ok "mcon.spacing < %d (mcon.2)" + + exact_overlap lic/li + +#------------------------------------------------------------- +# METAL1 - +#------------------------------------------------------------- + + width *m1,rm1 140 "Metal1 width < %d (met1.1)" + spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (met1.2)" + area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)" + + surround lic/m1 *met1 30 absence_illegal \ + "Metal1 overlap of local interconnect contact < %d (met1.4)" + surround lic/m1 *met1 60 directional \ + "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)" + + angles allm1 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)" + +variants (fast),(full) + widespacing allm1 3000 allm1,*obsm1 280 touching_ok \ + "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)" + widespacing *obsm1 3000 allm1 280 touching_ok \ + "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)" + +variants (full) + cifmaxwidth m1_hole_empty 0 bend_illegal \ + "Min area of metal1 holes > 0.14um^2 (met1.7)" + + cifspacing m1_large_halo m1_large_halo 280 touching_ok \ + "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)" +variants * + +#-------------------------------------------------- +# VIA1 +#-------------------------------------------------- + + width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)" + spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)" + surround v1/m1 *m1 30 directional \ + "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)" + surround v1/m2 *m2 30 directional \ + "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)" + + exact_overlap v1/m1 + +#-------------------------------------------------- +# METAL2 - +#-------------------------------------------------- + + width allm2 140 "Metal2 width < %d (met2.1)" + spacing allm2 allm2,obsm2 140 touching_ok "Metal2 spacing < %d (met2.2)" + area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)" + + angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)" + +variants (fast),(full) + widespacing allm2 3000 allm2,obsm2 280 touching_ok \ + "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)" + widespacing obsm2 3000 allm2 280 touching_ok \ + "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)" + +variants (full) + cifmaxwidth m2_hole_empty 0 bend_illegal \ + "Min area of metal2 holes > 0.14um^2 (met2.7)" + + cifspacing m2_large_halo m2_large_halo 280 touching_ok \ + "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)" +variants * + +#-------------------------------------------------- +# VIA2 +#-------------------------------------------------- + + width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)" + + spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)" + + surround v2/m2 *m2 45 directional \ + "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)" + surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)" + + exact_overlap v2/m2 + +#-------------------------------------------------- +# METAL3 - +#-------------------------------------------------- + + width allm3 300 "Metal3 width < %d (met3.1)" + spacing allm3 allm3,obsm3 300 touching_ok "Metal3 spacing < %d (met3.2)" + area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)" + + angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)" + +variants (fast),(full) + widespacing allm3 3000 allm3,obsm3 400 touching_ok \ + "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)" + widespacing obsm3 3000 allm3 400 touching_ok \ + "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)" +variants (full) + cifspacing m3_large_halo m3_large_halo 400 touching_ok \ + "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)" +variants * + + +#-------------------------------------------------- +# VIA3 - Requires METAL5 Module +#-------------------------------------------------- + + width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)" + spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)" + surround v3/m3 *m3 30 directional \ + "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)" + surround v3/m4 *m4 5 absence_illegal \ + "Metal4 overlap of via3.< %d (met4.3 - via3.4)" + + exact_overlap v3/m3 + +#----------------------------- +# METAL4 - METAL4 Module +#----------------------------- + +variants * + + width allm4 300 "Metal4 width < %d (met4.1)" + spacing allm4 allm4,obsm4 300 touching_ok "Metal4 spacing < %d (met4.2)" + area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)" + + angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)" + +variants (fast),(full) + widespacing allm4 3000 allm4,obsm4 400 touching_ok \ + "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)" + widespacing obsm4 3000 allm4 400 touching_ok \ + "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)" +variants (full) + cifspacing m4_large_halo m4_large_halo 400 touching_ok \ + "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)" +variants * + +#-------------------------------------------------- +# VIA4 - Requires METAL5 Module +#-------------------------------------------------- + + width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)" + spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)" + surround v4/m5 *m5 120 absence_illegal \ + "Metal5 overlap of via4.< %d (met5.3 - via4.4)" + + exact_overlap v4/m4 + +#----------------------------- +# METAL5 - METAL5 Module +#----------------------------- + + width allm5 1600 "Metal5 width < %d (met5.1)" + spacing allm5 allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (met5.2)" + area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)" + + angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)" + + + +variants (full) + + width metrdl 10000 "RDL width < %d (rdl.1)" + spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)" + surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)" + spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)" + +variants (fast),(full) + + +#-------------------------------------------------- +# NMOS, PMOS +#-------------------------------------------------- + + edge4way *poly allfetsstd 420 allfets 0 0 \ + "Transistor width < %d (diff/tap.2)" + edge4way *poly allfetsspecial 360 allfets 0 0 \ + "Transistor in standard cell width < %d (diff/tap.2)" + edge4way *poly npass,npd,nsonos 210 allfets 0 0 \ + "N-Transistor in SRAM core width < %d (diff/tap.2)" + edge4way *poly ppu 140 allfets 0 0 \ + "P-Transistor in SRAM core width < %d (diff/tap.2)" + + # Except: Note that standard cells allow transistor width minimum 0.36um + width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)" + + spacing allpolynonfet *nsd 55 corner_ok varactor \ + "poly spacing to diffusion tap < %d (poly.5)" + spacing allpolynonfet *mvnsd 55 corner_ok mvvaractor \ + "poly spacing to diffusion tap < %d (poly.5)" + + edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \ + "Butting P-tap spacing to NMOS gate < %d (poly.6)" + edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \ + "Butting N-tap spacing to PMOS gate < %d (poly.6)" + edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnnfet)/a *mvpsd 300 \ + "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)" + edge4way *mvnsd *mvpdiff 300 ~mvpfet/a *mvnsd 300 \ + "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)" + + # No LV FETs in HV diff + spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \ + "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)" + + spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \ + "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)" + + # No HV FETs in LV diff + spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal \ + "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)" + + spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal \ + "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)" + + # Minimum length of MV FETs. Note that this is larger than the minimum + # width (0.29um), so an edge rule is required + + edge4way mvndiff mvnfet 500 mvnfet 0 0 \ + "MV NMOS minimum length < %d (poly.13)" + + edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \ + "MV Varactor minimum length < %d (poly.13)" + + edge4way mvpdiff mvpfet 500 mvpfet 0 0 \ + "MV PMOS minimum length < %d (poly.13)" + +#-------------------------------------------------- +# mrp1 (N+ poly resistor) +#-------------------------------------------------- + + width mrp1 330 "mrp1 resistor width < %d (poly.3)" + +#-------------------------------------------------- +# xhrpoly (P+ poly resistor) +# uhrpoly (P+ poly resistor, 2kOhm/sq) +#-------------------------------------------------- + + # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27. + width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)" + width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)" + + spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \ + "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)" + + spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \ + "Poly resistor spacing to poly < %d (poly.9)" + + spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \ + "Poly resistor spacing to poly < %d (poly.9)" + + spacing mrp1 *poly 480 touching_ok \ + "Poly resistor spacing to poly < %d (poly.9)" + + spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \ + "Poly resistor spacing to diffusion < %d (poly.9)" + +#------------------------------------ +# nsonos +#------------------------------------ + +variants (full) + cifmaxwidth bbox_missing 0 bend_illegal \ + "SONOS transistor must be in cell with abutment box (tunm.8)" +variants (fast),(full) + +#------------------------------------ +# MOS Varactor device rules +#------------------------------------ + + overhang *nsd var,varhvt 250 \ + "N-Tap overhang of Varactor < %d (var.4)" + + overhang *mvnsd mvvar 250 \ + "N-Tap overhang of Varactor < %d (var.4)" + + width var,varhvt,mvvar 180 "Varactor length < %d (var.1)" + extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)" + +variants (full) + cifmaxwidth var_poly_no_nwell 0 bend_illegal \ + "N-well overlap of varactor poly < 0.15um (varac.5)" + + cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \ + "Varactor N-well must not contain P+ diffusion (varac.7)" +variants (fast),(full) + +#----------------------------------------------------------- +# MiM CAP (CAPM) - +#----------------------------------------------------------- + + width *mimcap 1000 "MiM cap width < %d (capm.1)" + spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)" + spacing *mimcap via3/m3 80 touching_illegal \ + "MiM cap spacing to via3 < %d (capm.5 - via3.4)" + surround *mimcc *mimcap 80 absence_illegal \ + "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)" + rect_only *mimcap "MiM cap must be rectangular (capm.7) + + surround *mimcap *metal3/m3 140 absence_illegal \ + "Metal3 must surround MiM cap by %d (capm.3)" + spacing via2 *mimcap 100 touching_illegal \ + "MiM cap spacing to via2 < %d (capm.8 - via2.4)" + spacing *mimcap *metal3/m3 500 surround_ok \ + "MiM cap spacing to unrelated metal3 < %d (capm.11)" + +variants (full) + cifspacing mim_bottom mim_bottom 1200 touching_ok \ + "MiM cap bottom plate spacing < %d (capm.2b)" +variants (fast),(full) + + # MiM cap contact rules (VIA3) + + width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)" + spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)" + surround mimcc/m4 *m4 5 directional \ + "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)" + exact_overlap mimcc/c1 + + width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)" + spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)" + spacing *mimcap2 via4/m4 10 touching_illegal \ + "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)" + surround *mim2cc *mimcap2 10 absence_illegal \ + "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)" + rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7) + + surround *mimcap2 *metal4/m4 140 absence_illegal \ + "Metal4 must surround MiM2 cap by %d (cap2m.3)" + spacing via3,mimcc *mimcap2 80 touching_illegal \ + "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)" + spacing *mimcap2 *metal4/m4 500 surround_ok \ + "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)" + +variants (full) + cifspacing mim2_bottom mim2_bottom 1200 touching_ok \ + "MiM2 cap bottom plate spacing < %d (cap2m.2b)" +variants (fast),(full) + + # MiM cap contact rules (VIA4) + + width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)" + spacing mim2cc mim2cc 420 touching_ok \ + "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)" + surround mim2cc/m5 *m5 120 absence_illegal \ + "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)" + exact_overlap mim2cc/c2 + + +#---------------------------- +# HVNTM +#---------------------------- +variants (full) + cifspacing hvntm_generate hvntm_generate 700 touching_ok \ + "HVNTM spacing < %d (hvntm.2)" +variants (fast),(full) + +#---------------------------- +# End DRC style +#---------------------------- + +end + +#---------------------------- +# LEF format definitions +#---------------------------- + +lef + + masterslice pwell pwell PWELL substrate + masterslice nwell nwell NWELL + + routing li li1 LI1 LI li + + routing m1 met1 MET1 m1 + routing m2 met2 MET2 m2 + routing m3 met3 MET3 m3 + routing m4 met4 MET4 m4 + routing m5 met5 MET5 m5 + routing mrdl met6 MET6 m6 MRDL METRDL + + cut lic mcon MCON Mcon + cut m2c via via1 VIA VIA1 cont2 via12 + cut m3c via2 VIA2 cont3 via23 + cut via3 via3 VIA3 cont4 via34 + cut via4 via4 VIA4 cont5 via45 + + obs obsli li1 + obs obsm1 met1 + obs obsm2 met2 + obs obsm3 met3 + + obs obsm4 met4 + obs obsm5 met5 + obs obsmrdl met6 + + # NOTE: obslic only used with li1, not obsli. + obs obslic mcon + + # Vias on obstruction layers should be ignored, so cast to obstruction metal. + obs obsm1 via + obs obsm2 via2 + obs obsm3 via3 + obs obsm4 via4 + +end + +#----------------------------------------------------- +# Device and Parasitic extraction +#----------------------------------------------------- + + +extract + style ngspice variants (),(orig),(si) + cscale 1 + # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all + # dimensions must be in units of microns in the extract file. + # Use extract style "ngspice(si)" to override this and produce + # a file with SI units for length/area. + + variants (),(orig) + lambda 1E6 + variants (si) + lambda 1.0 + variants * + + units microns + step 7 + sidehalo 2 + + # NOTE: MiM cap layers have been purposely put out of order, + # may want to reconsider. + + planeorder dwell 0 + planeorder well 1 + planeorder active 2 + planeorder locali 3 + planeorder metal1 4 + planeorder metal2 5 + planeorder metal3 6 + planeorder metal4 7 + planeorder metal5 8 + planeorder metali 9 + planeorder block 10 + planeorder comment 11 + planeorder cap1 12 + planeorder cap2 13 + + height dnwell -0.1 0.1 + height nwell,pwell 0.0 0.2062 + height alldiff 0.2062 0.12 + height allpoly 0.3262 0.18 + height alldiffcont 0.3262 0.61 + height pc 0.5062 0.43 + height allli 0.9361 0.10 + height lic 1.0361 0.34 + height allm1 1.3761 0.36 + height v1 1.7361 0.27 + height allm2 2.0061 0.36 + height v2 2.3661 0.42 + height allm3 2.7861 0.845 + height v3 3.6311 0.39 + height allm4 4.0211 0.845 + height v4 4.8661 0.505 + height allm5 5.3711 1.26 + height mimcap 2.4661 0.2 + height mimcap2 3.7311 0.2 + height mimcc 2.6661 0.12 + height mim2cc 3.9311 0.09 + height mrdlc 6.6311 5.2523 + height mrdl 11.8834 4.0 + + # Antenna check parameters + # Note that checks w/diode diffusion are not modeled + model partial + antenna poly sidewall 50 none + antenna allcont surface 3 none + antenna li sidewall 75 0 450 + antenna lic surface 3 0 18 + antenna m1,m2,m3 sidewall 400 2600 400 + antenna v1 surface 3 0 18 + antenna v2 surface 6 0 36 + antenna m4,m5 sidewall 400 2600 400 + antenna v3,v4 surface 6 0 36 + + tiedown alldiffnonfet + + substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell + +# Layer resistance: Use document xp018-PDS-v4_2_1.pdf + +# Resistances are in milliohms per square +# Optional 3rd argument is the corner adjustment fraction +# Device values come from trtc.cor (typical corner) + resist (dnwell)/dwell 2200000 + resist (pwell)/well 3050000 + resist (nwell)/well 1700000 + resist (rpw)/well 3050000 0.5 + resist (*ndiff,nsd)/active 120000 + resist (*pdiff,*psd)/active 197000 + resist (*mvndiff,mvnsd)/active 114000 + resist (*mvpdiff,*mvpsd)/active 191000 + + resist ndiffres/active 120000 0.5 + resist pdiffres/active 197000 0.5 + resist mvndiffres/active 114000 0.5 + resist mvpdiffres/active 191000 0.5 + resist mrp1/active 48200 0.5 + resist xhrpoly/active 319800 0.5 + resist uhrpoly/active 2000000 0.5 + + resist (allpolynonres)/active 48200 + resist rmp/active 48200 + + resist (allli)/locali 12200 + resist (allm1)/metal1 125 + resist (allm2)/metal2 125 + resist (allm3)/metal3 47 + resist (allm4)/metal4 47 + resist (allm5)/metal5 29 + resist mrdl/metali 5 + + contact ndc,nsc 15000 + contact pdc,psc 15000 + contact mvndc,mvnsc 15000 + contact mvpdc,mvpsc 15000 + contact pc 15000 + contact lic 152000 + contact m2c 4500 + contact m3c 3410 + contact mimcc 4500 + contact mim2cc 3410 + contact via3 3410 + contact via4 380 + contact mrdlc 6 + +#------------------------------------------------------------------------- +# Parasitic capacitance values: Use document (...) +#------------------------------------------------------------------------- +# This uses the new "default" definitions that determine the intervening +# planes from the planeorder stack, take care of the reflexive sideoverlap +# definitions, and generally clean up the section and make it more readable. +# +# Also uses "units microns" statement. All values are taken from the +# document PEX/xRC/cap_models. Fringe capacitance values are approximated. +# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps. +#------------------------------------------------------------------------- +# Remember that device capacitances to substrate are taken care of by the +# models. Thus, active and poly definitions ignore all "fet" types. +# fet types are excluded when computing parasitic capacitance to +# active from layers above them because poly is a shield; fet types are +# included for parasitics from layers above to poly. Resistor types +# should be removed from all parasitic capacitance calculations, or else +# they just create floating caps. Technically, the capacitance probably +# should be split between the two terminals. Unsure of the correct model. +#------------------------------------------------------------------------- + +#n-well +# NOTE: This value not found in PEX files +defaultareacap nwell well 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 22 +# defaultareacap allpolynonfet active 106 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 23 + defaultareacap *poly active nwell,obswell,pwell well 106 + defaultperimeter *poly active nwell,obswell,pwell well 55 + +#locali + defaultsidewall allli locali 33 + defaultareacap allli locali nwell,obswell,pwell well 37 + defaultperimeter allli locali nwell,obswell,pwell well 55 + defaultoverlap allli locali nwell well 37 + +#locali->diff + defaultoverlap allli locali allactivenonfet active 37 + defaultsideoverlap allli locali allactivenonfet active 55 + +#locali->poly + defaultoverlap allli locali allpolynonres active 94 + defaultsideoverlap allli locali allpolynonres active 52 + defaultsideoverlap *poly active allli locali 25 + +#metal1 + defaultsidewall allm1 metal1 45 + defaultareacap allm1 metal1 nwell,obswell,pwell well 26 + defaultperimeter allm1 metal1 nwell,obswell,pwell well 41 + defaultoverlap allm1 metal1 nwell well 26 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 26 + defaultsideoverlap allm1 metal1 allactivenonfet active 41 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 45 + defaultsideoverlap allm1 metal1 allpolynonres active 47 + defaultsideoverlap *poly active allm1 metal1 17 + +#metal1->locali + defaultoverlap allm1 metal1 allli locali 114 + defaultsideoverlap allm1 metal1 allli locali 59 + defaultsideoverlap allli locali allm1 metal1 35 + +#metal2 + defaultsidewall allm2 metal2 50 + defaultareacap allm2 metal2 nwell,obswell,pwell well 17 + defaultperimeter allm2 metal2 nwell,obswell,pwell well 41 + defaultoverlap allm2 metal2 nwell well 38 + +#metal2->diff + defaultoverlap allm2 metal2 allactivenonfet active 17 + defaultsideoverlap allm2 metal2 allactivenonfet active 41 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 24 + defaultsideoverlap allm2 metal2 allpolynonres active 41 + defaultsideoverlap *poly active allm2 metal2 11 + +#metal2->locali + defaultoverlap allm2 metal2 allli locali 38 + defaultsideoverlap allm2 metal2 allli locali 46 + defaultsideoverlap allli locali allm2 metal2 22 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 134 + defaultsideoverlap allm2 metal2 allm1 metal1 67 + defaultsideoverlap allm1 metal1 allm2 metal2 48 + +#metal3 + defaultsidewall allm3 metal3 63 + defaultoverlap allm3 metal3 nwell well 12 + defaultareacap allm3 metal3 nwell,obswell,pwell well 12 + defaultperimeter allm3 metal3 nwell,obswell,pwell well 41 + +#metal3->diff + defaultoverlap allm3 metal3 allactive active 12 + defaultsideoverlap allm3 metal3 allactive active 41 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 16 + defaultsideoverlap allm3 metal3 allpolynonres active 44 + defaultsideoverlap *poly active allm3 metal3 9 + +#metal3->locali + defaultoverlap allm3 metal3 allli locali 21 + defaultsideoverlap allm3 metal3 allli locali 47 + defaultsideoverlap allli locali allm3 metal3 15 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 35 + defaultsideoverlap allm3 metal3 allm1 metal1 55 + defaultsideoverlap allm1 metal1 allm3 metal3 27 + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 86 + defaultsideoverlap allm3 metal3 allm2 metal2 70 + defaultsideoverlap allm2 metal2 allm3 metal3 44 + +#metal4 + defaultsidewall allm4 metal4 67 +# defaultareacap alltopm metal4 well 6 + areacap allm4/m4 8 + defaultoverlap allm4 metal4 nwell well 8 + defaultperimeter allm4 metal4 well 37 + +#metal4->diff + defaultoverlap allm4 metal4 allactivenonfet active 8 + defaultsideoverlap allm4 metal4 allactivenonfet active 37 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 10 + defaultsideoverlap allm4 metal4 allpolynonres active 38 + defaultsideoverlap *poly active allm4 metal4 6 + +#metal4->locali + defaultoverlap allm4 metal4 allli locali 12 + defaultsideoverlap allm4 metal4 allli locali 40 + defaultsideoverlap allli locali allm4 metal4 10 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 15 + defaultsideoverlap allm4 metal4 allm1 metal1 43 + defaultsideoverlap allm1 metal1 allm4 metal4 16 + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 20 + defaultsideoverlap allm4 metal4 allm2 metal2 46 + defaultsideoverlap allm2 metal2 allm4 metal4 22 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 84 + defaultsideoverlap allm4 metal4 allm3 metal3 71 + defaultsideoverlap allm3 metal3 allm4 metal4 43 + +#metal5 + defaultsidewall allm5 metal5 127 +# defaultareacap allm5 metal5 well 6 + areacap allm5/m5 6 + defaultoverlap allm5 metal5 nwell well 6 + defaultperimeter allm5 metal5 well 39 + +#metal5->diff + defaultoverlap allm5 metal5 allactivenonfet active 6 + defaultsideoverlap allm5 metal5 allactivenonfet active 39 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 7 + defaultsideoverlap allm5 metal5 allpolynonres active 40 + defaultsideoverlap *poly active allm5 metal5 6 + +#metal5->locali + defaultoverlap allm5 metal5 allli locali 8 + defaultsideoverlap allm5 metal5 allli locali 41 + defaultsideoverlap allli locali allm5 metal5 8 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 9 + defaultsideoverlap allm5 metal5 allm1 metal1 43 + defaultsideoverlap allm1 metal1 allm5 metal5 12 + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 11 + defaultsideoverlap allm5 metal5 allm2 metal2 46 + defaultsideoverlap allm2 metal2 allm5 metal5 16 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 20 + defaultsideoverlap allm5 metal5 allm3 metal3 54 + defaultsideoverlap allm3 metal3 allm5 metal5 28 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 68 + defaultsideoverlap allm5 metal5 allm4 metal4 83 + defaultsideoverlap allm4 metal4 allm5 metal5 47 + + +# Devices: Base models (not subcircuit wrappers) + +variants (),(si) + + device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w + device msubcircuit sky130_fd_pr__special_pfet_pass ppu \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w + device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w + device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w + device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w + + device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w + device msubcircuit sky130_fd_pr__special_nfet_latch npd \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w + device msubcircuit sky130_fd_pr__special_nfet_pass npass \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w + device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w + device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w + device subcircuit sky130_fd_pr__cap_var_lvt varactor \ + *nndiff nwell error l=l w=w + device subcircuit sky130_fd_pr__cap_var_hvt varhvt \ + *nndiff nwell error l=l w=w + device subcircuit sky130_fd_pr__cap_var mvvaractor \ + *mvnndiff nwell error l=l w=w + + # Bipolars + device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area + device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area + device msubcircuit sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area + + # Ignore the extended-drain FET geometry that forms part of the high-voltage + # bipolar devices. + device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp + device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp + + # Extended drain devices (must appear before the regular devices) + device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error l=l w=w + device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error l=l w=w + device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \ + pwell,space/w nwell error l=l w=w + + device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \ + *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w + device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w + device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w + + device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli + device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1 + device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2 + device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3 + device resistor sky130_fd_pr__res_generic_m4 rm4 *m4 + device resistor sky130_fd_pr__res_generic_m5 rm5 *m5 + + device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \ + xpc pwell,space/w error +res0p35 l=l + device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \ + xpc pwell,space/w error +res0p69 l=l + device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \ + xpc pwell,space/w error +res1p41 l=l + device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \ + xpc pwell,space/w error +res2p85 l=l + device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \ + xpc pwell,space/w error +res5p73 l=l + device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \ + xpc pwell,space/w error l=l w=w + device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \ + xpc pwell,space/w error +res0p35 l=l + device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \ + xpc pwell,space/w error +res0p69 l=l + device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \ + xpc pwell,space/w error +res1p41 l=l + device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \ + xpc pwell,space/w error +res2p85 l=l + device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \ + xpc pwell,space/w error +res5p73 l=l + device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \ + xpc pwell,space/w error l=l w=w + + device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \ + *ndiff pwell,space/w error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \ + *pdiff nwell error l=l w=w + device rsubcircuit sky130_fd_pr__res_iso_pw rpw \ + pwell dnwell error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \ + *mvndiff pwell,space/w error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \ + *mvpdiff nwell error l=l w=w + + device resistor sky130_fd_pr__res_generic_po rmp *poly + device resistor sky130_fd_pr__res_generic_po mrp1 *poly + + device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \ + nwell a=area + device subcircuit sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \ + nwell a=area + device subcircuit sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \ + nwell a=area + device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \ + nwell a=area + + device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \ + pwell,space/w a=area + device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \ + pwell,space/w a=area + device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \ + pwell,space/w a=area + device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \ + pwell,space/w a=area + + + device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l + device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l + + variants (orig) + + device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \ + pwell,space/w + + # Note that corenvar, corepvar are not considered devices, and extract as + # parasitic capacitance instead (but cap values need to be added). + + # Extended drain devices (must appear before the regular devices) + device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error + device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error + device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \ + pwell,space/w nwell error + + device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell + device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w + device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w + + # These devices always extract as subcircuits + device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w + device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w + device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w + + device resistor sky130_fd_pr__res_generic_po rmp *poly + device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli + device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1 + device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2 + device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3 + device resistor sky130_fd_pr__res_generic_m4 rm4 *m4 + device resistor sky130_fd_pr__res_generic_m5 rm5 *m5 + + device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35 + device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69 + device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41 + device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85 + device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73 + device resistor sky130_fd_pr__res_high_po xhrpoly xpc + device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35 + device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69 + device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41 + device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85 + device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73 + device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc + device resistor sky130_fd_pr__res_generic_po mrp1 *poly + device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff + device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff + device resistor mrdn_hv mvndiffres *mvndiff + device resistor mrdp_hv mvpdiffres *mvpdiff + device resistor sky130_fd_pr__res_iso_pw rpw pwell + + device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area + device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area + device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area + device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area + + device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area + device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area + device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area + device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area + + device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area + device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area + device bjt sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area + + device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1 + device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1 + +end + +#----------------------------------------------------- +# Wiring tool definitions +#----------------------------------------------------- + +wiring + # All wiring values are in nanometers + scalefactor 10 + + contact lic 170 li 0 0 m1 30 60 + contact v1 260 m1 0 30 m2 0 30 + contact v2 280 m2 0 45 m3 25 0 + contact v3 320 m3 0 30 m4 5 5 + contact v4 1180 m4 0 m5 120 + + contact pc 170 poly 50 80 li 0 80 + contact pdc 170 pdiff 40 60 li 0 80 + contact ndc 170 ndiff 40 60 li 0 80 + contact psc 170 psd 40 60 li 0 80 + contact nsc 170 nsd 40 60 li 0 80 + +end + +#----------------------------------------------------- +# Plain old router. . . +#----------------------------------------------------- + +router +end + +#------------------------------------------------------------ +# Plowing (restored in magic 8.2, need to fill this section) +#------------------------------------------------------------ + +plowing +end + +#----------------------------------------------------------------- +# No special plot layers defined (use default PNM color choices) +#----------------------------------------------------------------- + +plot + style pnm + default + draw fillblock no_color_at_all + draw nwell cwell +end
diff --git a/Post layout simulation/AC Response/Opamp2_AC_Res.PNG b/Post layout simulation/AC Response/Opamp2_AC_Res.PNG new file mode 100644 index 0000000..8c13cbe --- /dev/null +++ b/Post layout simulation/AC Response/Opamp2_AC_Res.PNG Binary files differ
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diff --git a/Pre-layout Simulation/Screenshots of Output/Vout-AC-Phase-Res.PNG b/Pre-layout Simulation/Screenshots of Output/Vout-AC-Phase-Res.PNG new file mode 100644 index 0000000..86cf26d --- /dev/null +++ b/Pre-layout Simulation/Screenshots of Output/Vout-AC-Phase-Res.PNG Binary files differ
diff --git a/Pre-layout Simulation/Screenshots of Output/Vout-tran.PNG b/Pre-layout Simulation/Screenshots of Output/Vout-tran.PNG new file mode 100644 index 0000000..9654b9d --- /dev/null +++ b/Pre-layout Simulation/Screenshots of Output/Vout-tran.PNG Binary files differ
diff --git a/Pre-layout Simulation/Screenshots of Output/vout-ac-magres.PNG b/Pre-layout Simulation/Screenshots of Output/vout-ac-magres.PNG new file mode 100644 index 0000000..9b1c609 --- /dev/null +++ b/Pre-layout Simulation/Screenshots of Output/vout-ac-magres.PNG Binary files differ
diff --git a/Pre-layout Simulation/Screenshots of Output/vout-ac-phres.PNG b/Pre-layout Simulation/Screenshots of Output/vout-ac-phres.PNG new file mode 100644 index 0000000..5e10573 --- /dev/null +++ b/Pre-layout Simulation/Screenshots of Output/vout-ac-phres.PNG Binary files differ
diff --git "a/Pre-layout Simulation/Screenshots of Output/vout-ac-pm \0502\051.PNG" "b/Pre-layout Simulation/Screenshots of Output/vout-ac-pm \0502\051.PNG" new file mode 100644 index 0000000..63aadae --- /dev/null +++ "b/Pre-layout Simulation/Screenshots of Output/vout-ac-pm \0502\051.PNG" Binary files differ
diff --git a/Pre-layout Simulation/ngspice files/Opamp_AC.cir.out b/Pre-layout Simulation/ngspice files/Opamp_AC.cir.out new file mode 100644 index 0000000..0108be3 --- /dev/null +++ b/Pre-layout Simulation/ngspice files/Opamp_AC.cir.out
@@ -0,0 +1,46 @@ +* D:\CMOS_OPAMP_Project\Diff_amp\Diff_amp_Opamp.cir + +.lib "sky130_fd_pr/models/sky130.lib.spice" tt + +* Sheet Name: / +xM1 Net-_M1-Pad1_ vbias vdd vdd sky130_fd_pr__pfet_01v8 w=20 l=1 +xM4 Net-_M2-Pad1_ Net-_M2-Pad1_ vss vss sky130_fd_pr__nfet_01v8 w=20 l=1 +xM2 Net-_M2-Pad1_ vinp Net-_M1-Pad1_ Net-_M1-Pad1_ sky130_fd_pr__pfet_01v8 w=50 l=1 +xM3 vo vinm Net-_M1-Pad1_ Net-_M1-Pad1_ sky130_fd_pr__pfet_01v8 w=50 l=1 +xM5 vo Net-_M2-Pad1_ vss vss sky130_fd_pr__nfet_01v8 w=20 l=1 + +R1 vo Net-_C1-Pad2_ 290 +C1 vout Net-_C1-Pad2_ 3.2p +xM6 vout vbias vdd vdd sky130_fd_pr__pfet_01v8 w=20 l=1 +xM7 vout vo GND GND sky130_fd_pr__nfet_01v8 w=50 l=1 +CL vout GND 14p + +******* DC supply info****** +VDD vdd GND 5 +VSS vss GND 0 +VBIAS vbias 0 3.9 + +*******Transient analysis AC Source******** +*VINP vinp 0 SIN(3.9 1m 10k 0 0 0) +*VINM vinm 0 SIN(3.9 1m 10k 0 0 180) + +*******AC analysis AC Source****** +VINP vinp 0 dc 3.9 ac 1 +VINM vinm 0 dc 3.9 ac -1 + +******AC Command***** +ac dec 100 1 1000meg +*Magnitude dB plot for v(vout) on log scale +plot vdb(vout) xlog + +*Phase degrees plot for v(vout) on log scale +let outd = 57.29*vp(vout) +settype phase outd +plot outd xlimit 1 1000meg ylabel 'phase' +let pm = outd + 180 +settype phase pm +plot pm xlimit 1 1000meg ylabel 'Phase Margin' + +.endc + +.end
diff --git a/Pre-layout Simulation/ngspice files/Opamp_TRAN.cir.out b/Pre-layout Simulation/ngspice files/Opamp_TRAN.cir.out new file mode 100644 index 0000000..20f540f --- /dev/null +++ b/Pre-layout Simulation/ngspice files/Opamp_TRAN.cir.out
@@ -0,0 +1,44 @@ + + +.lib "sky130_fd_pr/models/sky130.lib.spice" tt + +* Sheet Name: / +xM1 Net-_M1-Pad1_ vbias vdd vdd sky130_fd_pr__pfet_01v8 w=20 l=1 +xM4 Net-_M2-Pad1_ Net-_M2-Pad1_ vss vss sky130_fd_pr__nfet_01v8 w=20 l=1 +xM2 Net-_M2-Pad1_ vinp Net-_M1-Pad1_ Net-_M1-Pad1_ sky130_fd_pr__pfet_01v8 w=50 l=1 +xM3 vo vinm Net-_M1-Pad1_ Net-_M1-Pad1_ sky130_fd_pr__pfet_01v8 w=50 l=1 +xM5 vo Net-_M2-Pad1_ vss vss sky130_fd_pr__nfet_01v8 w=20 l=1 + +R1 vo Net-_C1-Pad2_ 290 +C1 vout Net-_C1-Pad2_ 3.2p +xM6 vout vbias vdd vdd sky130_fd_pr__pfet_01v8 w=20 l=1 +xM7 vout vo GND GND sky130_fd_pr__nfet_01v8 w=50 l=1 +CL vout GND 14p + +******* DC supply info****** +VDD vdd GND 5 +VSS vss GND 0 +VBIAS vbias 0 3.9 + +*******Transient analysis AC Source******** +VINP vinp 0 SIN(3.9 1m 10k 0 0 0) +VINM vinm 0 SIN(3.9 1m 10k 0 0 180) + +*******AC analysis AC Source****** +*VINP vinp 0 dc 3.9 ac 1 +*VINM vinm 0 dc 3.9 ac -1 + +*******Tran command******* +.tran 0.1us 1000us +********Transient Plot ****** +.control +run +plot V(vinp) V(vinm) +plot V(vout) +plot V(vo) +plot V(vdd) V(vbias) + + +.endc + +.end
