| /root/two_stage_cmos_operational_amplifier/Makefile |
| /root/two_stage_cmos_operational_amplifier/docs/environment.yml |
| /root/two_stage_cmos_operational_amplifier/docs/Makefile |
| /root/two_stage_cmos_operational_amplifier/docs/source/index.rst |
| /root/two_stage_cmos_operational_amplifier/docs/source/conf.py |
| /root/two_stage_cmos_operational_amplifier/post_layout/post_layout_simulation/differential_gain.cir |
| /root/two_stage_cmos_operational_amplifier/post_layout/post_layout_simulation/offset_voltage.cir |
| /root/two_stage_cmos_operational_amplifier/post_layout/post_layout_simulation/transient.cir |
| /root/two_stage_cmos_operational_amplifier/post_layout/post_layout_simulation/common_mode_gain.cir |
| /root/two_stage_cmos_operational_amplifier/post_layout/post_layout_simulation/input_noise_spectrum.cir |
| /root/two_stage_cmos_operational_amplifier/post_layout/post_layout_simulation/power_dissipation.cir |
| /root/two_stage_cmos_operational_amplifier/post_layout/post_layout_simulation/slew_rate.cir |
| /root/two_stage_cmos_operational_amplifier/post_layout/post_layout_simulation/circuit.cir |
| /root/two_stage_cmos_operational_amplifier/verilog/dv/Makefile |
| /root/two_stage_cmos_operational_amplifier/verilog/dv/mprj_por/mprj_por_tb.v |
| /root/two_stage_cmos_operational_amplifier/verilog/dv/mprj_por/Makefile |
| /root/two_stage_cmos_operational_amplifier/verilog/dv/mprj_por/mprj_por.c |
| /root/two_stage_cmos_operational_amplifier/verilog/rtl/example_por.v |
| /root/two_stage_cmos_operational_amplifier/verilog/rtl/uprj_analog_netlists.v |
| /root/two_stage_cmos_operational_amplifier/verilog/rtl/user_analog_proj_example.v |
| /root/two_stage_cmos_operational_amplifier/verilog/rtl/user_analog_project_wrapper.v |
| /root/two_stage_cmos_operational_amplifier/xschem/xschemrc |
| /root/two_stage_cmos_operational_amplifier/xschem/example_por.sch |
| /root/two_stage_cmos_operational_amplifier/xschem/example_por.sym |
| /root/two_stage_cmos_operational_amplifier/xschem/example_por_tb.spice.orig |
| /root/two_stage_cmos_operational_amplifier/xschem/test.data |
| /root/two_stage_cmos_operational_amplifier/xschem/user_analog_project_wrapper.sym |
| /root/two_stage_cmos_operational_amplifier/xschem/example_por_tb.sch |
| /root/two_stage_cmos_operational_amplifier/xschem/user_analog_project_wrapper.sch |
| /root/two_stage_cmos_operational_amplifier/xschem/analog_wrapper_tb.sch |
| /root/two_stage_cmos_operational_amplifier/xschem/.spiceinit |
| /root/two_stage_cmos_operational_amplifier/layout_design/avsd_opamp_layout.ext |
| /root/two_stage_cmos_operational_amplifier/openlane/Makefile |
| /root/two_stage_cmos_operational_amplifier/netgen/run_lvs_wrapper_verilog.sh |
| /root/two_stage_cmos_operational_amplifier/netgen/run_lvs_por.sh |
| /root/two_stage_cmos_operational_amplifier/netgen/run_lvs_wrapper_xschem.sh |
| /root/two_stage_cmos_operational_amplifier/pre_layout/schematics/avsd_opamp_eSim_project/avsd_opamp.cir |
| /root/two_stage_cmos_operational_amplifier/pre_layout/schematics/avsd_opamp_eSim_project/avsd_opamp.pro |
| /root/two_stage_cmos_operational_amplifier/pre_layout/schematics/avsd_opamp_eSim_project/avsd_opamp.proj |
| /root/two_stage_cmos_operational_amplifier/pre_layout/schematics/avsd_opamp_eSim_project/avsd_opamp.sch |
| /root/two_stage_cmos_operational_amplifier/pre_layout/pre_layout_simulation/differential_gain.cir |
| /root/two_stage_cmos_operational_amplifier/pre_layout/pre_layout_simulation/offset_voltage.cir |
| /root/two_stage_cmos_operational_amplifier/pre_layout/pre_layout_simulation/transient.cir |
| /root/two_stage_cmos_operational_amplifier/pre_layout/pre_layout_simulation/common_mode_gain.cir |
| /root/two_stage_cmos_operational_amplifier/pre_layout/pre_layout_simulation/input_noise_spectrum.cir |
| /root/two_stage_cmos_operational_amplifier/pre_layout/pre_layout_simulation/power_dissipation.cir |
| /root/two_stage_cmos_operational_amplifier/pre_layout/pre_layout_simulation/slew_rate.cir |
| /root/two_stage_cmos_operational_amplifier/pre_layout/pre_layout_simulation/circuit.cir |
