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docs/source/index.rst

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@@ -318,6 +318,8 @@
 
 |:heavy_check_mark:| Full Chip Simulation passes for RTL and GL (gate-level)
 
+|:heavy_check_mark:| The project contains a spice netlist for the ``user_analog_project_wrapper`` at netgen/user_analog_project_wrapper.spice
+
 |:heavy_check_mark:| The hardened Macros are LVS and DRC clean
 
 |:heavy_check_mark:| The ``user_analog_project_wrapper`` adheres to empty wrapper template  order specified at  `user_analog_project_wrapper_empty <https://github.com/efabless/caravel/blob/master/mag/user_analog_project_wrapper_empty.mag>`__

gds/user_analog_project_wrapper.gds

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deleted file mode 100644
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