commit	984718db4d117ff4638eb4ca1730b003042e013c	[log] [tgz]
author	H-S-S-11 <harry@snell.org.uk>	Sun Oct 10 12:14:45 2021 +0100
committer	H-S-S-11 <harry@snell.org.uk>	Sun Oct 10 12:14:45 2021 +0100
tree	d3ba9cedca997d34d7f2a02c54c990cbefb12015
parent	617df52767df4ee38b24c7122100444bb6506b10 [diff]

clean up and set up verilog simulation

verilog/dv/Makefile[diff]
verilog/dv/README.md[diff]
verilog/dv/comparator/Makefile[diff]
verilog/dv/comparator/comparator.hex[Renamed from verilog/dv/comparator/mprj_por.hex - diff]
verilog/dv/comparator/comparator_tb.v[Renamed from verilog/dv/comparator/comparator.v - diff]
verilog/rtl/example_por.v[Deleted - diff]
verilog/rtl/uprj_analog_netlists.v[diff]
verilog/rtl/user_analog_proj_example.v[Deleted - diff]
verilog/rtl/user_analog_project_wrapper.v[diff]

9 files changed

tree: d3ba9cedca997d34d7f2a02c54c990cbefb12015

README.md

Caravel Analog User

Mixed signal tests

Collection of analog and mixed signal test circuits.

Basic goal: a comparator based on the circuit in “CMOS Design” (Jacob Baker).

Extra goals:

A small array (eg 1x8) of Flash cells for characterisation
An alternative comparator layout using only self-biased amplifiers (no bias voltage required)
The digital section of delta-sigma ADC
Demo charge pump
Sample-and-hold circuit

Refer to README for the sample project documentation.