commit 617df52767df4ee38b24c7122100444bb6506b10
author H-S-S-11 <harry@snell.org.uk> Sat Oct 09 17:14:30 2021 +0100
committer H-S-S-11 <harry@snell.org.uk> Sat Oct 09 17:14:30 2021 +0100
tree f69c1f277451956f158f4f5c21b128e6d8ed584d
parent d60d38d5880691736463a3ed66b77ebc9ad291f7

rename testbench

verilog/dv/comparator/Makefile

diff --git a/verilog/dv/mprj_por/Makefile b/verilog/dv/comparator/Makefile
similarity index 100%
rename from verilog/dv/mprj_por/Makefile
rename to verilog/dv/comparator/Makefile

verilog/dv/comparator/comparator.c

diff --git a/verilog/dv/mprj_por/mprj_por.c b/verilog/dv/comparator/comparator.c
similarity index 100%
rename from verilog/dv/mprj_por/mprj_por.c
rename to verilog/dv/comparator/comparator.c

verilog/dv/comparator/comparator.v

diff --git a/verilog/dv/mprj_por/mprj_por_tb.v b/verilog/dv/comparator/comparator.v
similarity index 98%
rename from verilog/dv/mprj_por/mprj_por_tb.v
rename to verilog/dv/comparator/comparator.v
index 39e4a36..d038cff 100644
--- a/verilog/dv/mprj_por/mprj_por_tb.v
+++ b/verilog/dv/comparator/comparator.v
@@ -22,7 +22,7 @@
 `include "spiflash.v"
 `include "tbuart.v"
 
-module mprj_por_tb;
+module comparator_tb;
     // Signals declaration
     reg clock;
     reg RSTB;

verilog/dv/comparator/mprj_por.hex

diff --git a/verilog/dv/mprj_por/mprj_por.hex b/verilog/dv/comparator/mprj_por.hex
similarity index 100%
rename from verilog/dv/mprj_por/mprj_por.hex
rename to verilog/dv/comparator/mprj_por.hex