| v {xschem version=2.9.9 file_version=1.2 } |
| G {} |
| K {} |
| V {} |
| S {} |
| E {} |
| T {140mA} 1790 -160 0 0 0.2 0.2 {} |
| T {140mA} 1790 80 0 0 0.2 0.2 {} |
| N -380 50 -380 80 { lab=vref} |
| N -380 140 -380 180 { lab=GND} |
| N 550 -450 920 -450 { lab=feedback_p} |
| N 420 -270 470 -270 { lab=vin_p} |
| N 1080 -310 1080 -280 { lab=vdd} |
| N 1080 -240 1080 -210 { lab=GND} |
| N 420 110 470 110 { lab=vin_n} |
| N 1070 90 1070 120 { lab=vdd} |
| N 1070 160 1070 190 { lab=GND} |
| N 1960 -260 2040 -260 { lab=audio_p} |
| N 1980 -260 1980 -250 { lab=audio_p} |
| N 1980 -190 1980 -170 { lab=GND} |
| N 1980 210 1980 230 { lab=GND} |
| N 400 -270 420 -270 { lab=vin_p} |
| N 1120 140 1130 140 { lab=vcmp_n} |
| N -290 50 -290 80 { lab=vdd} |
| N -290 140 -290 170 { lab=GND} |
| N 1280 -320 1280 -300 { lab=vdd} |
| N 1280 -220 1280 -200 { lab=GND} |
| N 1280 80 1280 100 { lab=vdd} |
| N 1280 180 1280 200 { lab=GND} |
| N 1130 140 1150 140 { lab=vcmp_n} |
| N 1950 150 1980 150 { lab=audio_n} |
| N 2040 -260 2040 -50 { lab=audio_p} |
| N 2040 -50 2040 -40 { lab=audio_p} |
| N 2040 20 2040 150 { lab=audio_n} |
| N 1980 150 2040 150 { lab=audio_n} |
| N 740 -120 950 -120 { lab=vtriang} |
| N -80 -70 80 -70 { lab=#net1} |
| N 90 -50 120 -50 { lab=vref} |
| N 90 -70 120 -70 { lab=#net1} |
| N 240 -140 240 -120 { lab=vdd} |
| N 240 -40 240 -20 { lab=GND} |
| N 550 -450 550 -290 { lab=feedback_p} |
| N 470 -290 470 -270 { lab=vin_p} |
| N 530 -290 550 -290 { lab=feedback_p} |
| N 530 110 550 110 { lab=feedback_n} |
| N 1130 -260 1150 -260 { lab=vcmp_p} |
| N 800 -220 800 -210 { lab=GND} |
| N 580 -110 610 -110 { lab=vbias2} |
| N 580 -90 610 -90 { lab=vref} |
| N 740 -90 790 -90 { lab=vsquare} |
| N 560 360 940 360 { lab=feedback_n} |
| N 560 110 560 360 { lab=feedback_n} |
| N -80 -10 -80 10 { lab=GND} |
| N 70 300 70 380 { lab=v1} |
| N 70 330 140 330 { lab=v1} |
| N 70 220 70 240 { lab=vdd} |
| N 70 440 70 450 { lab=GND} |
| N 70 410 70 440 { lab=GND} |
| N 110 410 150 410 { lab=v1} |
| N 140 330 140 410 { lab=v1} |
| N 150 410 190 410 { lab=v1} |
| N 190 410 630 410 { lab=v1} |
| N 220 450 250 450 { lab=GND} |
| N 400 450 430 450 { lab=GND} |
| N 570 450 600 450 { lab=GND} |
| N 240 450 240 480 { lab=GND} |
| N 420 450 420 480 { lab=GND} |
| N 580 450 580 480 { lab=GND} |
| N 190 450 220 450 { lab=GND} |
| N 250 450 280 450 { lab=GND} |
| N 370 450 400 450 { lab=GND} |
| N 430 450 460 450 { lab=GND} |
| N 540 450 570 450 { lab=GND} |
| N 600 450 630 450 { lab=GND} |
| N 630 410 790 410 { lab=v1} |
| N 740 450 760 450 { lab=GND} |
| N 750 450 750 480 { lab=GND} |
| N 760 450 790 450 { lab=GND} |
| N 710 450 740 450 { lab=GND} |
| N 980 -450 1580 -450 { lab=out_p} |
| N 1000 360 1570 360 { lab=out_n} |
| N 580 -130 610 -130 { lab=vbias1} |
| N 80 -70 90 -70 { lab=#net1} |
| N 90 -90 120 -90 { lab=vbias4} |
| N 90 -110 120 -110 { lab=vbias3} |
| N 160 450 160 500 { lab=vbias1} |
| N 310 450 310 500 { lab=vbias2} |
| N 340 450 340 500 { lab=vbias3} |
| N 490 450 490 500 { lab=vbias4} |
| N 510 450 510 500 { lab=vbias5} |
| N 660 450 660 500 { lab=vbias6} |
| N 680 450 680 500 { lab=vbias7} |
| N 820 450 820 500 { lab=vbias8} |
| N 470 -180 470 -150 { lab=#net2} |
| N 470 -180 670 -180 { lab=#net2} |
| N 670 -180 670 -160 { lab=#net2} |
| N 670 -160 670 -150 { lab=#net2} |
| N 470 -90 470 -70 { lab=GND} |
| N 400 110 420 110 { lab=vin_n} |
| N 360 -270 360 -90 { lab=vin_p} |
| N 360 -270 400 -270 { lab=vin_p} |
| N 360 -70 360 110 { lab=vin_n} |
| N 360 110 400 110 { lab=vin_n} |
| N 1770 350 1770 360 { lab=out_n} |
| N 1570 360 1770 360 { lab=out_n} |
| N 1580 -450 1770 -450 { lab=out_p} |
| N 1410 130 1440 130 { lab=vn_p} |
| N 1440 -40 1440 130 { lab=vn_p} |
| N 1440 -40 1470 -40 { lab=vn_p} |
| N 1400 150 1470 150 { lab=vn_n} |
| N 1470 -20 1470 150 { lab=vn_n} |
| N 1400 -270 1460 -270 { lab=vp_p} |
| N 1460 -270 1470 -270 { lab=vp_p} |
| N 1470 -270 1470 -80 { lab=vp_p} |
| N 1400 -250 1430 -250 { lab=vp_n} |
| N 1430 -250 1430 -60 { lab=vp_n} |
| N 1430 -60 1470 -60 { lab=vp_n} |
| N 1530 -230 1530 -180 { lab=GND} |
| N 1530 -330 1530 -290 { lab=#net3} |
| N 1530 -330 1590 -330 { lab=#net3} |
| N 1770 150 1890 150 { lab=out_n} |
| N 1770 -260 1900 -260 { lab=out_p} |
| N 1400 130 1410 130 { lab=vn_p} |
| N 550 110 560 110 { lab=feedback_n} |
| N 800 -370 800 -320 { lab=vdd} |
| N 800 -260 800 -220 { lab=GND} |
| N 630 -270 650 -270 { lab=vref} |
| N 550 -310 600 -310 { lab=feedback_p} |
| N 600 -310 650 -310 { lab=feedback_p} |
| N 630 -290 650 -290 { lab=vbias5} |
| N 950 -290 970 -290 { lab=error_p} |
| N 970 -290 970 -280 { lab=error_p} |
| N 970 -280 1020 -280 { lab=error_p} |
| N 950 -260 1020 -260 { lab=vtriang} |
| N 950 -260 950 -120 { lab=vtriang} |
| N 970 -240 1020 -240 { lab=vbias7} |
| N 670 -70 670 -30 { lab=GND} |
| N 800 60 800 100 { lab=vdd} |
| N 800 160 800 180 { lab=GND} |
| N 560 110 650 110 { lab=feedback_n} |
| N 610 130 650 130 { lab=vbias6} |
| N 610 150 650 150 { lab=vref} |
| N 980 160 1010 160 { lab=vbias8} |
| N 950 120 950 130 { lab=error_n} |
| N 950 120 1010 120 { lab=error_n} |
| N 950 -120 950 90 { lab=vtriang} |
| N 950 90 990 90 { lab=vtriang} |
| N 990 90 990 140 { lab=vtriang} |
| N 990 140 1010 140 { lab=vtriang} |
| N 1600 -330 1600 -100 { lab=#net3} |
| N 1590 -330 1600 -330 { lab=#net3} |
| N 1630 -330 1630 -100 { lab=#net3} |
| N 1600 -330 1630 -330 { lab=#net3} |
| N 1620 0 1620 40 { lab=GND} |
| N 1770 100 1770 150 { lab=out_n} |
| N 1770 -40 1770 40 { lab=#net4} |
| N 1770 -150 1770 -60 { lab=#net5} |
| N 1770 -260 1770 -210 { lab=out_p} |
| N 1770 150 1770 350 { lab=out_n} |
| N 1770 -450 1770 -260 { lab=out_p} |
| C {vsource.sym} -80 -40 0 0 {name=V1 value="sin(0.9 0.8 5k)"} |
| C {code_shown.sym} -1130 -450 0 0 {name=s2 only_toplevel=false value=" |
| .option rshunt=1e20 |
| .nodeset V(audio_p)=0.9 V(audio_n)=0.9 V(vp_p)=0.79 V(vn_p)=0 V(vcmp_p)=0.859 |
| + V(vp_n)=0.79 V(vn_n)=0 V(vcmp_n)=0.859 v(vin_p)=0.9 v(vin_n)=0.9 v(vtriang)=0.9 |
| *.nodeset all=0.9 |
| *.option VNTOL=1e-6 ABSTOL=1e-9 |
| *.option savecurrents |
| *set the absolute voltage error tolerance and absolute current error tolerance |
| .control |
| save out_p out_n audio_p audio_n I(V4) I(V2) @r6[i] @r1[i] i(v3) i(v6) vtriang vin_p vin_n error_p error_n vcmp_p vcmp_n vp_p vp_n vn_p vn_n i(v7) |
| *save vtriang audio_p audio_n I(V2) @r6[i] out_p out_n |
| *op |
| tran 3n 10m |
| *linearize V(audio) |
| *linearize V(out) |
| *fft V(out) |
| *fft V(audio) |
| *plot mag(V(audio)) |
| *plot mag(V(out)) |
| let pout=@r6[i]*(V(audio_p)-V(audio_n)) |
| let pin=1.8*(I(V4)+I(V2)+I(V3)) |
| meas tran pload avg pout from=2m to=9m |
| meas tran p_supply avg pin from=2m to=9m |
| *print pload/p_supply |
| set nfreqs=20 |
| *fourier 10k V(out_p)-V(out_n) |
| |
| fourier 5k V(audio_p)-V(audio_n) |
| write class_d_5k_08_output_current_test.raw |
| |
| .endc |
| |
| |
| "} |
| C {netlist_not_shown.sym} -310 -140 0 0 {name=TT_MODELS1 |
| spice_ignore=false |
| only_toplevel=true |
| format="tcleval( @value )" |
| value=" |
| .include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice |
| .include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice |
| .include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice |
| .include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_post.spice |
| .include /home/eda/magic/class_d_audio_amplifier/triang/triangle_post.spice |
| .include /home/eda/magic/class_d_audio_amplifier/comparator/comparator_post.spice |
| .include /home/eda/magic/class_d_audio_amplifier/dead_time/dead_time_post.spice |
| .include /home/eda/magic/class_d_audio_amplifier/output_driver/output_driver_post.spice |
| * Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor |
| .include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice |
| .include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice |
| * Special cells |
| .include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice |
| |
| " |
| } |
| C {lab_wire.sym} 870 -120 0 0 {name=l9 sig_type=std_logic lab=vtriang} |
| C {vsource.sym} -380 110 0 0 {name=V5 value=0.9} |
| C {lab_wire.sym} -380 70 0 0 {name=l26 sig_type=std_logic lab=vref} |
| C {lab_wire.sym} 420 -270 0 1 {name=l1 sig_type=std_logic lab=vin_p} |
| C {lab_wire.sym} 800 -350 0 0 {name=l6 sig_type=std_logic lab=vdd} |
| C {ind.sym} 1930 -260 1 0 {name=L1 |
| m=1 |
| value=28u |
| footprint=1206 |
| device=inductor} |
| C {capa.sym} 1980 -220 0 0 {name=C1 |
| m=1 |
| value=1.3u |
| footprint=1206 |
| device="ceramic capacitor"} |
| C {res.sym} 950 -450 1 0 {name=R1 |
| value=200k |
| footprint=1206 |
| device=resistor |
| m=1} |
| C {res.sym} 500 -290 1 0 {name=R3 |
| value=200k |
| footprint=1206 |
| device=resistor |
| m=1} |
| C {lab_wire.sym} 550 -360 0 0 {name=l18 sig_type=std_logic lab=feedback_p} |
| C {lab_wire.sym} 1140 -260 0 0 {name=l19 sig_type=std_logic lab=vcmp_p} |
| C {lab_wire.sym} 1080 -300 0 0 {name=l21 sig_type=std_logic lab=vdd} |
| C {lab_wire.sym} 1000 -280 0 0 {name=l8 sig_type=std_logic lab=error_p} |
| C {lab_wire.sym} 800 80 0 0 {name=l24 sig_type=std_logic lab=vdd} |
| C {lab_wire.sym} 630 150 0 0 {name=l27 sig_type=std_logic lab=vref} |
| C {res.sym} 970 360 1 0 {name=R4 |
| value=200k |
| footprint=1206 |
| device=resistor |
| m=1} |
| C {res.sym} 500 110 1 0 {name=R5 |
| value=200k |
| footprint=1206 |
| device=resistor |
| m=1} |
| C {lab_wire.sym} 1070 100 0 0 {name=l38 sig_type=std_logic lab=vdd} |
| C {ind.sym} 1920 150 3 1 {name=L2 |
| m=1 |
| value=28u |
| footprint=1206 |
| device=inductor} |
| C {capa.sym} 1980 180 0 1 {name=C4 |
| m=1 |
| value=1.3u |
| footprint=1206 |
| device="ceramic capacitor"} |
| C {res.sym} 2040 -10 2 0 {name=R6 |
| value=8 |
| footprint=1206 |
| device=resistor |
| m=1} |
| C {lab_wire.sym} 960 120 0 0 {name=l29 sig_type=std_logic lab=error_n} |
| C {lab_wire.sym} 560 190 0 0 {name=l30 sig_type=std_logic lab=feedback_n} |
| C {lab_wire.sym} 1130 140 0 1 {name=l40 sig_type=std_logic lab=vcmp_n} |
| C {lab_wire.sym} 1990 -260 0 1 {name=l43 sig_type=std_logic lab=audio_p} |
| C {lab_wire.sym} 1990 150 0 1 {name=l44 sig_type=std_logic lab=audio_n} |
| C {vsource.sym} -290 110 0 0 {name=V4 value="pulse(0 1.8 0 10n 10n 10 20)"} |
| C {lab_wire.sym} -290 60 0 0 {name=l16 sig_type=std_logic lab=vdd} |
| C {lab_wire.sym} 1280 -320 0 0 {name=l17 sig_type=std_logic lab=vdd} |
| C {lab_wire.sym} 1280 80 0 0 {name=l34 sig_type=std_logic lab=vdd} |
| C {lab_wire.sym} 1430 130 0 0 {name=l51 sig_type=std_logic lab=vn_p} |
| C {lab_wire.sym} 1440 150 0 0 {name=l52 sig_type=std_logic lab=vn_n} |
| C {lab_wire.sym} 110 -110 0 0 {name=l36 sig_type=std_logic lab=vbias3} |
| C {lab_wire.sym} 110 -50 0 0 {name=l56 sig_type=std_logic lab=vref} |
| C {lab_wire.sym} 240 -130 0 0 {name=l57 sig_type=std_logic lab=vdd} |
| C {lab_wire.sym} 640 -290 0 0 {name=l3 sig_type=std_logic lab=vbias5} |
| C {lab_wire.sym} 630 130 0 0 {name=l14 sig_type=std_logic lab=vbias6} |
| C {lab_wire.sym} 1010 -240 0 0 {name=l20 sig_type=std_logic lab=vbias7} |
| C {lab_wire.sym} 590 -110 0 0 {name=l45 sig_type=std_logic lab=vbias2} |
| C {lab_wire.sym} 590 -90 0 0 {name=l46 sig_type=std_logic lab=vref} |
| C {lab_wire.sym} 750 -90 0 1 {name=l60 sig_type=std_logic lab=vsquare} |
| C {lab_wire.sym} 990 160 0 0 {name=l61 sig_type=std_logic lab=vbias8} |
| C {gnd.sym} -290 170 0 0 {name=l63 lab=GND} |
| C {gnd.sym} -380 180 0 0 {name=l2 lab=GND} |
| C {gnd.sym} -80 10 0 0 {name=l4 lab=GND} |
| C {gnd.sym} 240 -20 0 0 {name=l5 lab=GND} |
| C {gnd.sym} 800 -210 0 0 {name=l11 lab=GND} |
| C {gnd.sym} 1080 -210 0 0 {name=l13 lab=GND} |
| C {gnd.sym} 1280 -200 0 0 {name=l22 lab=GND} |
| C {gnd.sym} 1280 200 0 0 {name=l41 lab=GND} |
| C {gnd.sym} 1070 190 0 0 {name=l42 lab=GND} |
| C {gnd.sym} 800 180 0 0 {name=l48 lab=GND} |
| C {gnd.sym} 1980 230 0 0 {name=l55 lab=GND} |
| C {gnd.sym} 1980 -170 0 0 {name=l58 lab=GND} |
| C {isource.sym} 70 270 0 0 {name=I0 value=15u} |
| C {lab_wire.sym} 70 220 0 0 {name=l53 sig_type=std_logic lab=vdd} |
| C {gnd.sym} 70 450 0 0 {name=l10 lab=GND} |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 90 410 0 1 {name=M5 |
| L=2 |
| W=4 |
| nf=2 |
| mult=8 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 190 430 3 1 {name=M6 |
| L=2 |
| W=4 |
| nf=2 |
| mult=8 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {lab_wire.sym} 120 330 0 1 {name=l62 sig_type=std_logic lab=v1} |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 280 430 1 0 {name=M7 |
| L=2 |
| W=4 |
| nf=2 |
| mult=8 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 370 430 3 1 {name=M8 |
| L=2 |
| W=4 |
| nf=2 |
| mult=8 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 460 430 1 0 {name=M9 |
| L=2 |
| W=4 |
| nf=2 |
| mult=8 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 540 430 3 1 {name=M10 |
| L=2 |
| W=4 |
| nf=2 |
| mult=8 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 630 430 1 0 {name=M11 |
| L=2 |
| W=4 |
| nf=2 |
| mult=8 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {gnd.sym} 240 480 0 0 {name=l54 lab=GND} |
| C {gnd.sym} 420 480 0 0 {name=l59 lab=GND} |
| C {gnd.sym} 580 480 0 0 {name=l64 lab=GND} |
| C {gnd.sym} 750 480 0 0 {name=l65 lab=GND} |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 710 430 1 0 {name=M12 |
| L=2 |
| W=4 |
| nf=2 |
| mult=8 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 790 430 1 0 {name=M13 |
| L=2 |
| W=4 |
| nf=2 |
| mult=8 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {lab_wire.sym} 590 -130 0 0 {name=l32 sig_type=std_logic lab=vbias1} |
| C {lab_wire.sym} 110 -90 0 0 {name=l35 sig_type=std_logic lab=vbias4} |
| C {lab_wire.sym} 160 490 0 0 {name=l39 sig_type=std_logic lab=vbias1} |
| C {lab_wire.sym} 310 500 0 0 {name=l66 sig_type=std_logic lab=vbias2} |
| C {lab_wire.sym} 340 500 0 1 {name=l67 sig_type=std_logic lab=vbias3} |
| C {lab_wire.sym} 490 500 0 0 {name=l68 sig_type=std_logic lab=vbias4} |
| C {lab_wire.sym} 510 500 0 1 {name=l69 sig_type=std_logic lab=vbias5} |
| C {lab_wire.sym} 660 490 0 0 {name=l70 sig_type=std_logic lab=vbias6} |
| C {lab_wire.sym} 680 500 0 1 {name=l71 sig_type=std_logic lab=vbias7} |
| C {lab_wire.sym} 820 490 0 1 {name=l72 sig_type=std_logic lab=vbias8} |
| C {vsource.sym} 470 -120 0 0 {name=V2 value=1.8} |
| C {gnd.sym} 470 -70 0 0 {name=l47 lab=GND} |
| C {lab_wire.sym} 410 110 0 1 {name=l23 sig_type=std_logic lab=vin_n} |
| C {lab_wire.sym} 1450 -270 0 1 {name=l15 sig_type=std_logic lab=vp_p} |
| C {lab_wire.sym} 1430 -220 0 1 {name=l25 sig_type=std_logic lab=vp_n} |
| C {vsource.sym} 1530 -260 0 0 {name=V3 value=1.8} |
| C {gnd.sym} 1530 -180 0 0 {name=l28 lab=GND} |
| C {gnd.sym} 1620 40 0 0 {name=l31 lab=GND} |
| C {lab_wire.sym} 1820 -260 0 1 {name=l33 sig_type=std_logic lab=out_p} |
| C {lab_wire.sym} 1830 150 0 1 {name=l37 sig_type=std_logic lab=out_n} |
| C {lab_wire.sym} 640 -270 0 0 {name=l7 sig_type=std_logic lab=vref} |
| C {gnd.sym} 670 -30 0 0 {name=l12 lab=GND} |
| C {src/S_to_D/S_to_D.sym} 270 -80 0 0 {name=x1} |
| C {src/triangle/triangle.sym} 670 -110 0 0 {name=x2} |
| C {src/integrator/integrator.sym} 800 -290 0 0 {name=x3} |
| C {src/integrator/integrator.sym} 800 130 0 0 {name=x4} |
| C {src/comparator/comparator.sym} 1110 -220 0 0 {name=x5} |
| C {src/comparator/comparator.sym} 1100 180 0 0 {name=x6} |
| C {src/dead_time/dead_time.sym} 1250 -260 0 0 {name=x7} |
| C {src/dead_time/dead_time.sym} 1250 140 0 0 {name=x8} |
| C {src/output_driver/output_driver.sym} 1620 -50 0 0 {name=x9} |
| C {vsource.sym} 1770 -180 0 0 {name=V6 value=0} |
| C {vsource.sym} 1770 70 0 0 {name=V7 value=0} |
