upload
diff --git a/gds/.magicrc b/gds/.magicrc new file mode 100644 index 0000000..0f68c8c --- /dev/null +++ b/gds/.magicrc
@@ -0,0 +1,82 @@ +puts stdout "Sourcing design .magicrc for technology sky130A ..." + +# Put grid on 0.005 pitch. This is important, as some commands don't +# rescale the grid automatically (such as lef read?). + +set scalefac [tech lambda] +if {[lindex $scalefac 1] < 2} { + scalegrid 1 2 +} + +# drc off +drc euclidean on +# Change this to a fixed number for repeatable behavior with GDS writes +# e.g., "random seed 12345" +catch {random seed} + +# Allow override of PDK path from environment variable PDKPATH +if {[catch {set PDKPATH $env(PDKPATH)}]} { + set PDKPATH "/home/eda/pdk/sky130A" +} + +# loading technology +tech load $PDKPATH/libs.tech/magic/sky130A.tech + +# load device generator +source $PDKPATH/libs.tech/magic/sky130A.tcl + +# load bind keys (optional) +# source $PDKPATH/libs.tech/magic/sky130A-BindKeys + +# set units to lambda grid +snap lambda + +# set sky130 standard power, ground, and substrate names +set VDD VPWR +set GND VGND +set SUB VSUBS + +# Allow override of type of magic library views used, "mag" or "maglef", +# from environment variable MAGTYPE + +if {[catch {set MAGTYPE $env(MAGTYPE)}]} { + set MAGTYPE mag +} + +# add path to reference cells +if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} { + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18 + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros +} else { + addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE} +} + +# add path to GDS cells + +# add path to IP from catalog. This procedure defined in the PDK script. +catch {magic::query_mylib_ip} +# add path to local IP from user design space. Defined in the PDK script. +catch {magic::query_my_projects}
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz new file mode 100644 index 0000000..3dd19e8 --- /dev/null +++ b/gds/user_analog_project_wrapper.gds.gz
@@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:bd3acddb9a9789143356c1aa9acb7f138838c34c85ed18d9ed83e342203e79cb +size 121607665
diff --git a/netgen/comp.out b/netgen/comp.out index 9955338..f69925d 100644 --- a/netgen/comp.out +++ b/netgen/comp.out
@@ -1,64 +1,147 @@ -Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_W5U4AW in circuit example_por (0)(1 instance) -Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ in circuit example_por (0)(1 instance) -Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_TGFUGS in circuit example_por (0)(1 instance) -Flattening unmatched subcell sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 in circuit example_por (0)(1 instance) -Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_3YBPVB in circuit example_por (0)(4 instances) -Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YUHPXE in circuit example_por (0)(1 instance) -Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_PKVMTM in circuit example_por (0)(1 instance) -Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC in circuit example_por (0)(1 instance) -Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_1_WRT4AW in circuit example_por (0)(1 instance) -Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YEUEBV in circuit example_por (0)(1 instance) -Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YUHPBG in circuit example_por (0)(1 instance) -Flattening unmatched subcell user_analog_proj_example in circuit user_analog_project_wrapper (0)(1 instance) -Equate elements: no current cell. -Equate elements: no current cell. -Equate elements: no current cell. -Equate elements: no current cell. -Equate elements: no current cell. -Class sky130_fd_sc_hvl__buf_8: Merged 18 devices. -Equate elements: no current cell. -Equate elements: no current cell. -Class sky130_fd_sc_hvl__inv_8: Merged 14 devices. -Equate elements: no current cell. -Class example_por: Merged 20 devices. - -Subcircuit summary: -Circuit 1: example_por |Circuit 2: example_por -------------------------------------------------------------------------|------------------------------------------------------------------------ -sky130_fd_pr__cap_mim_m3_2 (1) |sky130_fd_pr__cap_mim_m3_2 (1) -sky130_fd_sc_hvl__buf_8 (2) |sky130_fd_sc_hvl__buf_8 (2) -sky130_fd_pr__pfet_g5v0d10v5 (8) |sky130_fd_pr__pfet_g5v0d10v5 (8) -sky130_fd_pr__nfet_g5v0d10v5 (3) |sky130_fd_pr__nfet_g5v0d10v5 (3) -sky130_fd_pr__res_xhigh_po_0p69 (3) |sky130_fd_pr__res_xhigh_po_0p69 (3) -sky130_fd_sc_hvl__schmittbuf_1 (1) |sky130_fd_sc_hvl__schmittbuf_1 (1) -sky130_fd_pr__cap_mim_m3_1 (1) |sky130_fd_pr__cap_mim_m3_1 (1) -sky130_fd_sc_hvl__inv_8 (1) |sky130_fd_sc_hvl__inv_8 (1) -Number of devices: 20 |Number of devices: 20 -Number of nets: 16 |Number of nets: 16 -------------------------------------------------------------------------------------------------------------------------------------------------- -Circuits match uniquely. -Property errors were found. -Netlists match uniquely. -There were property errors. -sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/sky130_fd_pr__res_xhigh_po_0p693 vs. sky130_fd_pr__res_xhigh_po_0p69R1: -Property W in circuit2 has no matching property in circuit1 -sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/sky130_fd_pr__res_xhigh_po_0p690 vs. sky130_fd_pr__res_xhigh_po_0p69R2: -Property W in circuit2 has no matching property in circuit1 -sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/sky130_fd_pr__res_xhigh_po_0p6918 vs. sky130_fd_pr__res_xhigh_po_0p69R3: -Property W in circuit2 has no matching property in circuit1 +Flattening unmatched subcell OTA in circuit S_to_D (1)(2 instances) +Flattening unmatched subcell OTA_tri in circuit triangle (1)(1 instance) +Flattening unmatched subcell OTA in circuit triangle (1)(1 instance) +Flattening unmatched subcell OTA_int in circuit integrator (1)(1 instance) +Flattening unmatched subcell inverter in circuit dead_time (1)(1 instance) +Flattening unmatched subcell nand in circuit dead_time (1)(2 instances) +Flattening unmatched subcell half_driver in circuit output_driver (1)(2 instances) +Flattening unmatched subcell S_to_D in circuit Class_D (1)(1 instance) +Flattening unmatched subcell triangle in circuit Class_D (1)(1 instance) +Flattening unmatched subcell integrator in circuit Class_D (1)(2 instances) +Flattening unmatched subcell comparator in circuit Class_D (1)(2 instances) +Flattening unmatched subcell dead_time in circuit Class_D (1)(2 instances) +Flattening unmatched subcell biasing_network in circuit Class_D (1)(1 instance) +Flattening unmatched subcell output_driver in circuit Class_D (1)(1 instance) +Flattening unmatched subcell Class_D_post in circuit user_analog_project_wrapper (0)(1 instance) +Flattening unmatched subcell Class_D in circuit user_analog_project_wrapper (1)(1 instance) +Warning: Equate pins: cell sky130_fd_pr__pfet_01v8_lvt has no definition, treated as a black box. +Warning: Equate pins: cell sky130_fd_pr__pfet_01v8_lvt has no definition, treated as a black box. Subcircuit pins: -Circuit 1: example_por |Circuit 2: example_por -------------------------------------------------------------------------|------------------------------------------------------------------------ -vdd3v3 |vdd3v3 -porb_h |porb_h -porb_l |porb_l -por_l |por_l -vdd1v8 |vdd1v8 -vss |vss -------------------------------------------------------------------------------------------------------------------------------------------------- +Circuit 1: sky130_fd_pr__pfet_01v8_lvt |Circuit 2: sky130_fd_pr__pfet_01v8_lvt +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- Cell pin lists are equivalent. -Device classes example_por and example_por are equivalent. +Device classes sky130_fd_pr__pfet_01v8_lvt and sky130_fd_pr__pfet_01v8_lvt are equivalent. +Warning: Equate pins: cell sky130_fd_pr__nfet_01v8_lvt has no definition, treated as a black box. +Warning: Equate pins: cell sky130_fd_pr__nfet_01v8_lvt has no definition, treated as a black box. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__nfet_01v8_lvt |Circuit 2: sky130_fd_pr__nfet_01v8_lvt +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__nfet_01v8_lvt and sky130_fd_pr__nfet_01v8_lvt are equivalent. +Warning: Equate pins: cell sky130_fd_pr__res_xhigh_po has no definition, treated as a black box. +Warning: Equate pins: cell sky130_fd_pr__res_xhigh_po has no definition, treated as a black box. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__res_xhigh_po |Circuit 2: sky130_fd_pr__res_xhigh_po +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__res_xhigh_po and sky130_fd_pr__res_xhigh_po are equivalent. +Warning: Equate pins: cell sky130_fd_pr__cap_mim_m3_1 has no definition, treated as a black box. +Warning: Equate pins: cell sky130_fd_pr__cap_mim_m3_1 has no definition, treated as a black box. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__cap_mim_m3_1 |Circuit 2: sky130_fd_pr__cap_mim_m3_1 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__cap_mim_m3_1 and sky130_fd_pr__cap_mim_m3_1 are equivalent. +Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 has no definition, treated as a black box. +Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 has no definition, treated as a black box. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent. +Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 has no definition, treated as a black box. +Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 has no definition, treated as a black box. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__pfet_01v8 |Circuit 2: sky130_fd_pr__pfet_01v8 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__pfet_01v8 and sky130_fd_pr__pfet_01v8 are equivalent. +Warning: Equate pins: cell sky130_fd_pr__cap_mim_m3_2 has no definition, treated as a black box. +Warning: Equate pins: cell sky130_fd_pr__cap_mim_m3_2 has no definition, treated as a black box. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__cap_mim_m3_2 |Circuit 2: sky130_fd_pr__cap_mim_m3_2 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__cap_mim_m3_2 and sky130_fd_pr__cap_mim_m3_2 are equivalent. + +Subcircuit summary: +Circuit 1: io_clamp |Circuit 2: io_clamp +-------------------------------------------|------------------------------------------- +sky130_fd_pr__diode_pd2nw_05v5 (4) |sky130_fd_pr__diode_pd2nw_05v5 (4) +Number of devices: 4 |Number of devices: 4 +Number of nets: 5 |Number of nets: 5 +--------------------------------------------------------------------------------------- +Circuits match uniquely. +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: io_clamp |Circuit 2: io_clamp +-------------------------------------------|------------------------------------------- +vdd |vdd +vss |vss +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes io_clamp and io_clamp are equivalent. + +Cell ESD disconnected node: w_61637_n30343# + +Subcircuit summary: +Circuit 1: ESD |Circuit 2: ESD +-------------------------------------------|------------------------------------------- +sky130_fd_pr__diode_pw2nd_05v5 (1) |sky130_fd_pr__diode_pw2nd_05v5 (1) +sky130_fd_pr__diode_pd2nw_05v5 (1) |sky130_fd_pr__diode_pd2nw_05v5 (1) +Number of devices: 2 |Number of devices: 2 +Number of nets: 3 |Number of nets: 3 +--------------------------------------------------------------------------------------- +Circuits match uniquely. +Netlists match uniquely. + +Subcircuit pins: +Circuit 1: ESD |Circuit 2: ESD +-------------------------------------------|------------------------------------------- +vin |vin +vdd |vdd +vss |vss +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes ESD and ESD are equivalent. Cell user_analog_project_wrapper disconnected node: gpio_analog[0] Cell user_analog_project_wrapper disconnected node: gpio_analog[10] @@ -71,9 +154,11 @@ Cell user_analog_project_wrapper disconnected node: gpio_analog[17] Cell user_analog_project_wrapper disconnected node: gpio_analog[1] Cell user_analog_project_wrapper disconnected node: gpio_analog[2] +Cell user_analog_project_wrapper disconnected node: gpio_analog[3] Cell user_analog_project_wrapper disconnected node: gpio_analog[4] Cell user_analog_project_wrapper disconnected node: gpio_analog[5] Cell user_analog_project_wrapper disconnected node: gpio_analog[6] +Cell user_analog_project_wrapper disconnected node: gpio_analog[7] Cell user_analog_project_wrapper disconnected node: gpio_analog[8] Cell user_analog_project_wrapper disconnected node: gpio_analog[9] Cell user_analog_project_wrapper disconnected node: gpio_noesd[0] @@ -94,16 +179,13 @@ Cell user_analog_project_wrapper disconnected node: gpio_noesd[7] Cell user_analog_project_wrapper disconnected node: gpio_noesd[8] Cell user_analog_project_wrapper disconnected node: gpio_noesd[9] -Cell user_analog_project_wrapper disconnected node: io_analog[0] -Cell user_analog_project_wrapper disconnected node: io_analog[10] -Cell user_analog_project_wrapper disconnected node: io_analog[1] -Cell user_analog_project_wrapper disconnected node: io_analog[2] -Cell user_analog_project_wrapper disconnected node: io_analog[3] -Cell user_analog_project_wrapper disconnected node: io_analog[7] -Cell user_analog_project_wrapper disconnected node: io_analog[8] Cell user_analog_project_wrapper disconnected node: io_analog[9] -Cell user_analog_project_wrapper disconnected node: io_analog[5] -Cell user_analog_project_wrapper disconnected node: io_analog[6] +Cell user_analog_project_wrapper disconnected node: io_clamp_high[0] +Cell user_analog_project_wrapper disconnected node: io_clamp_high[1] +Cell user_analog_project_wrapper disconnected node: io_clamp_high[2] +Cell user_analog_project_wrapper disconnected node: io_clamp_low[0] +Cell user_analog_project_wrapper disconnected node: io_clamp_low[1] +Cell user_analog_project_wrapper disconnected node: io_clamp_low[2] Cell user_analog_project_wrapper disconnected node: io_in[0] Cell user_analog_project_wrapper disconnected node: io_in[10] Cell user_analog_project_wrapper disconnected node: io_in[11] @@ -160,8 +242,12 @@ Cell user_analog_project_wrapper disconnected node: io_in_3v3[9] Cell user_analog_project_wrapper disconnected node: io_oeb[0] Cell user_analog_project_wrapper disconnected node: io_oeb[10] +Cell user_analog_project_wrapper disconnected node: io_oeb[11] +Cell user_analog_project_wrapper disconnected node: io_oeb[12] Cell user_analog_project_wrapper disconnected node: io_oeb[13] Cell user_analog_project_wrapper disconnected node: io_oeb[14] +Cell user_analog_project_wrapper disconnected node: io_oeb[15] +Cell user_analog_project_wrapper disconnected node: io_oeb[16] Cell user_analog_project_wrapper disconnected node: io_oeb[17] Cell user_analog_project_wrapper disconnected node: io_oeb[18] Cell user_analog_project_wrapper disconnected node: io_oeb[19] @@ -183,8 +269,12 @@ Cell user_analog_project_wrapper disconnected node: io_oeb[9] Cell user_analog_project_wrapper disconnected node: io_out[0] Cell user_analog_project_wrapper disconnected node: io_out[10] +Cell user_analog_project_wrapper disconnected node: io_out[11] +Cell user_analog_project_wrapper disconnected node: io_out[12] Cell user_analog_project_wrapper disconnected node: io_out[13] Cell user_analog_project_wrapper disconnected node: io_out[14] +Cell user_analog_project_wrapper disconnected node: io_out[15] +Cell user_analog_project_wrapper disconnected node: io_out[16] Cell user_analog_project_wrapper disconnected node: io_out[17] Cell user_analog_project_wrapper disconnected node: io_out[18] Cell user_analog_project_wrapper disconnected node: io_out[19] @@ -592,11 +682,6 @@ Cell user_analog_project_wrapper disconnected node: user_irq[0] Cell user_analog_project_wrapper disconnected node: user_irq[1] Cell user_analog_project_wrapper disconnected node: user_irq[2] -Cell user_analog_project_wrapper disconnected node: vccd2 -Cell user_analog_project_wrapper disconnected node: vdda2 -Cell user_analog_project_wrapper disconnected node: vssa2 -Cell user_analog_project_wrapper disconnected node: vssd1 -Cell user_analog_project_wrapper disconnected node: vssd2 Cell user_analog_project_wrapper disconnected node: wb_clk_i Cell user_analog_project_wrapper disconnected node: wb_rst_i Cell user_analog_project_wrapper disconnected node: wbs_ack_o @@ -704,11 +789,6 @@ Cell user_analog_project_wrapper disconnected node: wbs_stb_i Cell user_analog_project_wrapper disconnected node: wbs_we_i -Cell user_analog_project_wrapper disconnected node: vdda2 -Cell user_analog_project_wrapper disconnected node: vssa2 -Cell user_analog_project_wrapper disconnected node: vccd2 -Cell user_analog_project_wrapper disconnected node: vssd1 -Cell user_analog_project_wrapper disconnected node: vssd2 Cell user_analog_project_wrapper disconnected node: wb_clk_i Cell user_analog_project_wrapper disconnected node: wb_rst_i Cell user_analog_project_wrapper disconnected node: wbs_stb_i @@ -1071,134 +1151,6 @@ Cell user_analog_project_wrapper disconnected node: la_data_out[2] Cell user_analog_project_wrapper disconnected node: la_data_out[1] Cell user_analog_project_wrapper disconnected node: la_data_out[0] -Cell user_analog_project_wrapper disconnected node: la_oenb[127] -Cell user_analog_project_wrapper disconnected node: la_oenb[126] -Cell user_analog_project_wrapper disconnected node: la_oenb[125] -Cell user_analog_project_wrapper disconnected node: la_oenb[124] -Cell user_analog_project_wrapper disconnected node: la_oenb[123] -Cell user_analog_project_wrapper disconnected node: la_oenb[122] -Cell user_analog_project_wrapper disconnected node: la_oenb[121] -Cell user_analog_project_wrapper disconnected node: la_oenb[120] -Cell user_analog_project_wrapper disconnected node: la_oenb[119] -Cell user_analog_project_wrapper disconnected node: la_oenb[118] -Cell user_analog_project_wrapper disconnected node: la_oenb[117] -Cell user_analog_project_wrapper disconnected node: la_oenb[116] -Cell user_analog_project_wrapper disconnected node: la_oenb[115] -Cell user_analog_project_wrapper disconnected node: la_oenb[114] -Cell user_analog_project_wrapper disconnected node: la_oenb[113] -Cell user_analog_project_wrapper disconnected node: la_oenb[112] -Cell user_analog_project_wrapper disconnected node: la_oenb[111] -Cell user_analog_project_wrapper disconnected node: la_oenb[110] -Cell user_analog_project_wrapper disconnected node: la_oenb[109] -Cell user_analog_project_wrapper disconnected node: la_oenb[108] -Cell user_analog_project_wrapper disconnected node: la_oenb[107] -Cell user_analog_project_wrapper disconnected node: la_oenb[106] -Cell user_analog_project_wrapper disconnected node: la_oenb[105] -Cell user_analog_project_wrapper disconnected node: la_oenb[104] -Cell user_analog_project_wrapper disconnected node: la_oenb[103] -Cell user_analog_project_wrapper disconnected node: la_oenb[102] -Cell user_analog_project_wrapper disconnected node: la_oenb[101] -Cell user_analog_project_wrapper disconnected node: la_oenb[100] -Cell user_analog_project_wrapper disconnected node: la_oenb[99] -Cell user_analog_project_wrapper disconnected node: la_oenb[98] -Cell user_analog_project_wrapper disconnected node: la_oenb[97] -Cell user_analog_project_wrapper disconnected node: la_oenb[96] -Cell user_analog_project_wrapper disconnected node: la_oenb[95] -Cell user_analog_project_wrapper disconnected node: la_oenb[94] -Cell user_analog_project_wrapper disconnected node: la_oenb[93] -Cell user_analog_project_wrapper disconnected node: la_oenb[92] -Cell user_analog_project_wrapper disconnected node: la_oenb[91] -Cell user_analog_project_wrapper disconnected node: la_oenb[90] -Cell user_analog_project_wrapper disconnected node: la_oenb[89] -Cell user_analog_project_wrapper disconnected node: la_oenb[88] -Cell user_analog_project_wrapper disconnected node: la_oenb[87] -Cell user_analog_project_wrapper disconnected node: la_oenb[86] -Cell user_analog_project_wrapper disconnected node: la_oenb[85] -Cell user_analog_project_wrapper disconnected node: la_oenb[84] -Cell user_analog_project_wrapper disconnected node: la_oenb[83] -Cell user_analog_project_wrapper disconnected node: la_oenb[82] -Cell user_analog_project_wrapper disconnected node: la_oenb[81] -Cell user_analog_project_wrapper disconnected node: la_oenb[80] -Cell user_analog_project_wrapper disconnected node: la_oenb[79] -Cell user_analog_project_wrapper disconnected node: la_oenb[78] -Cell user_analog_project_wrapper disconnected node: la_oenb[77] -Cell user_analog_project_wrapper disconnected node: la_oenb[76] -Cell user_analog_project_wrapper disconnected node: la_oenb[75] -Cell user_analog_project_wrapper disconnected node: la_oenb[74] -Cell user_analog_project_wrapper disconnected node: la_oenb[73] -Cell user_analog_project_wrapper disconnected node: la_oenb[72] -Cell user_analog_project_wrapper disconnected node: la_oenb[71] -Cell user_analog_project_wrapper disconnected node: la_oenb[70] -Cell user_analog_project_wrapper disconnected node: la_oenb[69] -Cell user_analog_project_wrapper disconnected node: la_oenb[68] -Cell user_analog_project_wrapper disconnected node: la_oenb[67] -Cell user_analog_project_wrapper disconnected node: la_oenb[66] -Cell user_analog_project_wrapper disconnected node: la_oenb[65] -Cell user_analog_project_wrapper disconnected node: la_oenb[64] -Cell user_analog_project_wrapper disconnected node: la_oenb[63] -Cell user_analog_project_wrapper disconnected node: la_oenb[62] -Cell user_analog_project_wrapper disconnected node: la_oenb[61] -Cell user_analog_project_wrapper disconnected node: la_oenb[60] -Cell user_analog_project_wrapper disconnected node: la_oenb[59] -Cell user_analog_project_wrapper disconnected node: la_oenb[58] -Cell user_analog_project_wrapper disconnected node: la_oenb[57] -Cell user_analog_project_wrapper disconnected node: la_oenb[56] -Cell user_analog_project_wrapper disconnected node: la_oenb[55] -Cell user_analog_project_wrapper disconnected node: la_oenb[54] -Cell user_analog_project_wrapper disconnected node: la_oenb[53] -Cell user_analog_project_wrapper disconnected node: la_oenb[52] -Cell user_analog_project_wrapper disconnected node: la_oenb[51] -Cell user_analog_project_wrapper disconnected node: la_oenb[50] -Cell user_analog_project_wrapper disconnected node: la_oenb[49] -Cell user_analog_project_wrapper disconnected node: la_oenb[48] -Cell user_analog_project_wrapper disconnected node: la_oenb[47] -Cell user_analog_project_wrapper disconnected node: la_oenb[46] -Cell user_analog_project_wrapper disconnected node: la_oenb[45] -Cell user_analog_project_wrapper disconnected node: la_oenb[44] -Cell user_analog_project_wrapper disconnected node: la_oenb[43] -Cell user_analog_project_wrapper disconnected node: la_oenb[42] -Cell user_analog_project_wrapper disconnected node: la_oenb[41] -Cell user_analog_project_wrapper disconnected node: la_oenb[40] -Cell user_analog_project_wrapper disconnected node: la_oenb[39] -Cell user_analog_project_wrapper disconnected node: la_oenb[38] -Cell user_analog_project_wrapper disconnected node: la_oenb[37] -Cell user_analog_project_wrapper disconnected node: la_oenb[36] -Cell user_analog_project_wrapper disconnected node: la_oenb[35] -Cell user_analog_project_wrapper disconnected node: la_oenb[34] -Cell user_analog_project_wrapper disconnected node: la_oenb[33] -Cell user_analog_project_wrapper disconnected node: la_oenb[32] -Cell user_analog_project_wrapper disconnected node: la_oenb[31] -Cell user_analog_project_wrapper disconnected node: la_oenb[30] -Cell user_analog_project_wrapper disconnected node: la_oenb[29] -Cell user_analog_project_wrapper disconnected node: la_oenb[28] -Cell user_analog_project_wrapper disconnected node: la_oenb[27] -Cell user_analog_project_wrapper disconnected node: la_oenb[26] -Cell user_analog_project_wrapper disconnected node: la_oenb[25] -Cell user_analog_project_wrapper disconnected node: la_oenb[24] -Cell user_analog_project_wrapper disconnected node: la_oenb[23] -Cell user_analog_project_wrapper disconnected node: la_oenb[22] -Cell user_analog_project_wrapper disconnected node: la_oenb[21] -Cell user_analog_project_wrapper disconnected node: la_oenb[20] -Cell user_analog_project_wrapper disconnected node: la_oenb[19] -Cell user_analog_project_wrapper disconnected node: la_oenb[18] -Cell user_analog_project_wrapper disconnected node: la_oenb[17] -Cell user_analog_project_wrapper disconnected node: la_oenb[16] -Cell user_analog_project_wrapper disconnected node: la_oenb[15] -Cell user_analog_project_wrapper disconnected node: la_oenb[14] -Cell user_analog_project_wrapper disconnected node: la_oenb[13] -Cell user_analog_project_wrapper disconnected node: la_oenb[12] -Cell user_analog_project_wrapper disconnected node: la_oenb[11] -Cell user_analog_project_wrapper disconnected node: la_oenb[10] -Cell user_analog_project_wrapper disconnected node: la_oenb[9] -Cell user_analog_project_wrapper disconnected node: la_oenb[8] -Cell user_analog_project_wrapper disconnected node: la_oenb[7] -Cell user_analog_project_wrapper disconnected node: la_oenb[6] -Cell user_analog_project_wrapper disconnected node: la_oenb[5] -Cell user_analog_project_wrapper disconnected node: la_oenb[4] -Cell user_analog_project_wrapper disconnected node: la_oenb[3] -Cell user_analog_project_wrapper disconnected node: la_oenb[2] -Cell user_analog_project_wrapper disconnected node: la_oenb[1] -Cell user_analog_project_wrapper disconnected node: la_oenb[0] Cell user_analog_project_wrapper disconnected node: io_in[26] Cell user_analog_project_wrapper disconnected node: io_in[25] Cell user_analog_project_wrapper disconnected node: io_in[24] @@ -1253,6 +1205,7 @@ Cell user_analog_project_wrapper disconnected node: io_in_3v3[2] Cell user_analog_project_wrapper disconnected node: io_in_3v3[1] Cell user_analog_project_wrapper disconnected node: io_in_3v3[0] +Cell user_analog_project_wrapper disconnected node: user_clock2 Cell user_analog_project_wrapper disconnected node: io_out[26] Cell user_analog_project_wrapper disconnected node: io_out[25] Cell user_analog_project_wrapper disconnected node: io_out[24] @@ -1263,8 +1216,12 @@ Cell user_analog_project_wrapper disconnected node: io_out[19] Cell user_analog_project_wrapper disconnected node: io_out[18] Cell user_analog_project_wrapper disconnected node: io_out[17] +Cell user_analog_project_wrapper disconnected node: io_out[16] +Cell user_analog_project_wrapper disconnected node: io_out[15] Cell user_analog_project_wrapper disconnected node: io_out[14] Cell user_analog_project_wrapper disconnected node: io_out[13] +Cell user_analog_project_wrapper disconnected node: io_out[12] +Cell user_analog_project_wrapper disconnected node: io_out[11] Cell user_analog_project_wrapper disconnected node: io_out[10] Cell user_analog_project_wrapper disconnected node: io_out[9] Cell user_analog_project_wrapper disconnected node: io_out[8] @@ -1313,9 +1270,11 @@ Cell user_analog_project_wrapper disconnected node: gpio_analog[10] Cell user_analog_project_wrapper disconnected node: gpio_analog[9] Cell user_analog_project_wrapper disconnected node: gpio_analog[8] +Cell user_analog_project_wrapper disconnected node: gpio_analog[7] Cell user_analog_project_wrapper disconnected node: gpio_analog[6] Cell user_analog_project_wrapper disconnected node: gpio_analog[5] Cell user_analog_project_wrapper disconnected node: gpio_analog[4] +Cell user_analog_project_wrapper disconnected node: gpio_analog[3] Cell user_analog_project_wrapper disconnected node: gpio_analog[2] Cell user_analog_project_wrapper disconnected node: gpio_analog[1] Cell user_analog_project_wrapper disconnected node: gpio_analog[0] @@ -1337,707 +1296,2129 @@ Cell user_analog_project_wrapper disconnected node: gpio_noesd[2] Cell user_analog_project_wrapper disconnected node: gpio_noesd[1] Cell user_analog_project_wrapper disconnected node: gpio_noesd[0] -Cell user_analog_project_wrapper disconnected node: io_analog[10] Cell user_analog_project_wrapper disconnected node: io_analog[9] -Cell user_analog_project_wrapper disconnected node: io_analog[8] -Cell user_analog_project_wrapper disconnected node: io_analog[7] -Cell user_analog_project_wrapper disconnected node: io_analog[6] -Cell user_analog_project_wrapper disconnected node: io_analog[5] -Cell user_analog_project_wrapper disconnected node: io_analog[3] -Cell user_analog_project_wrapper disconnected node: io_analog[2] -Cell user_analog_project_wrapper disconnected node: io_analog[1] -Cell user_analog_project_wrapper disconnected node: io_analog[0] Cell user_analog_project_wrapper disconnected node: io_clamp_high[2] Cell user_analog_project_wrapper disconnected node: io_clamp_high[1] Cell user_analog_project_wrapper disconnected node: io_clamp_high[0] Cell user_analog_project_wrapper disconnected node: io_clamp_low[2] Cell user_analog_project_wrapper disconnected node: io_clamp_low[1] Cell user_analog_project_wrapper disconnected node: io_clamp_low[0] -Cell user_analog_project_wrapper disconnected node: user_clock2 Cell user_analog_project_wrapper disconnected node: user_irq[2] Cell user_analog_project_wrapper disconnected node: user_irq[1] Cell user_analog_project_wrapper disconnected node: user_irq[0] +Cell user_analog_project_wrapper disconnected node: la_oenb[127] +Cell user_analog_project_wrapper disconnected node: la_oenb[126] +Cell user_analog_project_wrapper disconnected node: la_oenb[125] +Cell user_analog_project_wrapper disconnected node: la_oenb[124] +Cell user_analog_project_wrapper disconnected node: la_oenb[123] +Cell user_analog_project_wrapper disconnected node: la_oenb[122] +Cell user_analog_project_wrapper disconnected node: la_oenb[121] +Cell user_analog_project_wrapper disconnected node: la_oenb[120] +Cell user_analog_project_wrapper disconnected node: la_oenb[119] +Cell user_analog_project_wrapper disconnected node: la_oenb[118] +Cell user_analog_project_wrapper disconnected node: la_oenb[117] +Cell user_analog_project_wrapper disconnected node: la_oenb[116] +Cell user_analog_project_wrapper disconnected node: la_oenb[115] +Cell user_analog_project_wrapper disconnected node: la_oenb[114] +Cell user_analog_project_wrapper disconnected node: la_oenb[113] +Cell user_analog_project_wrapper disconnected node: la_oenb[112] +Cell user_analog_project_wrapper disconnected node: la_oenb[111] +Cell user_analog_project_wrapper disconnected node: la_oenb[110] +Cell user_analog_project_wrapper disconnected node: la_oenb[109] +Cell user_analog_project_wrapper disconnected node: la_oenb[108] +Cell user_analog_project_wrapper disconnected node: la_oenb[107] +Cell user_analog_project_wrapper disconnected node: la_oenb[106] +Cell user_analog_project_wrapper disconnected node: la_oenb[105] +Cell user_analog_project_wrapper disconnected node: la_oenb[104] +Cell user_analog_project_wrapper disconnected node: la_oenb[103] +Cell user_analog_project_wrapper disconnected node: la_oenb[102] +Cell user_analog_project_wrapper disconnected node: la_oenb[101] +Cell user_analog_project_wrapper disconnected node: la_oenb[100] +Cell user_analog_project_wrapper disconnected node: la_oenb[99] +Cell user_analog_project_wrapper disconnected node: la_oenb[98] +Cell user_analog_project_wrapper disconnected node: la_oenb[97] +Cell user_analog_project_wrapper disconnected node: la_oenb[96] +Cell user_analog_project_wrapper disconnected node: la_oenb[95] +Cell user_analog_project_wrapper disconnected node: la_oenb[94] +Cell user_analog_project_wrapper disconnected node: la_oenb[93] +Cell user_analog_project_wrapper disconnected node: la_oenb[92] +Cell user_analog_project_wrapper disconnected node: la_oenb[91] +Cell user_analog_project_wrapper disconnected node: la_oenb[90] +Cell user_analog_project_wrapper disconnected node: la_oenb[89] +Cell user_analog_project_wrapper disconnected node: la_oenb[88] +Cell user_analog_project_wrapper disconnected node: la_oenb[87] +Cell user_analog_project_wrapper disconnected node: la_oenb[86] +Cell user_analog_project_wrapper disconnected node: la_oenb[85] +Cell user_analog_project_wrapper disconnected node: la_oenb[84] +Cell user_analog_project_wrapper disconnected node: la_oenb[83] +Cell user_analog_project_wrapper disconnected node: la_oenb[82] +Cell user_analog_project_wrapper disconnected node: la_oenb[81] +Cell user_analog_project_wrapper disconnected node: la_oenb[80] +Cell user_analog_project_wrapper disconnected node: la_oenb[79] +Cell user_analog_project_wrapper disconnected node: la_oenb[78] +Cell user_analog_project_wrapper disconnected node: la_oenb[77] +Cell user_analog_project_wrapper disconnected node: la_oenb[76] +Cell user_analog_project_wrapper disconnected node: la_oenb[75] +Cell user_analog_project_wrapper disconnected node: la_oenb[74] +Cell user_analog_project_wrapper disconnected node: la_oenb[73] +Cell user_analog_project_wrapper disconnected node: la_oenb[72] +Cell user_analog_project_wrapper disconnected node: la_oenb[71] +Cell user_analog_project_wrapper disconnected node: la_oenb[70] +Cell user_analog_project_wrapper disconnected node: la_oenb[69] +Cell user_analog_project_wrapper disconnected node: la_oenb[68] +Cell user_analog_project_wrapper disconnected node: la_oenb[67] +Cell user_analog_project_wrapper disconnected node: la_oenb[66] +Cell user_analog_project_wrapper disconnected node: la_oenb[65] +Cell user_analog_project_wrapper disconnected node: la_oenb[64] +Cell user_analog_project_wrapper disconnected node: la_oenb[63] +Cell user_analog_project_wrapper disconnected node: la_oenb[62] +Cell user_analog_project_wrapper disconnected node: la_oenb[61] +Cell user_analog_project_wrapper disconnected node: la_oenb[60] +Cell user_analog_project_wrapper disconnected node: la_oenb[59] +Cell user_analog_project_wrapper disconnected node: la_oenb[58] +Cell user_analog_project_wrapper disconnected node: la_oenb[57] +Cell user_analog_project_wrapper disconnected node: la_oenb[56] +Cell user_analog_project_wrapper disconnected node: la_oenb[55] +Cell user_analog_project_wrapper disconnected node: la_oenb[54] +Cell user_analog_project_wrapper disconnected node: la_oenb[53] +Cell user_analog_project_wrapper disconnected node: la_oenb[52] +Cell user_analog_project_wrapper disconnected node: la_oenb[51] +Cell user_analog_project_wrapper disconnected node: la_oenb[50] +Cell user_analog_project_wrapper disconnected node: la_oenb[49] +Cell user_analog_project_wrapper disconnected node: la_oenb[48] +Cell user_analog_project_wrapper disconnected node: la_oenb[47] +Cell user_analog_project_wrapper disconnected node: la_oenb[46] +Cell user_analog_project_wrapper disconnected node: la_oenb[45] +Cell user_analog_project_wrapper disconnected node: la_oenb[44] +Cell user_analog_project_wrapper disconnected node: la_oenb[43] +Cell user_analog_project_wrapper disconnected node: la_oenb[42] +Cell user_analog_project_wrapper disconnected node: la_oenb[41] +Cell user_analog_project_wrapper disconnected node: la_oenb[40] +Cell user_analog_project_wrapper disconnected node: la_oenb[39] +Cell user_analog_project_wrapper disconnected node: la_oenb[38] +Cell user_analog_project_wrapper disconnected node: la_oenb[37] +Cell user_analog_project_wrapper disconnected node: la_oenb[36] +Cell user_analog_project_wrapper disconnected node: la_oenb[35] +Cell user_analog_project_wrapper disconnected node: la_oenb[34] +Cell user_analog_project_wrapper disconnected node: la_oenb[33] +Cell user_analog_project_wrapper disconnected node: la_oenb[32] +Cell user_analog_project_wrapper disconnected node: la_oenb[31] +Cell user_analog_project_wrapper disconnected node: la_oenb[30] +Cell user_analog_project_wrapper disconnected node: la_oenb[29] +Cell user_analog_project_wrapper disconnected node: la_oenb[28] +Cell user_analog_project_wrapper disconnected node: la_oenb[27] +Cell user_analog_project_wrapper disconnected node: la_oenb[26] +Cell user_analog_project_wrapper disconnected node: la_oenb[25] +Cell user_analog_project_wrapper disconnected node: la_oenb[24] +Cell user_analog_project_wrapper disconnected node: la_oenb[23] +Cell user_analog_project_wrapper disconnected node: la_oenb[22] +Cell user_analog_project_wrapper disconnected node: la_oenb[21] +Cell user_analog_project_wrapper disconnected node: la_oenb[20] +Cell user_analog_project_wrapper disconnected node: la_oenb[19] +Cell user_analog_project_wrapper disconnected node: la_oenb[18] +Cell user_analog_project_wrapper disconnected node: la_oenb[17] +Cell user_analog_project_wrapper disconnected node: la_oenb[16] +Cell user_analog_project_wrapper disconnected node: la_oenb[15] +Cell user_analog_project_wrapper disconnected node: la_oenb[14] +Cell user_analog_project_wrapper disconnected node: la_oenb[13] +Cell user_analog_project_wrapper disconnected node: la_oenb[12] +Cell user_analog_project_wrapper disconnected node: la_oenb[11] +Cell user_analog_project_wrapper disconnected node: la_oenb[10] +Cell user_analog_project_wrapper disconnected node: la_oenb[9] +Cell user_analog_project_wrapper disconnected node: la_oenb[8] +Cell user_analog_project_wrapper disconnected node: la_oenb[7] +Cell user_analog_project_wrapper disconnected node: la_oenb[6] +Cell user_analog_project_wrapper disconnected node: la_oenb[5] +Cell user_analog_project_wrapper disconnected node: la_oenb[4] +Cell user_analog_project_wrapper disconnected node: la_oenb[3] +Cell user_analog_project_wrapper disconnected node: la_oenb[2] +Cell user_analog_project_wrapper disconnected node: la_oenb[1] +Cell user_analog_project_wrapper disconnected node: la_oenb[0] +Class user_analog_project_wrapper: Merged 921 devices. +Class user_analog_project_wrapper: Merged 3 devices. + +Cell user_analog_project_wrapper disconnected node: gpio_analog[0] +Cell user_analog_project_wrapper disconnected node: gpio_analog[10] +Cell user_analog_project_wrapper disconnected node: gpio_analog[11] +Cell user_analog_project_wrapper disconnected node: gpio_analog[12] +Cell user_analog_project_wrapper disconnected node: gpio_analog[13] +Cell user_analog_project_wrapper disconnected node: gpio_analog[14] +Cell user_analog_project_wrapper disconnected node: gpio_analog[15] +Cell user_analog_project_wrapper disconnected node: gpio_analog[16] +Cell user_analog_project_wrapper disconnected node: gpio_analog[17] +Cell user_analog_project_wrapper disconnected node: gpio_analog[1] +Cell user_analog_project_wrapper disconnected node: gpio_analog[2] +Cell user_analog_project_wrapper disconnected node: gpio_analog[3] +Cell user_analog_project_wrapper disconnected node: gpio_analog[4] +Cell user_analog_project_wrapper disconnected node: gpio_analog[5] +Cell user_analog_project_wrapper disconnected node: gpio_analog[6] +Cell user_analog_project_wrapper disconnected node: gpio_analog[7] +Cell user_analog_project_wrapper disconnected node: gpio_analog[8] +Cell user_analog_project_wrapper disconnected node: gpio_analog[9] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[0] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[10] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[11] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[12] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[13] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[14] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[15] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[16] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[17] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[1] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[2] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[3] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[4] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[5] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[6] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[7] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[8] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[9] +Cell user_analog_project_wrapper disconnected node: io_analog[9] +Cell user_analog_project_wrapper disconnected node: io_clamp_high[0] +Cell user_analog_project_wrapper disconnected node: io_clamp_high[1] +Cell user_analog_project_wrapper disconnected node: io_clamp_high[2] +Cell user_analog_project_wrapper disconnected node: io_clamp_low[0] +Cell user_analog_project_wrapper disconnected node: io_clamp_low[1] +Cell user_analog_project_wrapper disconnected node: io_clamp_low[2] +Cell user_analog_project_wrapper disconnected node: io_in[0] +Cell user_analog_project_wrapper disconnected node: io_in[10] +Cell user_analog_project_wrapper disconnected node: io_in[11] +Cell user_analog_project_wrapper disconnected node: io_in[12] +Cell user_analog_project_wrapper disconnected node: io_in[13] +Cell user_analog_project_wrapper disconnected node: io_in[14] +Cell user_analog_project_wrapper disconnected node: io_in[15] +Cell user_analog_project_wrapper disconnected node: io_in[16] +Cell user_analog_project_wrapper disconnected node: io_in[17] +Cell user_analog_project_wrapper disconnected node: io_in[18] +Cell user_analog_project_wrapper disconnected node: io_in[19] +Cell user_analog_project_wrapper disconnected node: io_in[1] +Cell user_analog_project_wrapper disconnected node: io_in[20] +Cell user_analog_project_wrapper disconnected node: io_in[21] +Cell user_analog_project_wrapper disconnected node: io_in[22] +Cell user_analog_project_wrapper disconnected node: io_in[23] +Cell user_analog_project_wrapper disconnected node: io_in[24] +Cell user_analog_project_wrapper disconnected node: io_in[25] +Cell user_analog_project_wrapper disconnected node: io_in[26] +Cell user_analog_project_wrapper disconnected node: io_in[2] +Cell user_analog_project_wrapper disconnected node: io_in[3] +Cell user_analog_project_wrapper disconnected node: io_in[4] +Cell user_analog_project_wrapper disconnected node: io_in[5] +Cell user_analog_project_wrapper disconnected node: io_in[6] +Cell user_analog_project_wrapper disconnected node: io_in[7] +Cell user_analog_project_wrapper disconnected node: io_in[8] +Cell user_analog_project_wrapper disconnected node: io_in[9] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[0] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[10] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[11] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[12] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[13] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[14] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[15] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[16] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[17] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[18] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[19] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[1] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[20] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[21] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[22] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[23] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[24] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[25] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[26] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[2] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[3] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[4] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[5] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[6] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[7] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[8] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[9] +Cell user_analog_project_wrapper disconnected node: io_oeb[0] +Cell user_analog_project_wrapper disconnected node: io_oeb[10] +Cell user_analog_project_wrapper disconnected node: io_oeb[11] +Cell user_analog_project_wrapper disconnected node: io_oeb[12] +Cell user_analog_project_wrapper disconnected node: io_oeb[13] +Cell user_analog_project_wrapper disconnected node: io_oeb[14] +Cell user_analog_project_wrapper disconnected node: io_oeb[15] +Cell user_analog_project_wrapper disconnected node: io_oeb[16] +Cell user_analog_project_wrapper disconnected node: io_oeb[17] +Cell user_analog_project_wrapper disconnected node: io_oeb[18] +Cell user_analog_project_wrapper disconnected node: io_oeb[19] +Cell user_analog_project_wrapper disconnected node: io_oeb[1] +Cell user_analog_project_wrapper disconnected node: io_oeb[20] +Cell user_analog_project_wrapper disconnected node: io_oeb[21] +Cell user_analog_project_wrapper disconnected node: io_oeb[22] +Cell user_analog_project_wrapper disconnected node: io_oeb[23] +Cell user_analog_project_wrapper disconnected node: io_oeb[24] +Cell user_analog_project_wrapper disconnected node: io_oeb[25] +Cell user_analog_project_wrapper disconnected node: io_oeb[26] +Cell user_analog_project_wrapper disconnected node: io_oeb[2] +Cell user_analog_project_wrapper disconnected node: io_oeb[3] +Cell user_analog_project_wrapper disconnected node: io_oeb[4] +Cell user_analog_project_wrapper disconnected node: io_oeb[5] +Cell user_analog_project_wrapper disconnected node: io_oeb[6] +Cell user_analog_project_wrapper disconnected node: io_oeb[7] +Cell user_analog_project_wrapper disconnected node: io_oeb[8] +Cell user_analog_project_wrapper disconnected node: io_oeb[9] +Cell user_analog_project_wrapper disconnected node: io_out[0] +Cell user_analog_project_wrapper disconnected node: io_out[10] +Cell user_analog_project_wrapper disconnected node: io_out[11] +Cell user_analog_project_wrapper disconnected node: io_out[12] +Cell user_analog_project_wrapper disconnected node: io_out[13] +Cell user_analog_project_wrapper disconnected node: io_out[14] +Cell user_analog_project_wrapper disconnected node: io_out[15] +Cell user_analog_project_wrapper disconnected node: io_out[16] +Cell user_analog_project_wrapper disconnected node: io_out[17] +Cell user_analog_project_wrapper disconnected node: io_out[18] +Cell user_analog_project_wrapper disconnected node: io_out[19] +Cell user_analog_project_wrapper disconnected node: io_out[1] +Cell user_analog_project_wrapper disconnected node: io_out[20] +Cell user_analog_project_wrapper disconnected node: io_out[21] +Cell user_analog_project_wrapper disconnected node: io_out[22] +Cell user_analog_project_wrapper disconnected node: io_out[23] +Cell user_analog_project_wrapper disconnected node: io_out[24] +Cell user_analog_project_wrapper disconnected node: io_out[25] +Cell user_analog_project_wrapper disconnected node: io_out[26] +Cell user_analog_project_wrapper disconnected node: io_out[2] +Cell user_analog_project_wrapper disconnected node: io_out[3] +Cell user_analog_project_wrapper disconnected node: io_out[4] +Cell user_analog_project_wrapper disconnected node: io_out[5] +Cell user_analog_project_wrapper disconnected node: io_out[6] +Cell user_analog_project_wrapper disconnected node: io_out[7] +Cell user_analog_project_wrapper disconnected node: io_out[8] +Cell user_analog_project_wrapper disconnected node: io_out[9] +Cell user_analog_project_wrapper disconnected node: la_data_in[0] +Cell user_analog_project_wrapper disconnected node: la_data_in[100] +Cell user_analog_project_wrapper disconnected node: la_data_in[101] +Cell user_analog_project_wrapper disconnected node: la_data_in[102] +Cell user_analog_project_wrapper disconnected node: la_data_in[103] +Cell user_analog_project_wrapper disconnected node: la_data_in[104] +Cell user_analog_project_wrapper disconnected node: la_data_in[105] +Cell user_analog_project_wrapper disconnected node: la_data_in[106] +Cell user_analog_project_wrapper disconnected node: la_data_in[107] +Cell user_analog_project_wrapper disconnected node: la_data_in[108] +Cell user_analog_project_wrapper disconnected node: la_data_in[109] +Cell user_analog_project_wrapper disconnected node: la_data_in[10] +Cell user_analog_project_wrapper disconnected node: la_data_in[110] +Cell user_analog_project_wrapper disconnected node: la_data_in[111] +Cell user_analog_project_wrapper disconnected node: la_data_in[112] +Cell user_analog_project_wrapper disconnected node: la_data_in[113] +Cell user_analog_project_wrapper disconnected node: la_data_in[114] +Cell user_analog_project_wrapper disconnected node: la_data_in[115] +Cell user_analog_project_wrapper disconnected node: la_data_in[116] +Cell user_analog_project_wrapper disconnected node: la_data_in[117] +Cell user_analog_project_wrapper disconnected node: la_data_in[118] +Cell user_analog_project_wrapper disconnected node: la_data_in[119] +Cell user_analog_project_wrapper disconnected node: la_data_in[11] +Cell user_analog_project_wrapper disconnected node: la_data_in[120] +Cell user_analog_project_wrapper disconnected node: la_data_in[121] +Cell user_analog_project_wrapper disconnected node: la_data_in[122] +Cell user_analog_project_wrapper disconnected node: la_data_in[123] +Cell user_analog_project_wrapper disconnected node: la_data_in[124] +Cell user_analog_project_wrapper disconnected node: la_data_in[125] +Cell user_analog_project_wrapper disconnected node: la_data_in[126] +Cell user_analog_project_wrapper disconnected node: la_data_in[127] +Cell user_analog_project_wrapper disconnected node: la_data_in[12] +Cell user_analog_project_wrapper disconnected node: la_data_in[13] +Cell user_analog_project_wrapper disconnected node: la_data_in[14] +Cell user_analog_project_wrapper disconnected node: la_data_in[15] +Cell user_analog_project_wrapper disconnected node: la_data_in[16] +Cell user_analog_project_wrapper disconnected node: la_data_in[17] +Cell user_analog_project_wrapper disconnected node: la_data_in[18] +Cell user_analog_project_wrapper disconnected node: la_data_in[19] +Cell user_analog_project_wrapper disconnected node: la_data_in[1] +Cell user_analog_project_wrapper disconnected node: la_data_in[20] +Cell user_analog_project_wrapper disconnected node: la_data_in[21] +Cell user_analog_project_wrapper disconnected node: la_data_in[22] +Cell user_analog_project_wrapper disconnected node: la_data_in[23] +Cell user_analog_project_wrapper disconnected node: la_data_in[24] +Cell user_analog_project_wrapper disconnected node: la_data_in[25] +Cell user_analog_project_wrapper disconnected node: la_data_in[26] +Cell user_analog_project_wrapper disconnected node: la_data_in[27] +Cell user_analog_project_wrapper disconnected node: la_data_in[28] +Cell user_analog_project_wrapper disconnected node: la_data_in[29] +Cell user_analog_project_wrapper disconnected node: la_data_in[2] +Cell user_analog_project_wrapper disconnected node: la_data_in[30] +Cell user_analog_project_wrapper disconnected node: la_data_in[31] +Cell user_analog_project_wrapper disconnected node: la_data_in[32] +Cell user_analog_project_wrapper disconnected node: la_data_in[33] +Cell user_analog_project_wrapper disconnected node: la_data_in[34] +Cell user_analog_project_wrapper disconnected node: la_data_in[35] +Cell user_analog_project_wrapper disconnected node: la_data_in[36] +Cell user_analog_project_wrapper disconnected node: la_data_in[37] +Cell user_analog_project_wrapper disconnected node: la_data_in[38] +Cell user_analog_project_wrapper disconnected node: la_data_in[39] +Cell user_analog_project_wrapper disconnected node: la_data_in[3] +Cell user_analog_project_wrapper disconnected node: la_data_in[40] +Cell user_analog_project_wrapper disconnected node: la_data_in[41] +Cell user_analog_project_wrapper disconnected node: la_data_in[42] +Cell user_analog_project_wrapper disconnected node: la_data_in[43] +Cell user_analog_project_wrapper disconnected node: la_data_in[44] +Cell user_analog_project_wrapper disconnected node: la_data_in[45] +Cell user_analog_project_wrapper disconnected node: la_data_in[46] +Cell user_analog_project_wrapper disconnected node: la_data_in[47] +Cell user_analog_project_wrapper disconnected node: la_data_in[48] +Cell user_analog_project_wrapper disconnected node: la_data_in[49] +Cell user_analog_project_wrapper disconnected node: la_data_in[4] +Cell user_analog_project_wrapper disconnected node: la_data_in[50] +Cell user_analog_project_wrapper disconnected node: la_data_in[51] +Cell user_analog_project_wrapper disconnected node: la_data_in[52] +Cell user_analog_project_wrapper disconnected node: la_data_in[53] +Cell user_analog_project_wrapper disconnected node: la_data_in[54] +Cell user_analog_project_wrapper disconnected node: la_data_in[55] +Cell user_analog_project_wrapper disconnected node: la_data_in[56] +Cell user_analog_project_wrapper disconnected node: la_data_in[57] +Cell user_analog_project_wrapper disconnected node: la_data_in[58] +Cell user_analog_project_wrapper disconnected node: la_data_in[59] +Cell user_analog_project_wrapper disconnected node: la_data_in[5] +Cell user_analog_project_wrapper disconnected node: la_data_in[60] +Cell user_analog_project_wrapper disconnected node: la_data_in[61] +Cell user_analog_project_wrapper disconnected node: la_data_in[62] +Cell user_analog_project_wrapper disconnected node: la_data_in[63] +Cell user_analog_project_wrapper disconnected node: la_data_in[64] +Cell user_analog_project_wrapper disconnected node: la_data_in[65] +Cell user_analog_project_wrapper disconnected node: la_data_in[66] +Cell user_analog_project_wrapper disconnected node: la_data_in[67] +Cell user_analog_project_wrapper disconnected node: la_data_in[68] +Cell user_analog_project_wrapper disconnected node: la_data_in[69] +Cell user_analog_project_wrapper disconnected node: la_data_in[6] +Cell user_analog_project_wrapper disconnected node: la_data_in[70] +Cell user_analog_project_wrapper disconnected node: la_data_in[71] +Cell user_analog_project_wrapper disconnected node: la_data_in[72] +Cell user_analog_project_wrapper disconnected node: la_data_in[73] +Cell user_analog_project_wrapper disconnected node: la_data_in[74] +Cell user_analog_project_wrapper disconnected node: la_data_in[75] +Cell user_analog_project_wrapper disconnected node: la_data_in[76] +Cell user_analog_project_wrapper disconnected node: la_data_in[77] +Cell user_analog_project_wrapper disconnected node: la_data_in[78] +Cell user_analog_project_wrapper disconnected node: la_data_in[79] +Cell user_analog_project_wrapper disconnected node: la_data_in[7] +Cell user_analog_project_wrapper disconnected node: la_data_in[80] +Cell user_analog_project_wrapper disconnected node: la_data_in[81] +Cell user_analog_project_wrapper disconnected node: la_data_in[82] +Cell user_analog_project_wrapper disconnected node: la_data_in[83] +Cell user_analog_project_wrapper disconnected node: la_data_in[84] +Cell user_analog_project_wrapper disconnected node: la_data_in[85] +Cell user_analog_project_wrapper disconnected node: la_data_in[86] +Cell user_analog_project_wrapper disconnected node: la_data_in[87] +Cell user_analog_project_wrapper disconnected node: la_data_in[88] +Cell user_analog_project_wrapper disconnected node: la_data_in[89] +Cell user_analog_project_wrapper disconnected node: la_data_in[8] +Cell user_analog_project_wrapper disconnected node: la_data_in[90] +Cell user_analog_project_wrapper disconnected node: la_data_in[91] +Cell user_analog_project_wrapper disconnected node: la_data_in[92] +Cell user_analog_project_wrapper disconnected node: la_data_in[93] +Cell user_analog_project_wrapper disconnected node: la_data_in[94] +Cell user_analog_project_wrapper disconnected node: la_data_in[95] +Cell user_analog_project_wrapper disconnected node: la_data_in[96] +Cell user_analog_project_wrapper disconnected node: la_data_in[97] +Cell user_analog_project_wrapper disconnected node: la_data_in[98] +Cell user_analog_project_wrapper disconnected node: la_data_in[99] +Cell user_analog_project_wrapper disconnected node: la_data_in[9] +Cell user_analog_project_wrapper disconnected node: la_data_out[0] +Cell user_analog_project_wrapper disconnected node: la_data_out[100] +Cell user_analog_project_wrapper disconnected node: la_data_out[101] +Cell user_analog_project_wrapper disconnected node: la_data_out[102] +Cell user_analog_project_wrapper disconnected node: la_data_out[103] +Cell user_analog_project_wrapper disconnected node: la_data_out[104] +Cell user_analog_project_wrapper disconnected node: la_data_out[105] +Cell user_analog_project_wrapper disconnected node: la_data_out[106] +Cell user_analog_project_wrapper disconnected node: la_data_out[107] +Cell user_analog_project_wrapper disconnected node: la_data_out[108] +Cell user_analog_project_wrapper disconnected node: la_data_out[109] +Cell user_analog_project_wrapper disconnected node: la_data_out[10] +Cell user_analog_project_wrapper disconnected node: la_data_out[110] +Cell user_analog_project_wrapper disconnected node: la_data_out[111] +Cell user_analog_project_wrapper disconnected node: la_data_out[112] +Cell user_analog_project_wrapper disconnected node: la_data_out[113] +Cell user_analog_project_wrapper disconnected node: la_data_out[114] +Cell user_analog_project_wrapper disconnected node: la_data_out[115] +Cell user_analog_project_wrapper disconnected node: la_data_out[116] +Cell user_analog_project_wrapper disconnected node: la_data_out[117] +Cell user_analog_project_wrapper disconnected node: la_data_out[118] +Cell user_analog_project_wrapper disconnected node: la_data_out[119] +Cell user_analog_project_wrapper disconnected node: la_data_out[11] +Cell user_analog_project_wrapper disconnected node: la_data_out[120] +Cell user_analog_project_wrapper disconnected node: la_data_out[121] +Cell user_analog_project_wrapper disconnected node: la_data_out[122] +Cell user_analog_project_wrapper disconnected node: la_data_out[123] +Cell user_analog_project_wrapper disconnected node: la_data_out[124] +Cell user_analog_project_wrapper disconnected node: la_data_out[125] +Cell user_analog_project_wrapper disconnected node: la_data_out[126] +Cell user_analog_project_wrapper disconnected node: la_data_out[127] +Cell user_analog_project_wrapper disconnected node: la_data_out[12] +Cell user_analog_project_wrapper disconnected node: la_data_out[13] +Cell user_analog_project_wrapper disconnected node: la_data_out[14] +Cell user_analog_project_wrapper disconnected node: la_data_out[15] +Cell user_analog_project_wrapper disconnected node: la_data_out[16] +Cell user_analog_project_wrapper disconnected node: la_data_out[17] +Cell user_analog_project_wrapper disconnected node: la_data_out[18] +Cell user_analog_project_wrapper disconnected node: la_data_out[19] +Cell user_analog_project_wrapper disconnected node: la_data_out[1] +Cell user_analog_project_wrapper disconnected node: la_data_out[20] +Cell user_analog_project_wrapper disconnected node: la_data_out[21] +Cell user_analog_project_wrapper disconnected node: la_data_out[22] +Cell user_analog_project_wrapper disconnected node: la_data_out[23] +Cell user_analog_project_wrapper disconnected node: la_data_out[24] +Cell user_analog_project_wrapper disconnected node: la_data_out[25] +Cell user_analog_project_wrapper disconnected node: la_data_out[26] +Cell user_analog_project_wrapper disconnected node: la_data_out[27] +Cell user_analog_project_wrapper disconnected node: la_data_out[28] +Cell user_analog_project_wrapper disconnected node: la_data_out[29] +Cell user_analog_project_wrapper disconnected node: la_data_out[2] +Cell user_analog_project_wrapper disconnected node: la_data_out[30] +Cell user_analog_project_wrapper disconnected node: la_data_out[31] +Cell user_analog_project_wrapper disconnected node: la_data_out[32] +Cell user_analog_project_wrapper disconnected node: la_data_out[33] +Cell user_analog_project_wrapper disconnected node: la_data_out[34] +Cell user_analog_project_wrapper disconnected node: la_data_out[35] +Cell user_analog_project_wrapper disconnected node: la_data_out[36] +Cell user_analog_project_wrapper disconnected node: la_data_out[37] +Cell user_analog_project_wrapper disconnected node: la_data_out[38] +Cell user_analog_project_wrapper disconnected node: la_data_out[39] +Cell user_analog_project_wrapper disconnected node: la_data_out[3] +Cell user_analog_project_wrapper disconnected node: la_data_out[40] +Cell user_analog_project_wrapper disconnected node: la_data_out[41] +Cell user_analog_project_wrapper disconnected node: la_data_out[42] +Cell user_analog_project_wrapper disconnected node: la_data_out[43] +Cell user_analog_project_wrapper disconnected node: la_data_out[44] +Cell user_analog_project_wrapper disconnected node: la_data_out[45] +Cell user_analog_project_wrapper disconnected node: la_data_out[46] +Cell user_analog_project_wrapper disconnected node: la_data_out[47] +Cell user_analog_project_wrapper disconnected node: la_data_out[48] +Cell user_analog_project_wrapper disconnected node: la_data_out[49] +Cell user_analog_project_wrapper disconnected node: la_data_out[4] +Cell user_analog_project_wrapper disconnected node: la_data_out[50] +Cell user_analog_project_wrapper disconnected node: la_data_out[51] +Cell user_analog_project_wrapper disconnected node: la_data_out[52] +Cell user_analog_project_wrapper disconnected node: la_data_out[53] +Cell user_analog_project_wrapper disconnected node: la_data_out[54] +Cell user_analog_project_wrapper disconnected node: la_data_out[55] +Cell user_analog_project_wrapper disconnected node: la_data_out[56] +Cell user_analog_project_wrapper disconnected node: la_data_out[57] +Cell user_analog_project_wrapper disconnected node: la_data_out[58] +Cell user_analog_project_wrapper disconnected node: la_data_out[59] +Cell user_analog_project_wrapper disconnected node: la_data_out[5] +Cell user_analog_project_wrapper disconnected node: la_data_out[60] +Cell user_analog_project_wrapper disconnected node: la_data_out[61] +Cell user_analog_project_wrapper disconnected node: la_data_out[62] +Cell user_analog_project_wrapper disconnected node: la_data_out[63] +Cell user_analog_project_wrapper disconnected node: la_data_out[64] +Cell user_analog_project_wrapper disconnected node: la_data_out[65] +Cell user_analog_project_wrapper disconnected node: la_data_out[66] +Cell user_analog_project_wrapper disconnected node: la_data_out[67] +Cell user_analog_project_wrapper disconnected node: la_data_out[68] +Cell user_analog_project_wrapper disconnected node: la_data_out[69] +Cell user_analog_project_wrapper disconnected node: la_data_out[6] +Cell user_analog_project_wrapper disconnected node: la_data_out[70] +Cell user_analog_project_wrapper disconnected node: la_data_out[71] +Cell user_analog_project_wrapper disconnected node: la_data_out[72] +Cell user_analog_project_wrapper disconnected node: la_data_out[73] +Cell user_analog_project_wrapper disconnected node: la_data_out[74] +Cell user_analog_project_wrapper disconnected node: la_data_out[75] +Cell user_analog_project_wrapper disconnected node: la_data_out[76] +Cell user_analog_project_wrapper disconnected node: la_data_out[77] +Cell user_analog_project_wrapper disconnected node: la_data_out[78] +Cell user_analog_project_wrapper disconnected node: la_data_out[79] +Cell user_analog_project_wrapper disconnected node: la_data_out[7] +Cell user_analog_project_wrapper disconnected node: la_data_out[80] +Cell user_analog_project_wrapper disconnected node: la_data_out[81] +Cell user_analog_project_wrapper disconnected node: la_data_out[82] +Cell user_analog_project_wrapper disconnected node: la_data_out[83] +Cell user_analog_project_wrapper disconnected node: la_data_out[84] +Cell user_analog_project_wrapper disconnected node: la_data_out[85] +Cell user_analog_project_wrapper disconnected node: la_data_out[86] +Cell user_analog_project_wrapper disconnected node: la_data_out[87] +Cell user_analog_project_wrapper disconnected node: la_data_out[88] +Cell user_analog_project_wrapper disconnected node: la_data_out[89] +Cell user_analog_project_wrapper disconnected node: la_data_out[8] +Cell user_analog_project_wrapper disconnected node: la_data_out[90] +Cell user_analog_project_wrapper disconnected node: la_data_out[91] +Cell user_analog_project_wrapper disconnected node: la_data_out[92] +Cell user_analog_project_wrapper disconnected node: la_data_out[93] +Cell user_analog_project_wrapper disconnected node: la_data_out[94] +Cell user_analog_project_wrapper disconnected node: la_data_out[95] +Cell user_analog_project_wrapper disconnected node: la_data_out[96] +Cell user_analog_project_wrapper disconnected node: la_data_out[97] +Cell user_analog_project_wrapper disconnected node: la_data_out[98] +Cell user_analog_project_wrapper disconnected node: la_data_out[99] +Cell user_analog_project_wrapper disconnected node: la_data_out[9] +Cell user_analog_project_wrapper disconnected node: la_oenb[0] +Cell user_analog_project_wrapper disconnected node: la_oenb[100] +Cell user_analog_project_wrapper disconnected node: la_oenb[101] +Cell user_analog_project_wrapper disconnected node: la_oenb[102] +Cell user_analog_project_wrapper disconnected node: la_oenb[103] +Cell user_analog_project_wrapper disconnected node: la_oenb[104] +Cell user_analog_project_wrapper disconnected node: la_oenb[105] +Cell user_analog_project_wrapper disconnected node: la_oenb[106] +Cell user_analog_project_wrapper disconnected node: la_oenb[107] +Cell user_analog_project_wrapper disconnected node: la_oenb[108] +Cell user_analog_project_wrapper disconnected node: la_oenb[109] +Cell user_analog_project_wrapper disconnected node: la_oenb[10] +Cell user_analog_project_wrapper disconnected node: la_oenb[110] +Cell user_analog_project_wrapper disconnected node: la_oenb[111] +Cell user_analog_project_wrapper disconnected node: la_oenb[112] +Cell user_analog_project_wrapper disconnected node: la_oenb[113] +Cell user_analog_project_wrapper disconnected node: la_oenb[114] +Cell user_analog_project_wrapper disconnected node: la_oenb[115] +Cell user_analog_project_wrapper disconnected node: la_oenb[116] +Cell user_analog_project_wrapper disconnected node: la_oenb[117] +Cell user_analog_project_wrapper disconnected node: la_oenb[118] +Cell user_analog_project_wrapper disconnected node: la_oenb[119] +Cell user_analog_project_wrapper disconnected node: la_oenb[11] +Cell user_analog_project_wrapper disconnected node: la_oenb[120] +Cell user_analog_project_wrapper disconnected node: la_oenb[121] +Cell user_analog_project_wrapper disconnected node: la_oenb[122] +Cell user_analog_project_wrapper disconnected node: la_oenb[123] +Cell user_analog_project_wrapper disconnected node: la_oenb[124] +Cell user_analog_project_wrapper disconnected node: la_oenb[125] +Cell user_analog_project_wrapper disconnected node: la_oenb[126] +Cell user_analog_project_wrapper disconnected node: la_oenb[127] +Cell user_analog_project_wrapper disconnected node: la_oenb[12] +Cell user_analog_project_wrapper disconnected node: la_oenb[13] +Cell user_analog_project_wrapper disconnected node: la_oenb[14] +Cell user_analog_project_wrapper disconnected node: la_oenb[15] +Cell user_analog_project_wrapper disconnected node: la_oenb[16] +Cell user_analog_project_wrapper disconnected node: la_oenb[17] +Cell user_analog_project_wrapper disconnected node: la_oenb[18] +Cell user_analog_project_wrapper disconnected node: la_oenb[19] +Cell user_analog_project_wrapper disconnected node: la_oenb[1] +Cell user_analog_project_wrapper disconnected node: la_oenb[20] +Cell user_analog_project_wrapper disconnected node: la_oenb[21] +Cell user_analog_project_wrapper disconnected node: la_oenb[22] +Cell user_analog_project_wrapper disconnected node: la_oenb[23] +Cell user_analog_project_wrapper disconnected node: la_oenb[24] +Cell user_analog_project_wrapper disconnected node: la_oenb[25] +Cell user_analog_project_wrapper disconnected node: la_oenb[26] +Cell user_analog_project_wrapper disconnected node: la_oenb[27] +Cell user_analog_project_wrapper disconnected node: la_oenb[28] +Cell user_analog_project_wrapper disconnected node: la_oenb[29] +Cell user_analog_project_wrapper disconnected node: la_oenb[2] +Cell user_analog_project_wrapper disconnected node: la_oenb[30] +Cell user_analog_project_wrapper disconnected node: la_oenb[31] +Cell user_analog_project_wrapper disconnected node: la_oenb[32] +Cell user_analog_project_wrapper disconnected node: la_oenb[33] +Cell user_analog_project_wrapper disconnected node: la_oenb[34] +Cell user_analog_project_wrapper disconnected node: la_oenb[35] +Cell user_analog_project_wrapper disconnected node: la_oenb[36] +Cell user_analog_project_wrapper disconnected node: la_oenb[37] +Cell user_analog_project_wrapper disconnected node: la_oenb[38] +Cell user_analog_project_wrapper disconnected node: la_oenb[39] +Cell user_analog_project_wrapper disconnected node: la_oenb[3] +Cell user_analog_project_wrapper disconnected node: la_oenb[40] +Cell user_analog_project_wrapper disconnected node: la_oenb[41] +Cell user_analog_project_wrapper disconnected node: la_oenb[42] +Cell user_analog_project_wrapper disconnected node: la_oenb[43] +Cell user_analog_project_wrapper disconnected node: la_oenb[44] +Cell user_analog_project_wrapper disconnected node: la_oenb[45] +Cell user_analog_project_wrapper disconnected node: la_oenb[46] +Cell user_analog_project_wrapper disconnected node: la_oenb[47] +Cell user_analog_project_wrapper disconnected node: la_oenb[48] +Cell user_analog_project_wrapper disconnected node: la_oenb[49] +Cell user_analog_project_wrapper disconnected node: la_oenb[4] +Cell user_analog_project_wrapper disconnected node: la_oenb[50] +Cell user_analog_project_wrapper disconnected node: la_oenb[51] +Cell user_analog_project_wrapper disconnected node: la_oenb[52] +Cell user_analog_project_wrapper disconnected node: la_oenb[53] +Cell user_analog_project_wrapper disconnected node: la_oenb[54] +Cell user_analog_project_wrapper disconnected node: la_oenb[55] +Cell user_analog_project_wrapper disconnected node: la_oenb[56] +Cell user_analog_project_wrapper disconnected node: la_oenb[57] +Cell user_analog_project_wrapper disconnected node: la_oenb[58] +Cell user_analog_project_wrapper disconnected node: la_oenb[59] +Cell user_analog_project_wrapper disconnected node: la_oenb[5] +Cell user_analog_project_wrapper disconnected node: la_oenb[60] +Cell user_analog_project_wrapper disconnected node: la_oenb[61] +Cell user_analog_project_wrapper disconnected node: la_oenb[62] +Cell user_analog_project_wrapper disconnected node: la_oenb[63] +Cell user_analog_project_wrapper disconnected node: la_oenb[64] +Cell user_analog_project_wrapper disconnected node: la_oenb[65] +Cell user_analog_project_wrapper disconnected node: la_oenb[66] +Cell user_analog_project_wrapper disconnected node: la_oenb[67] +Cell user_analog_project_wrapper disconnected node: la_oenb[68] +Cell user_analog_project_wrapper disconnected node: la_oenb[69] +Cell user_analog_project_wrapper disconnected node: la_oenb[6] +Cell user_analog_project_wrapper disconnected node: la_oenb[70] +Cell user_analog_project_wrapper disconnected node: la_oenb[71] +Cell user_analog_project_wrapper disconnected node: la_oenb[72] +Cell user_analog_project_wrapper disconnected node: la_oenb[73] +Cell user_analog_project_wrapper disconnected node: la_oenb[74] +Cell user_analog_project_wrapper disconnected node: la_oenb[75] +Cell user_analog_project_wrapper disconnected node: la_oenb[76] +Cell user_analog_project_wrapper disconnected node: la_oenb[77] +Cell user_analog_project_wrapper disconnected node: la_oenb[78] +Cell user_analog_project_wrapper disconnected node: la_oenb[79] +Cell user_analog_project_wrapper disconnected node: la_oenb[7] +Cell user_analog_project_wrapper disconnected node: la_oenb[80] +Cell user_analog_project_wrapper disconnected node: la_oenb[81] +Cell user_analog_project_wrapper disconnected node: la_oenb[82] +Cell user_analog_project_wrapper disconnected node: la_oenb[83] +Cell user_analog_project_wrapper disconnected node: la_oenb[84] +Cell user_analog_project_wrapper disconnected node: la_oenb[85] +Cell user_analog_project_wrapper disconnected node: la_oenb[86] +Cell user_analog_project_wrapper disconnected node: la_oenb[87] +Cell user_analog_project_wrapper disconnected node: la_oenb[88] +Cell user_analog_project_wrapper disconnected node: la_oenb[89] +Cell user_analog_project_wrapper disconnected node: la_oenb[8] +Cell user_analog_project_wrapper disconnected node: la_oenb[90] +Cell user_analog_project_wrapper disconnected node: la_oenb[91] +Cell user_analog_project_wrapper disconnected node: la_oenb[92] +Cell user_analog_project_wrapper disconnected node: la_oenb[93] +Cell user_analog_project_wrapper disconnected node: la_oenb[94] +Cell user_analog_project_wrapper disconnected node: la_oenb[95] +Cell user_analog_project_wrapper disconnected node: la_oenb[96] +Cell user_analog_project_wrapper disconnected node: la_oenb[97] +Cell user_analog_project_wrapper disconnected node: la_oenb[98] +Cell user_analog_project_wrapper disconnected node: la_oenb[99] +Cell user_analog_project_wrapper disconnected node: la_oenb[9] +Cell user_analog_project_wrapper disconnected node: user_clock2 +Cell user_analog_project_wrapper disconnected node: user_irq[0] +Cell user_analog_project_wrapper disconnected node: user_irq[1] +Cell user_analog_project_wrapper disconnected node: user_irq[2] +Cell user_analog_project_wrapper disconnected node: wb_clk_i +Cell user_analog_project_wrapper disconnected node: wb_rst_i +Cell user_analog_project_wrapper disconnected node: wbs_ack_o +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[0] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[10] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[11] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[12] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[13] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[14] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[15] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[16] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[17] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[18] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[19] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[1] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[20] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[21] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[22] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[23] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[24] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[25] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[26] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[27] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[28] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[29] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[2] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[30] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[31] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[3] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[4] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[5] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[6] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[7] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[8] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[9] +Cell user_analog_project_wrapper disconnected node: wbs_cyc_i +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[0] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[10] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[11] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[12] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[13] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[14] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[15] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[16] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[17] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[18] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[19] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[1] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[20] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[21] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[22] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[23] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[24] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[25] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[26] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[27] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[28] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[29] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[2] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[30] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[31] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[3] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[4] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[5] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[6] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[7] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[8] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[9] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[0] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[10] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[11] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[12] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[13] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[14] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[15] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[16] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[17] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[18] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[19] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[1] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[20] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[21] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[22] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[23] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[24] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[25] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[26] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[27] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[28] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[29] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[2] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[30] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[31] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[3] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[4] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[5] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[6] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[7] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[8] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[9] +Cell user_analog_project_wrapper disconnected node: wbs_sel_i[0] +Cell user_analog_project_wrapper disconnected node: wbs_sel_i[1] +Cell user_analog_project_wrapper disconnected node: wbs_sel_i[2] +Cell user_analog_project_wrapper disconnected node: wbs_sel_i[3] +Cell user_analog_project_wrapper disconnected node: wbs_stb_i +Cell user_analog_project_wrapper disconnected node: wbs_we_i + +Cell user_analog_project_wrapper disconnected node: wb_clk_i +Cell user_analog_project_wrapper disconnected node: wb_rst_i +Cell user_analog_project_wrapper disconnected node: wbs_stb_i +Cell user_analog_project_wrapper disconnected node: wbs_cyc_i +Cell user_analog_project_wrapper disconnected node: wbs_we_i +Cell user_analog_project_wrapper disconnected node: wbs_sel_i[3] +Cell user_analog_project_wrapper disconnected node: wbs_sel_i[2] +Cell user_analog_project_wrapper disconnected node: wbs_sel_i[1] +Cell user_analog_project_wrapper disconnected node: wbs_sel_i[0] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[31] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[30] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[29] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[28] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[27] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[26] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[25] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[24] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[23] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[22] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[21] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[20] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[19] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[18] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[17] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[16] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[15] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[14] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[13] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[12] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[11] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[10] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[9] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[8] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[7] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[6] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[5] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[4] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[3] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[2] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[1] +Cell user_analog_project_wrapper disconnected node: wbs_dat_i[0] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[31] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[30] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[29] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[28] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[27] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[26] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[25] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[24] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[23] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[22] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[21] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[20] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[19] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[18] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[17] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[16] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[15] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[14] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[13] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[12] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[11] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[10] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[9] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[8] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[7] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[6] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[5] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[4] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[3] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[2] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[1] +Cell user_analog_project_wrapper disconnected node: wbs_adr_i[0] +Cell user_analog_project_wrapper disconnected node: wbs_ack_o +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[31] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[30] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[29] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[28] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[27] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[26] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[25] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[24] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[23] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[22] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[21] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[20] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[19] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[18] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[17] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[16] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[15] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[14] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[13] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[12] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[11] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[10] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[9] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[8] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[7] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[6] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[5] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[4] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[3] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[2] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[1] +Cell user_analog_project_wrapper disconnected node: wbs_dat_o[0] +Cell user_analog_project_wrapper disconnected node: la_data_in[127] +Cell user_analog_project_wrapper disconnected node: la_data_in[126] +Cell user_analog_project_wrapper disconnected node: la_data_in[125] +Cell user_analog_project_wrapper disconnected node: la_data_in[124] +Cell user_analog_project_wrapper disconnected node: la_data_in[123] +Cell user_analog_project_wrapper disconnected node: la_data_in[122] +Cell user_analog_project_wrapper disconnected node: la_data_in[121] +Cell user_analog_project_wrapper disconnected node: la_data_in[120] +Cell user_analog_project_wrapper disconnected node: la_data_in[119] +Cell user_analog_project_wrapper disconnected node: la_data_in[118] +Cell user_analog_project_wrapper disconnected node: la_data_in[117] +Cell user_analog_project_wrapper disconnected node: la_data_in[116] +Cell user_analog_project_wrapper disconnected node: la_data_in[115] +Cell user_analog_project_wrapper disconnected node: la_data_in[114] +Cell user_analog_project_wrapper disconnected node: la_data_in[113] +Cell user_analog_project_wrapper disconnected node: la_data_in[112] +Cell user_analog_project_wrapper disconnected node: la_data_in[111] +Cell user_analog_project_wrapper disconnected node: la_data_in[110] +Cell user_analog_project_wrapper disconnected node: la_data_in[109] +Cell user_analog_project_wrapper disconnected node: la_data_in[108] +Cell user_analog_project_wrapper disconnected node: la_data_in[107] +Cell user_analog_project_wrapper disconnected node: la_data_in[106] +Cell user_analog_project_wrapper disconnected node: la_data_in[105] +Cell user_analog_project_wrapper disconnected node: la_data_in[104] +Cell user_analog_project_wrapper disconnected node: la_data_in[103] +Cell user_analog_project_wrapper disconnected node: la_data_in[102] +Cell user_analog_project_wrapper disconnected node: la_data_in[101] +Cell user_analog_project_wrapper disconnected node: la_data_in[100] +Cell user_analog_project_wrapper disconnected node: la_data_in[99] +Cell user_analog_project_wrapper disconnected node: la_data_in[98] +Cell user_analog_project_wrapper disconnected node: la_data_in[97] +Cell user_analog_project_wrapper disconnected node: la_data_in[96] +Cell user_analog_project_wrapper disconnected node: la_data_in[95] +Cell user_analog_project_wrapper disconnected node: la_data_in[94] +Cell user_analog_project_wrapper disconnected node: la_data_in[93] +Cell user_analog_project_wrapper disconnected node: la_data_in[92] +Cell user_analog_project_wrapper disconnected node: la_data_in[91] +Cell user_analog_project_wrapper disconnected node: la_data_in[90] +Cell user_analog_project_wrapper disconnected node: la_data_in[89] +Cell user_analog_project_wrapper disconnected node: la_data_in[88] +Cell user_analog_project_wrapper disconnected node: la_data_in[87] +Cell user_analog_project_wrapper disconnected node: la_data_in[86] +Cell user_analog_project_wrapper disconnected node: la_data_in[85] +Cell user_analog_project_wrapper disconnected node: la_data_in[84] +Cell user_analog_project_wrapper disconnected node: la_data_in[83] +Cell user_analog_project_wrapper disconnected node: la_data_in[82] +Cell user_analog_project_wrapper disconnected node: la_data_in[81] +Cell user_analog_project_wrapper disconnected node: la_data_in[80] +Cell user_analog_project_wrapper disconnected node: la_data_in[79] +Cell user_analog_project_wrapper disconnected node: la_data_in[78] +Cell user_analog_project_wrapper disconnected node: la_data_in[77] +Cell user_analog_project_wrapper disconnected node: la_data_in[76] +Cell user_analog_project_wrapper disconnected node: la_data_in[75] +Cell user_analog_project_wrapper disconnected node: la_data_in[74] +Cell user_analog_project_wrapper disconnected node: la_data_in[73] +Cell user_analog_project_wrapper disconnected node: la_data_in[72] +Cell user_analog_project_wrapper disconnected node: la_data_in[71] +Cell user_analog_project_wrapper disconnected node: la_data_in[70] +Cell user_analog_project_wrapper disconnected node: la_data_in[69] +Cell user_analog_project_wrapper disconnected node: la_data_in[68] +Cell user_analog_project_wrapper disconnected node: la_data_in[67] +Cell user_analog_project_wrapper disconnected node: la_data_in[66] +Cell user_analog_project_wrapper disconnected node: la_data_in[65] +Cell user_analog_project_wrapper disconnected node: la_data_in[64] +Cell user_analog_project_wrapper disconnected node: la_data_in[63] +Cell user_analog_project_wrapper disconnected node: la_data_in[62] +Cell user_analog_project_wrapper disconnected node: la_data_in[61] +Cell user_analog_project_wrapper disconnected node: la_data_in[60] +Cell user_analog_project_wrapper disconnected node: la_data_in[59] +Cell user_analog_project_wrapper disconnected node: la_data_in[58] +Cell user_analog_project_wrapper disconnected node: la_data_in[57] +Cell user_analog_project_wrapper disconnected node: la_data_in[56] +Cell user_analog_project_wrapper disconnected node: la_data_in[55] +Cell user_analog_project_wrapper disconnected node: la_data_in[54] +Cell user_analog_project_wrapper disconnected node: la_data_in[53] +Cell user_analog_project_wrapper disconnected node: la_data_in[52] +Cell user_analog_project_wrapper disconnected node: la_data_in[51] +Cell user_analog_project_wrapper disconnected node: la_data_in[50] +Cell user_analog_project_wrapper disconnected node: la_data_in[49] +Cell user_analog_project_wrapper disconnected node: la_data_in[48] +Cell user_analog_project_wrapper disconnected node: la_data_in[47] +Cell user_analog_project_wrapper disconnected node: la_data_in[46] +Cell user_analog_project_wrapper disconnected node: la_data_in[45] +Cell user_analog_project_wrapper disconnected node: la_data_in[44] +Cell user_analog_project_wrapper disconnected node: la_data_in[43] +Cell user_analog_project_wrapper disconnected node: la_data_in[42] +Cell user_analog_project_wrapper disconnected node: la_data_in[41] +Cell user_analog_project_wrapper disconnected node: la_data_in[40] +Cell user_analog_project_wrapper disconnected node: la_data_in[39] +Cell user_analog_project_wrapper disconnected node: la_data_in[38] +Cell user_analog_project_wrapper disconnected node: la_data_in[37] +Cell user_analog_project_wrapper disconnected node: la_data_in[36] +Cell user_analog_project_wrapper disconnected node: la_data_in[35] +Cell user_analog_project_wrapper disconnected node: la_data_in[34] +Cell user_analog_project_wrapper disconnected node: la_data_in[33] +Cell user_analog_project_wrapper disconnected node: la_data_in[32] +Cell user_analog_project_wrapper disconnected node: la_data_in[31] +Cell user_analog_project_wrapper disconnected node: la_data_in[30] +Cell user_analog_project_wrapper disconnected node: la_data_in[29] +Cell user_analog_project_wrapper disconnected node: la_data_in[28] +Cell user_analog_project_wrapper disconnected node: la_data_in[27] +Cell user_analog_project_wrapper disconnected node: la_data_in[26] +Cell user_analog_project_wrapper disconnected node: la_data_in[25] +Cell user_analog_project_wrapper disconnected node: la_data_in[24] +Cell user_analog_project_wrapper disconnected node: la_data_in[23] +Cell user_analog_project_wrapper disconnected node: la_data_in[22] +Cell user_analog_project_wrapper disconnected node: la_data_in[21] +Cell user_analog_project_wrapper disconnected node: la_data_in[20] +Cell user_analog_project_wrapper disconnected node: la_data_in[19] +Cell user_analog_project_wrapper disconnected node: la_data_in[18] +Cell user_analog_project_wrapper disconnected node: la_data_in[17] +Cell user_analog_project_wrapper disconnected node: la_data_in[16] +Cell user_analog_project_wrapper disconnected node: la_data_in[15] +Cell user_analog_project_wrapper disconnected node: la_data_in[14] +Cell user_analog_project_wrapper disconnected node: la_data_in[13] +Cell user_analog_project_wrapper disconnected node: la_data_in[12] +Cell user_analog_project_wrapper disconnected node: la_data_in[11] +Cell user_analog_project_wrapper disconnected node: la_data_in[10] +Cell user_analog_project_wrapper disconnected node: la_data_in[9] +Cell user_analog_project_wrapper disconnected node: la_data_in[8] +Cell user_analog_project_wrapper disconnected node: la_data_in[7] +Cell user_analog_project_wrapper disconnected node: la_data_in[6] +Cell user_analog_project_wrapper disconnected node: la_data_in[5] +Cell user_analog_project_wrapper disconnected node: la_data_in[4] +Cell user_analog_project_wrapper disconnected node: la_data_in[3] +Cell user_analog_project_wrapper disconnected node: la_data_in[2] +Cell user_analog_project_wrapper disconnected node: la_data_in[1] +Cell user_analog_project_wrapper disconnected node: la_data_in[0] +Cell user_analog_project_wrapper disconnected node: la_data_out[127] +Cell user_analog_project_wrapper disconnected node: la_data_out[126] +Cell user_analog_project_wrapper disconnected node: la_data_out[125] +Cell user_analog_project_wrapper disconnected node: la_data_out[124] +Cell user_analog_project_wrapper disconnected node: la_data_out[123] +Cell user_analog_project_wrapper disconnected node: la_data_out[122] +Cell user_analog_project_wrapper disconnected node: la_data_out[121] +Cell user_analog_project_wrapper disconnected node: la_data_out[120] +Cell user_analog_project_wrapper disconnected node: la_data_out[119] +Cell user_analog_project_wrapper disconnected node: la_data_out[118] +Cell user_analog_project_wrapper disconnected node: la_data_out[117] +Cell user_analog_project_wrapper disconnected node: la_data_out[116] +Cell user_analog_project_wrapper disconnected node: la_data_out[115] +Cell user_analog_project_wrapper disconnected node: la_data_out[114] +Cell user_analog_project_wrapper disconnected node: la_data_out[113] +Cell user_analog_project_wrapper disconnected node: la_data_out[112] +Cell user_analog_project_wrapper disconnected node: la_data_out[111] +Cell user_analog_project_wrapper disconnected node: la_data_out[110] +Cell user_analog_project_wrapper disconnected node: la_data_out[109] +Cell user_analog_project_wrapper disconnected node: la_data_out[108] +Cell user_analog_project_wrapper disconnected node: la_data_out[107] +Cell user_analog_project_wrapper disconnected node: la_data_out[106] +Cell user_analog_project_wrapper disconnected node: la_data_out[105] +Cell user_analog_project_wrapper disconnected node: la_data_out[104] +Cell user_analog_project_wrapper disconnected node: la_data_out[103] +Cell user_analog_project_wrapper disconnected node: la_data_out[102] +Cell user_analog_project_wrapper disconnected node: la_data_out[101] +Cell user_analog_project_wrapper disconnected node: la_data_out[100] +Cell user_analog_project_wrapper disconnected node: la_data_out[99] +Cell user_analog_project_wrapper disconnected node: la_data_out[98] +Cell user_analog_project_wrapper disconnected node: la_data_out[97] +Cell user_analog_project_wrapper disconnected node: la_data_out[96] +Cell user_analog_project_wrapper disconnected node: la_data_out[95] +Cell user_analog_project_wrapper disconnected node: la_data_out[94] +Cell user_analog_project_wrapper disconnected node: la_data_out[93] +Cell user_analog_project_wrapper disconnected node: la_data_out[92] +Cell user_analog_project_wrapper disconnected node: la_data_out[91] +Cell user_analog_project_wrapper disconnected node: la_data_out[90] +Cell user_analog_project_wrapper disconnected node: la_data_out[89] +Cell user_analog_project_wrapper disconnected node: la_data_out[88] +Cell user_analog_project_wrapper disconnected node: la_data_out[87] +Cell user_analog_project_wrapper disconnected node: la_data_out[86] +Cell user_analog_project_wrapper disconnected node: la_data_out[85] +Cell user_analog_project_wrapper disconnected node: la_data_out[84] +Cell user_analog_project_wrapper disconnected node: la_data_out[83] +Cell user_analog_project_wrapper disconnected node: la_data_out[82] +Cell user_analog_project_wrapper disconnected node: la_data_out[81] +Cell user_analog_project_wrapper disconnected node: la_data_out[80] +Cell user_analog_project_wrapper disconnected node: la_data_out[79] +Cell user_analog_project_wrapper disconnected node: la_data_out[78] +Cell user_analog_project_wrapper disconnected node: la_data_out[77] +Cell user_analog_project_wrapper disconnected node: la_data_out[76] +Cell user_analog_project_wrapper disconnected node: la_data_out[75] +Cell user_analog_project_wrapper disconnected node: la_data_out[74] +Cell user_analog_project_wrapper disconnected node: la_data_out[73] +Cell user_analog_project_wrapper disconnected node: la_data_out[72] +Cell user_analog_project_wrapper disconnected node: la_data_out[71] +Cell user_analog_project_wrapper disconnected node: la_data_out[70] +Cell user_analog_project_wrapper disconnected node: la_data_out[69] +Cell user_analog_project_wrapper disconnected node: la_data_out[68] +Cell user_analog_project_wrapper disconnected node: la_data_out[67] +Cell user_analog_project_wrapper disconnected node: la_data_out[66] +Cell user_analog_project_wrapper disconnected node: la_data_out[65] +Cell user_analog_project_wrapper disconnected node: la_data_out[64] +Cell user_analog_project_wrapper disconnected node: la_data_out[63] +Cell user_analog_project_wrapper disconnected node: la_data_out[62] +Cell user_analog_project_wrapper disconnected node: la_data_out[61] +Cell user_analog_project_wrapper disconnected node: la_data_out[60] +Cell user_analog_project_wrapper disconnected node: la_data_out[59] +Cell user_analog_project_wrapper disconnected node: la_data_out[58] +Cell user_analog_project_wrapper disconnected node: la_data_out[57] +Cell user_analog_project_wrapper disconnected node: la_data_out[56] +Cell user_analog_project_wrapper disconnected node: la_data_out[55] +Cell user_analog_project_wrapper disconnected node: la_data_out[54] +Cell user_analog_project_wrapper disconnected node: la_data_out[53] +Cell user_analog_project_wrapper disconnected node: la_data_out[52] +Cell user_analog_project_wrapper disconnected node: la_data_out[51] +Cell user_analog_project_wrapper disconnected node: la_data_out[50] +Cell user_analog_project_wrapper disconnected node: la_data_out[49] +Cell user_analog_project_wrapper disconnected node: la_data_out[48] +Cell user_analog_project_wrapper disconnected node: la_data_out[47] +Cell user_analog_project_wrapper disconnected node: la_data_out[46] +Cell user_analog_project_wrapper disconnected node: la_data_out[45] +Cell user_analog_project_wrapper disconnected node: la_data_out[44] +Cell user_analog_project_wrapper disconnected node: la_data_out[43] +Cell user_analog_project_wrapper disconnected node: la_data_out[42] +Cell user_analog_project_wrapper disconnected node: la_data_out[41] +Cell user_analog_project_wrapper disconnected node: la_data_out[40] +Cell user_analog_project_wrapper disconnected node: la_data_out[39] +Cell user_analog_project_wrapper disconnected node: la_data_out[38] +Cell user_analog_project_wrapper disconnected node: la_data_out[37] +Cell user_analog_project_wrapper disconnected node: la_data_out[36] +Cell user_analog_project_wrapper disconnected node: la_data_out[35] +Cell user_analog_project_wrapper disconnected node: la_data_out[34] +Cell user_analog_project_wrapper disconnected node: la_data_out[33] +Cell user_analog_project_wrapper disconnected node: la_data_out[32] +Cell user_analog_project_wrapper disconnected node: la_data_out[31] +Cell user_analog_project_wrapper disconnected node: la_data_out[30] +Cell user_analog_project_wrapper disconnected node: la_data_out[29] +Cell user_analog_project_wrapper disconnected node: la_data_out[28] +Cell user_analog_project_wrapper disconnected node: la_data_out[27] +Cell user_analog_project_wrapper disconnected node: la_data_out[26] +Cell user_analog_project_wrapper disconnected node: la_data_out[25] +Cell user_analog_project_wrapper disconnected node: la_data_out[24] +Cell user_analog_project_wrapper disconnected node: la_data_out[23] +Cell user_analog_project_wrapper disconnected node: la_data_out[22] +Cell user_analog_project_wrapper disconnected node: la_data_out[21] +Cell user_analog_project_wrapper disconnected node: la_data_out[20] +Cell user_analog_project_wrapper disconnected node: la_data_out[19] +Cell user_analog_project_wrapper disconnected node: la_data_out[18] +Cell user_analog_project_wrapper disconnected node: la_data_out[17] +Cell user_analog_project_wrapper disconnected node: la_data_out[16] +Cell user_analog_project_wrapper disconnected node: la_data_out[15] +Cell user_analog_project_wrapper disconnected node: la_data_out[14] +Cell user_analog_project_wrapper disconnected node: la_data_out[13] +Cell user_analog_project_wrapper disconnected node: la_data_out[12] +Cell user_analog_project_wrapper disconnected node: la_data_out[11] +Cell user_analog_project_wrapper disconnected node: la_data_out[10] +Cell user_analog_project_wrapper disconnected node: la_data_out[9] +Cell user_analog_project_wrapper disconnected node: la_data_out[8] +Cell user_analog_project_wrapper disconnected node: la_data_out[7] +Cell user_analog_project_wrapper disconnected node: la_data_out[6] +Cell user_analog_project_wrapper disconnected node: la_data_out[5] +Cell user_analog_project_wrapper disconnected node: la_data_out[4] +Cell user_analog_project_wrapper disconnected node: la_data_out[3] +Cell user_analog_project_wrapper disconnected node: la_data_out[2] +Cell user_analog_project_wrapper disconnected node: la_data_out[1] +Cell user_analog_project_wrapper disconnected node: la_data_out[0] +Cell user_analog_project_wrapper disconnected node: io_in[26] +Cell user_analog_project_wrapper disconnected node: io_in[25] +Cell user_analog_project_wrapper disconnected node: io_in[24] +Cell user_analog_project_wrapper disconnected node: io_in[23] +Cell user_analog_project_wrapper disconnected node: io_in[22] +Cell user_analog_project_wrapper disconnected node: io_in[21] +Cell user_analog_project_wrapper disconnected node: io_in[20] +Cell user_analog_project_wrapper disconnected node: io_in[19] +Cell user_analog_project_wrapper disconnected node: io_in[18] +Cell user_analog_project_wrapper disconnected node: io_in[17] +Cell user_analog_project_wrapper disconnected node: io_in[16] +Cell user_analog_project_wrapper disconnected node: io_in[15] +Cell user_analog_project_wrapper disconnected node: io_in[14] +Cell user_analog_project_wrapper disconnected node: io_in[13] +Cell user_analog_project_wrapper disconnected node: io_in[12] +Cell user_analog_project_wrapper disconnected node: io_in[11] +Cell user_analog_project_wrapper disconnected node: io_in[10] +Cell user_analog_project_wrapper disconnected node: io_in[9] +Cell user_analog_project_wrapper disconnected node: io_in[8] +Cell user_analog_project_wrapper disconnected node: io_in[7] +Cell user_analog_project_wrapper disconnected node: io_in[6] +Cell user_analog_project_wrapper disconnected node: io_in[5] +Cell user_analog_project_wrapper disconnected node: io_in[4] +Cell user_analog_project_wrapper disconnected node: io_in[3] +Cell user_analog_project_wrapper disconnected node: io_in[2] +Cell user_analog_project_wrapper disconnected node: io_in[1] +Cell user_analog_project_wrapper disconnected node: io_in[0] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[26] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[25] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[24] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[23] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[22] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[21] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[20] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[19] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[18] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[17] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[16] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[15] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[14] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[13] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[12] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[11] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[10] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[9] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[8] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[7] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[6] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[5] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[4] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[3] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[2] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[1] +Cell user_analog_project_wrapper disconnected node: io_in_3v3[0] +Cell user_analog_project_wrapper disconnected node: user_clock2 +Cell user_analog_project_wrapper disconnected node: io_out[26] +Cell user_analog_project_wrapper disconnected node: io_out[25] +Cell user_analog_project_wrapper disconnected node: io_out[24] +Cell user_analog_project_wrapper disconnected node: io_out[23] +Cell user_analog_project_wrapper disconnected node: io_out[22] +Cell user_analog_project_wrapper disconnected node: io_out[21] +Cell user_analog_project_wrapper disconnected node: io_out[20] +Cell user_analog_project_wrapper disconnected node: io_out[19] +Cell user_analog_project_wrapper disconnected node: io_out[18] +Cell user_analog_project_wrapper disconnected node: io_out[17] +Cell user_analog_project_wrapper disconnected node: io_out[16] +Cell user_analog_project_wrapper disconnected node: io_out[15] +Cell user_analog_project_wrapper disconnected node: io_out[14] +Cell user_analog_project_wrapper disconnected node: io_out[13] +Cell user_analog_project_wrapper disconnected node: io_out[12] +Cell user_analog_project_wrapper disconnected node: io_out[11] +Cell user_analog_project_wrapper disconnected node: io_out[10] +Cell user_analog_project_wrapper disconnected node: io_out[9] +Cell user_analog_project_wrapper disconnected node: io_out[8] +Cell user_analog_project_wrapper disconnected node: io_out[7] +Cell user_analog_project_wrapper disconnected node: io_out[6] +Cell user_analog_project_wrapper disconnected node: io_out[5] +Cell user_analog_project_wrapper disconnected node: io_out[4] +Cell user_analog_project_wrapper disconnected node: io_out[3] +Cell user_analog_project_wrapper disconnected node: io_out[2] +Cell user_analog_project_wrapper disconnected node: io_out[1] +Cell user_analog_project_wrapper disconnected node: io_out[0] +Cell user_analog_project_wrapper disconnected node: io_oeb[26] +Cell user_analog_project_wrapper disconnected node: io_oeb[25] +Cell user_analog_project_wrapper disconnected node: io_oeb[24] +Cell user_analog_project_wrapper disconnected node: io_oeb[23] +Cell user_analog_project_wrapper disconnected node: io_oeb[22] +Cell user_analog_project_wrapper disconnected node: io_oeb[21] +Cell user_analog_project_wrapper disconnected node: io_oeb[20] +Cell user_analog_project_wrapper disconnected node: io_oeb[19] +Cell user_analog_project_wrapper disconnected node: io_oeb[18] +Cell user_analog_project_wrapper disconnected node: io_oeb[17] +Cell user_analog_project_wrapper disconnected node: io_oeb[16] +Cell user_analog_project_wrapper disconnected node: io_oeb[15] +Cell user_analog_project_wrapper disconnected node: io_oeb[14] +Cell user_analog_project_wrapper disconnected node: io_oeb[13] +Cell user_analog_project_wrapper disconnected node: io_oeb[12] +Cell user_analog_project_wrapper disconnected node: io_oeb[11] +Cell user_analog_project_wrapper disconnected node: io_oeb[10] +Cell user_analog_project_wrapper disconnected node: io_oeb[9] +Cell user_analog_project_wrapper disconnected node: io_oeb[8] +Cell user_analog_project_wrapper disconnected node: io_oeb[7] +Cell user_analog_project_wrapper disconnected node: io_oeb[6] +Cell user_analog_project_wrapper disconnected node: io_oeb[5] +Cell user_analog_project_wrapper disconnected node: io_oeb[4] +Cell user_analog_project_wrapper disconnected node: io_oeb[3] +Cell user_analog_project_wrapper disconnected node: io_oeb[2] +Cell user_analog_project_wrapper disconnected node: io_oeb[1] +Cell user_analog_project_wrapper disconnected node: io_oeb[0] +Cell user_analog_project_wrapper disconnected node: gpio_analog[17] +Cell user_analog_project_wrapper disconnected node: gpio_analog[16] +Cell user_analog_project_wrapper disconnected node: gpio_analog[15] +Cell user_analog_project_wrapper disconnected node: gpio_analog[14] +Cell user_analog_project_wrapper disconnected node: gpio_analog[13] +Cell user_analog_project_wrapper disconnected node: gpio_analog[12] +Cell user_analog_project_wrapper disconnected node: gpio_analog[11] +Cell user_analog_project_wrapper disconnected node: gpio_analog[10] +Cell user_analog_project_wrapper disconnected node: gpio_analog[9] +Cell user_analog_project_wrapper disconnected node: gpio_analog[8] +Cell user_analog_project_wrapper disconnected node: gpio_analog[7] +Cell user_analog_project_wrapper disconnected node: gpio_analog[6] +Cell user_analog_project_wrapper disconnected node: gpio_analog[5] +Cell user_analog_project_wrapper disconnected node: gpio_analog[4] +Cell user_analog_project_wrapper disconnected node: gpio_analog[3] +Cell user_analog_project_wrapper disconnected node: gpio_analog[2] +Cell user_analog_project_wrapper disconnected node: gpio_analog[1] +Cell user_analog_project_wrapper disconnected node: gpio_analog[0] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[17] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[16] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[15] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[14] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[13] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[12] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[11] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[10] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[9] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[8] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[7] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[6] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[5] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[4] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[3] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[2] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[1] +Cell user_analog_project_wrapper disconnected node: gpio_noesd[0] +Cell user_analog_project_wrapper disconnected node: io_analog[9] +Cell user_analog_project_wrapper disconnected node: io_clamp_high[2] +Cell user_analog_project_wrapper disconnected node: io_clamp_high[1] +Cell user_analog_project_wrapper disconnected node: io_clamp_high[0] +Cell user_analog_project_wrapper disconnected node: io_clamp_low[2] +Cell user_analog_project_wrapper disconnected node: io_clamp_low[1] +Cell user_analog_project_wrapper disconnected node: io_clamp_low[0] +Cell user_analog_project_wrapper disconnected node: user_irq[2] +Cell user_analog_project_wrapper disconnected node: user_irq[1] +Cell user_analog_project_wrapper disconnected node: user_irq[0] +Cell user_analog_project_wrapper disconnected node: la_oenb[127] +Cell user_analog_project_wrapper disconnected node: la_oenb[126] +Cell user_analog_project_wrapper disconnected node: la_oenb[125] +Cell user_analog_project_wrapper disconnected node: la_oenb[124] +Cell user_analog_project_wrapper disconnected node: la_oenb[123] +Cell user_analog_project_wrapper disconnected node: la_oenb[122] +Cell user_analog_project_wrapper disconnected node: la_oenb[121] +Cell user_analog_project_wrapper disconnected node: la_oenb[120] +Cell user_analog_project_wrapper disconnected node: la_oenb[119] +Cell user_analog_project_wrapper disconnected node: la_oenb[118] +Cell user_analog_project_wrapper disconnected node: la_oenb[117] +Cell user_analog_project_wrapper disconnected node: la_oenb[116] +Cell user_analog_project_wrapper disconnected node: la_oenb[115] +Cell user_analog_project_wrapper disconnected node: la_oenb[114] +Cell user_analog_project_wrapper disconnected node: la_oenb[113] +Cell user_analog_project_wrapper disconnected node: la_oenb[112] +Cell user_analog_project_wrapper disconnected node: la_oenb[111] +Cell user_analog_project_wrapper disconnected node: la_oenb[110] +Cell user_analog_project_wrapper disconnected node: la_oenb[109] +Cell user_analog_project_wrapper disconnected node: la_oenb[108] +Cell user_analog_project_wrapper disconnected node: la_oenb[107] +Cell user_analog_project_wrapper disconnected node: la_oenb[106] +Cell user_analog_project_wrapper disconnected node: la_oenb[105] +Cell user_analog_project_wrapper disconnected node: la_oenb[104] +Cell user_analog_project_wrapper disconnected node: la_oenb[103] +Cell user_analog_project_wrapper disconnected node: la_oenb[102] +Cell user_analog_project_wrapper disconnected node: la_oenb[101] +Cell user_analog_project_wrapper disconnected node: la_oenb[100] +Cell user_analog_project_wrapper disconnected node: la_oenb[99] +Cell user_analog_project_wrapper disconnected node: la_oenb[98] +Cell user_analog_project_wrapper disconnected node: la_oenb[97] +Cell user_analog_project_wrapper disconnected node: la_oenb[96] +Cell user_analog_project_wrapper disconnected node: la_oenb[95] +Cell user_analog_project_wrapper disconnected node: la_oenb[94] +Cell user_analog_project_wrapper disconnected node: la_oenb[93] +Cell user_analog_project_wrapper disconnected node: la_oenb[92] +Cell user_analog_project_wrapper disconnected node: la_oenb[91] +Cell user_analog_project_wrapper disconnected node: la_oenb[90] +Cell user_analog_project_wrapper disconnected node: la_oenb[89] +Cell user_analog_project_wrapper disconnected node: la_oenb[88] +Cell user_analog_project_wrapper disconnected node: la_oenb[87] +Cell user_analog_project_wrapper disconnected node: la_oenb[86] +Cell user_analog_project_wrapper disconnected node: la_oenb[85] +Cell user_analog_project_wrapper disconnected node: la_oenb[84] +Cell user_analog_project_wrapper disconnected node: la_oenb[83] +Cell user_analog_project_wrapper disconnected node: la_oenb[82] +Cell user_analog_project_wrapper disconnected node: la_oenb[81] +Cell user_analog_project_wrapper disconnected node: la_oenb[80] +Cell user_analog_project_wrapper disconnected node: la_oenb[79] +Cell user_analog_project_wrapper disconnected node: la_oenb[78] +Cell user_analog_project_wrapper disconnected node: la_oenb[77] +Cell user_analog_project_wrapper disconnected node: la_oenb[76] +Cell user_analog_project_wrapper disconnected node: la_oenb[75] +Cell user_analog_project_wrapper disconnected node: la_oenb[74] +Cell user_analog_project_wrapper disconnected node: la_oenb[73] +Cell user_analog_project_wrapper disconnected node: la_oenb[72] +Cell user_analog_project_wrapper disconnected node: la_oenb[71] +Cell user_analog_project_wrapper disconnected node: la_oenb[70] +Cell user_analog_project_wrapper disconnected node: la_oenb[69] +Cell user_analog_project_wrapper disconnected node: la_oenb[68] +Cell user_analog_project_wrapper disconnected node: la_oenb[67] +Cell user_analog_project_wrapper disconnected node: la_oenb[66] +Cell user_analog_project_wrapper disconnected node: la_oenb[65] +Cell user_analog_project_wrapper disconnected node: la_oenb[64] +Cell user_analog_project_wrapper disconnected node: la_oenb[63] +Cell user_analog_project_wrapper disconnected node: la_oenb[62] +Cell user_analog_project_wrapper disconnected node: la_oenb[61] +Cell user_analog_project_wrapper disconnected node: la_oenb[60] +Cell user_analog_project_wrapper disconnected node: la_oenb[59] +Cell user_analog_project_wrapper disconnected node: la_oenb[58] +Cell user_analog_project_wrapper disconnected node: la_oenb[57] +Cell user_analog_project_wrapper disconnected node: la_oenb[56] +Cell user_analog_project_wrapper disconnected node: la_oenb[55] +Cell user_analog_project_wrapper disconnected node: la_oenb[54] +Cell user_analog_project_wrapper disconnected node: la_oenb[53] +Cell user_analog_project_wrapper disconnected node: la_oenb[52] +Cell user_analog_project_wrapper disconnected node: la_oenb[51] +Cell user_analog_project_wrapper disconnected node: la_oenb[50] +Cell user_analog_project_wrapper disconnected node: la_oenb[49] +Cell user_analog_project_wrapper disconnected node: la_oenb[48] +Cell user_analog_project_wrapper disconnected node: la_oenb[47] +Cell user_analog_project_wrapper disconnected node: la_oenb[46] +Cell user_analog_project_wrapper disconnected node: la_oenb[45] +Cell user_analog_project_wrapper disconnected node: la_oenb[44] +Cell user_analog_project_wrapper disconnected node: la_oenb[43] +Cell user_analog_project_wrapper disconnected node: la_oenb[42] +Cell user_analog_project_wrapper disconnected node: la_oenb[41] +Cell user_analog_project_wrapper disconnected node: la_oenb[40] +Cell user_analog_project_wrapper disconnected node: la_oenb[39] +Cell user_analog_project_wrapper disconnected node: la_oenb[38] +Cell user_analog_project_wrapper disconnected node: la_oenb[37] +Cell user_analog_project_wrapper disconnected node: la_oenb[36] +Cell user_analog_project_wrapper disconnected node: la_oenb[35] +Cell user_analog_project_wrapper disconnected node: la_oenb[34] +Cell user_analog_project_wrapper disconnected node: la_oenb[33] +Cell user_analog_project_wrapper disconnected node: la_oenb[32] +Cell user_analog_project_wrapper disconnected node: la_oenb[31] +Cell user_analog_project_wrapper disconnected node: la_oenb[30] +Cell user_analog_project_wrapper disconnected node: la_oenb[29] +Cell user_analog_project_wrapper disconnected node: la_oenb[28] +Cell user_analog_project_wrapper disconnected node: la_oenb[27] +Cell user_analog_project_wrapper disconnected node: la_oenb[26] +Cell user_analog_project_wrapper disconnected node: la_oenb[25] +Cell user_analog_project_wrapper disconnected node: la_oenb[24] +Cell user_analog_project_wrapper disconnected node: la_oenb[23] +Cell user_analog_project_wrapper disconnected node: la_oenb[22] +Cell user_analog_project_wrapper disconnected node: la_oenb[21] +Cell user_analog_project_wrapper disconnected node: la_oenb[20] +Cell user_analog_project_wrapper disconnected node: la_oenb[19] +Cell user_analog_project_wrapper disconnected node: la_oenb[18] +Cell user_analog_project_wrapper disconnected node: la_oenb[17] +Cell user_analog_project_wrapper disconnected node: la_oenb[16] +Cell user_analog_project_wrapper disconnected node: la_oenb[15] +Cell user_analog_project_wrapper disconnected node: la_oenb[14] +Cell user_analog_project_wrapper disconnected node: la_oenb[13] +Cell user_analog_project_wrapper disconnected node: la_oenb[12] +Cell user_analog_project_wrapper disconnected node: la_oenb[11] +Cell user_analog_project_wrapper disconnected node: la_oenb[10] +Cell user_analog_project_wrapper disconnected node: la_oenb[9] +Cell user_analog_project_wrapper disconnected node: la_oenb[8] +Cell user_analog_project_wrapper disconnected node: la_oenb[7] +Cell user_analog_project_wrapper disconnected node: la_oenb[6] +Cell user_analog_project_wrapper disconnected node: la_oenb[5] +Cell user_analog_project_wrapper disconnected node: la_oenb[4] +Cell user_analog_project_wrapper disconnected node: la_oenb[3] +Cell user_analog_project_wrapper disconnected node: la_oenb[2] +Cell user_analog_project_wrapper disconnected node: la_oenb[1] +Cell user_analog_project_wrapper disconnected node: la_oenb[0] Subcircuit summary: -Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper -------------------------------------------------------------------------|------------------------------------------------------------------------ -example_por (2) |example_por (2) -Number of devices: 2 |Number of devices: 2 -Number of nets: 10 |Number of nets: 10 -------------------------------------------------------------------------------------------------------------------------------------------------- +Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper +-------------------------------------------|------------------------------------------- +io_clamp (2) |io_clamp (2) +sky130_fd_pr__cap_mim_m3_2 (4) |sky130_fd_pr__cap_mim_m3_2 (4) +sky130_fd_pr__pfet_01v8 (26) |sky130_fd_pr__pfet_01v8 (26) +sky130_fd_pr__nfet_01v8 (26) |sky130_fd_pr__nfet_01v8 (26) +sky130_fd_pr__nfet_01v8_lvt (33) |sky130_fd_pr__nfet_01v8_lvt (33) +sky130_fd_pr__pfet_01v8_lvt (40) |sky130_fd_pr__pfet_01v8_lvt (40) +sky130_fd_pr__res_xhigh_po (15) |sky130_fd_pr__res_xhigh_po (15) +sky130_fd_pr__cap_mim_m3_1 (13) |sky130_fd_pr__cap_mim_m3_1 (13) +ESD (5) |ESD (5) +sky130_fd_pr__res_generic_m3 (5) |sky130_fd_pr__res_generic_m3 (5) +sky130_fd_pr__res_generic_m5 (3) |sky130_fd_pr__res_generic_m5 (3) +sky130_fd_pr__res_generic_m4 (2) |sky130_fd_pr__res_generic_m4 (2) +Number of devices: 174 |Number of devices: 174 +Number of nets: 93 |Number of nets: 93 +--------------------------------------------------------------------------------------- Resolving automorphisms by property value. -Resolving automorphisms by pin name. +Netlists match uniquely. Netlists match uniquely. Circuits match correctly. Subcircuit pins: -Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper -------------------------------------------------------------------------|------------------------------------------------------------------------ -vdda1 |vdda1 -io_clamp_high[0] |io_analog[4] **Mismatch** -gpio_analog[3] |gpio_analog[3] -gpio_analog[7] |gpio_analog[7] -io_out[11] |io_out[11] -io_out[15] |io_out[15] -io_out[16] |io_out[16] -io_out[12] |io_out[12] -vccd1 |vccd1 -vssa1 |vssa1 -gpio_analog[0] |gpio_analog[0] -gpio_analog[10] |gpio_analog[10] -gpio_analog[11] |gpio_analog[11] -gpio_analog[12] |gpio_analog[12] -gpio_analog[13] |gpio_analog[13] -gpio_analog[14] |gpio_analog[14] -gpio_analog[15] |gpio_analog[15] -gpio_analog[16] |gpio_analog[16] -gpio_analog[17] |gpio_analog[17] -gpio_analog[1] |gpio_analog[1] -gpio_analog[2] |gpio_analog[2] -gpio_analog[4] |gpio_analog[4] -gpio_analog[5] |gpio_analog[5] -gpio_analog[6] |gpio_analog[6] -gpio_analog[8] |gpio_analog[8] -gpio_analog[9] |gpio_analog[9] -gpio_noesd[0] |gpio_noesd[0] -gpio_noesd[10] |gpio_noesd[10] -gpio_noesd[11] |gpio_noesd[11] -gpio_noesd[12] |gpio_noesd[12] -gpio_noesd[13] |gpio_noesd[13] -gpio_noesd[14] |gpio_noesd[14] -gpio_noesd[15] |gpio_noesd[15] -gpio_noesd[16] |gpio_noesd[16] -gpio_noesd[17] |gpio_noesd[17] -gpio_noesd[1] |gpio_noesd[1] -gpio_noesd[2] |gpio_noesd[2] -gpio_noesd[3] |gpio_noesd[3] -gpio_noesd[4] |gpio_noesd[4] -gpio_noesd[5] |gpio_noesd[5] -gpio_noesd[6] |gpio_noesd[6] -gpio_noesd[7] |gpio_noesd[7] -gpio_noesd[8] |gpio_noesd[8] -gpio_noesd[9] |gpio_noesd[9] -io_analog[0] |io_analog[0] -io_analog[10] |io_analog[10] -io_analog[1] |io_analog[1] -io_analog[2] |io_analog[2] -io_analog[3] |io_analog[3] -io_analog[7] |io_analog[7] -io_analog[8] |io_analog[8] -io_analog[9] |io_analog[9] -io_analog[5] |io_analog[5] -io_analog[6] |io_analog[6] -io_in[0] |io_in[0] -io_in[10] |io_in[10] -io_in[11] |io_in[11] -io_in[12] |io_in[12] -io_in[13] |io_in[13] -io_in[14] |io_in[14] -io_in[15] |io_in[15] -io_in[16] |io_in[16] -io_in[17] |io_in[17] -io_in[18] |io_in[18] -io_in[19] |io_in[19] -io_in[1] |io_in[1] -io_in[20] |io_in[20] -io_in[21] |io_in[21] -io_in[22] |io_in[22] -io_in[23] |io_in[23] -io_in[24] |io_in[24] -io_in[25] |io_in[25] -io_in[26] |io_in[26] -io_in[2] |io_in[2] -io_in[3] |io_in[3] -io_in[4] |io_in[4] -io_in[5] |io_in[5] -io_in[6] |io_in[6] -io_in[7] |io_in[7] -io_in[8] |io_in[8] -io_in[9] |io_in[9] -io_in_3v3[0] |io_in_3v3[0] -io_in_3v3[10] |io_in_3v3[10] -io_in_3v3[11] |io_in_3v3[11] -io_in_3v3[12] |io_in_3v3[12] -io_in_3v3[13] |io_in_3v3[13] -io_in_3v3[14] |io_in_3v3[14] -io_in_3v3[15] |io_in_3v3[15] -io_in_3v3[16] |io_in_3v3[16] -io_in_3v3[17] |io_in_3v3[17] -io_in_3v3[18] |io_in_3v3[18] -io_in_3v3[19] |io_in_3v3[19] -io_in_3v3[1] |io_in_3v3[1] -io_in_3v3[20] |io_in_3v3[20] -io_in_3v3[21] |io_in_3v3[21] -io_in_3v3[22] |io_in_3v3[22] -io_in_3v3[23] |io_in_3v3[23] -io_in_3v3[24] |io_in_3v3[24] -io_in_3v3[25] |io_in_3v3[25] -io_in_3v3[26] |io_in_3v3[26] -io_in_3v3[2] |io_in_3v3[2] -io_in_3v3[3] |io_in_3v3[3] -io_in_3v3[4] |io_in_3v3[4] -io_in_3v3[5] |io_in_3v3[5] -io_in_3v3[6] |io_in_3v3[6] -io_in_3v3[7] |io_in_3v3[7] -io_in_3v3[8] |io_in_3v3[8] -io_in_3v3[9] |io_in_3v3[9] -io_oeb[0] |io_oeb[0] -io_oeb[10] |io_oeb[10] -io_oeb[13] |io_oeb[13] -io_oeb[14] |io_oeb[14] -io_oeb[17] |io_oeb[17] -io_oeb[18] |io_oeb[18] -io_oeb[19] |io_oeb[19] -io_oeb[1] |io_oeb[1] -io_oeb[20] |io_oeb[20] -io_oeb[21] |io_oeb[21] -io_oeb[22] |io_oeb[22] -io_oeb[23] |io_oeb[23] -io_oeb[24] |io_oeb[24] -io_oeb[25] |io_oeb[25] -io_oeb[26] |io_oeb[26] -io_oeb[2] |io_oeb[2] -io_oeb[3] |io_oeb[3] -io_oeb[4] |io_oeb[4] -io_oeb[5] |io_oeb[5] -io_oeb[6] |io_oeb[6] -io_oeb[7] |io_oeb[7] -io_oeb[8] |io_oeb[8] -io_oeb[9] |io_oeb[9] -io_out[0] |io_out[0] -io_out[10] |io_out[10] -io_out[13] |io_out[13] -io_out[14] |io_out[14] -io_out[17] |io_out[17] -io_out[18] |io_out[18] -io_out[19] |io_out[19] -io_out[1] |io_out[1] -io_out[20] |io_out[20] -io_out[21] |io_out[21] -io_out[22] |io_out[22] -io_out[23] |io_out[23] -io_out[24] |io_out[24] -io_out[25] |io_out[25] -io_out[26] |io_out[26] -io_out[2] |io_out[2] -io_out[3] |io_out[3] -io_out[4] |io_out[4] -io_out[5] |io_out[5] -io_out[6] |io_out[6] -io_out[7] |io_out[7] -io_out[8] |io_out[8] -io_out[9] |io_out[9] -la_data_in[0] |la_data_in[0] -la_data_in[100] |la_data_in[100] -la_data_in[101] |la_data_in[101] -la_data_in[102] |la_data_in[102] -la_data_in[103] |la_data_in[103] -la_data_in[104] |la_data_in[104] -la_data_in[105] |la_data_in[105] -la_data_in[106] |la_data_in[106] -la_data_in[107] |la_data_in[107] -la_data_in[108] |la_data_in[108] -la_data_in[109] |la_data_in[109] -la_data_in[10] |la_data_in[10] -la_data_in[110] |la_data_in[110] -la_data_in[111] |la_data_in[111] -la_data_in[112] |la_data_in[112] -la_data_in[113] |la_data_in[113] -la_data_in[114] |la_data_in[114] -la_data_in[115] |la_data_in[115] -la_data_in[116] |la_data_in[116] -la_data_in[117] |la_data_in[117] -la_data_in[118] |la_data_in[118] -la_data_in[119] |la_data_in[119] -la_data_in[11] |la_data_in[11] -la_data_in[120] |la_data_in[120] -la_data_in[121] |la_data_in[121] -la_data_in[122] |la_data_in[122] -la_data_in[123] |la_data_in[123] -la_data_in[124] |la_data_in[124] -la_data_in[125] |la_data_in[125] -la_data_in[126] |la_data_in[126] -la_data_in[127] |la_data_in[127] -la_data_in[12] |la_data_in[12] -la_data_in[13] |la_data_in[13] -la_data_in[14] |la_data_in[14] -la_data_in[15] |la_data_in[15] -la_data_in[16] |la_data_in[16] -la_data_in[17] |la_data_in[17] -la_data_in[18] |la_data_in[18] -la_data_in[19] |la_data_in[19] -la_data_in[1] |la_data_in[1] -la_data_in[20] |la_data_in[20] -la_data_in[21] |la_data_in[21] -la_data_in[22] |la_data_in[22] -la_data_in[23] |la_data_in[23] -la_data_in[24] |la_data_in[24] -la_data_in[25] |la_data_in[25] -la_data_in[26] |la_data_in[26] -la_data_in[27] |la_data_in[27] -la_data_in[28] |la_data_in[28] -la_data_in[29] |la_data_in[29] -la_data_in[2] |la_data_in[2] -la_data_in[30] |la_data_in[30] -la_data_in[31] |la_data_in[31] -la_data_in[32] |la_data_in[32] -la_data_in[33] |la_data_in[33] -la_data_in[34] |la_data_in[34] -la_data_in[35] |la_data_in[35] -la_data_in[36] |la_data_in[36] -la_data_in[37] |la_data_in[37] -la_data_in[38] |la_data_in[38] -la_data_in[39] |la_data_in[39] -la_data_in[3] |la_data_in[3] -la_data_in[40] |la_data_in[40] -la_data_in[41] |la_data_in[41] -la_data_in[42] |la_data_in[42] -la_data_in[43] |la_data_in[43] -la_data_in[44] |la_data_in[44] -la_data_in[45] |la_data_in[45] -la_data_in[46] |la_data_in[46] -la_data_in[47] |la_data_in[47] -la_data_in[48] |la_data_in[48] -la_data_in[49] |la_data_in[49] -la_data_in[4] |la_data_in[4] -la_data_in[50] |la_data_in[50] -la_data_in[51] |la_data_in[51] -la_data_in[52] |la_data_in[52] -la_data_in[53] |la_data_in[53] -la_data_in[54] |la_data_in[54] -la_data_in[55] |la_data_in[55] -la_data_in[56] |la_data_in[56] -la_data_in[57] |la_data_in[57] -la_data_in[58] |la_data_in[58] -la_data_in[59] |la_data_in[59] -la_data_in[5] |la_data_in[5] -la_data_in[60] |la_data_in[60] -la_data_in[61] |la_data_in[61] -la_data_in[62] |la_data_in[62] -la_data_in[63] |la_data_in[63] -la_data_in[64] |la_data_in[64] -la_data_in[65] |la_data_in[65] -la_data_in[66] |la_data_in[66] -la_data_in[67] |la_data_in[67] -la_data_in[68] |la_data_in[68] -la_data_in[69] |la_data_in[69] -la_data_in[6] |la_data_in[6] -la_data_in[70] |la_data_in[70] -la_data_in[71] |la_data_in[71] -la_data_in[72] |la_data_in[72] -la_data_in[73] |la_data_in[73] -la_data_in[74] |la_data_in[74] -la_data_in[75] |la_data_in[75] -la_data_in[76] |la_data_in[76] -la_data_in[77] |la_data_in[77] -la_data_in[78] |la_data_in[78] -la_data_in[79] |la_data_in[79] -la_data_in[7] |la_data_in[7] -la_data_in[80] |la_data_in[80] -la_data_in[81] |la_data_in[81] -la_data_in[82] |la_data_in[82] -la_data_in[83] |la_data_in[83] -la_data_in[84] |la_data_in[84] -la_data_in[85] |la_data_in[85] -la_data_in[86] |la_data_in[86] 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|la_data_out[112] -la_data_out[113] |la_data_out[113] -la_data_out[114] |la_data_out[114] -la_data_out[115] |la_data_out[115] -la_data_out[116] |la_data_out[116] -la_data_out[117] |la_data_out[117] -la_data_out[118] |la_data_out[118] -la_data_out[119] |la_data_out[119] -la_data_out[11] |la_data_out[11] -la_data_out[120] |la_data_out[120] -la_data_out[121] |la_data_out[121] -la_data_out[122] |la_data_out[122] -la_data_out[123] |la_data_out[123] -la_data_out[124] |la_data_out[124] -la_data_out[125] |la_data_out[125] -la_data_out[126] |la_data_out[126] -la_data_out[127] |la_data_out[127] -la_data_out[12] |la_data_out[12] -la_data_out[13] |la_data_out[13] -la_data_out[14] |la_data_out[14] -la_data_out[15] |la_data_out[15] -la_data_out[16] |la_data_out[16] -la_data_out[17] |la_data_out[17] -la_data_out[18] |la_data_out[18] -la_data_out[19] |la_data_out[19] -la_data_out[1] |la_data_out[1] -la_data_out[20] |la_data_out[20] -la_data_out[21] |la_data_out[21] -la_data_out[22] |la_data_out[22] -la_data_out[23] |la_data_out[23] -la_data_out[24] |la_data_out[24] -la_data_out[25] |la_data_out[25] -la_data_out[26] |la_data_out[26] -la_data_out[27] |la_data_out[27] -la_data_out[28] |la_data_out[28] -la_data_out[29] |la_data_out[29] -la_data_out[2] |la_data_out[2] -la_data_out[30] |la_data_out[30] -la_data_out[31] |la_data_out[31] -la_data_out[32] |la_data_out[32] -la_data_out[33] |la_data_out[33] -la_data_out[34] |la_data_out[34] -la_data_out[35] |la_data_out[35] -la_data_out[36] |la_data_out[36] -la_data_out[37] |la_data_out[37] -la_data_out[38] |la_data_out[38] -la_data_out[39] |la_data_out[39] -la_data_out[3] |la_data_out[3] -la_data_out[40] |la_data_out[40] -la_data_out[41] |la_data_out[41] -la_data_out[42] |la_data_out[42] -la_data_out[43] |la_data_out[43] -la_data_out[44] |la_data_out[44] -la_data_out[45] |la_data_out[45] -la_data_out[46] |la_data_out[46] -la_data_out[47] |la_data_out[47] -la_data_out[48] |la_data_out[48] -la_data_out[49] |la_data_out[49] -la_data_out[4] |la_data_out[4] -la_data_out[50] |la_data_out[50] -la_data_out[51] |la_data_out[51] -la_data_out[52] |la_data_out[52] -la_data_out[53] |la_data_out[53] -la_data_out[54] |la_data_out[54] -la_data_out[55] |la_data_out[55] -la_data_out[56] |la_data_out[56] -la_data_out[57] |la_data_out[57] -la_data_out[58] |la_data_out[58] -la_data_out[59] |la_data_out[59] -la_data_out[5] |la_data_out[5] -la_data_out[60] |la_data_out[60] -la_data_out[61] |la_data_out[61] -la_data_out[62] |la_data_out[62] -la_data_out[63] |la_data_out[63] -la_data_out[64] |la_data_out[64] -la_data_out[65] |la_data_out[65] -la_data_out[66] |la_data_out[66] -la_data_out[67] |la_data_out[67] -la_data_out[68] |la_data_out[68] -la_data_out[69] |la_data_out[69] -la_data_out[6] |la_data_out[6] -la_data_out[70] |la_data_out[70] -la_data_out[71] |la_data_out[71] -la_data_out[72] |la_data_out[72] -la_data_out[73] |la_data_out[73] -la_data_out[74] |la_data_out[74] -la_data_out[75] |la_data_out[75] -la_data_out[76] |la_data_out[76] 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|la_oenb[103] -la_oenb[104] |la_oenb[104] -la_oenb[105] |la_oenb[105] -la_oenb[106] |la_oenb[106] -la_oenb[107] |la_oenb[107] -la_oenb[108] |la_oenb[108] -la_oenb[109] |la_oenb[109] -la_oenb[10] |la_oenb[10] -la_oenb[110] |la_oenb[110] -la_oenb[111] |la_oenb[111] -la_oenb[112] |la_oenb[112] -la_oenb[113] |la_oenb[113] -la_oenb[114] |la_oenb[114] -la_oenb[115] |la_oenb[115] -la_oenb[116] |la_oenb[116] -la_oenb[117] |la_oenb[117] -la_oenb[118] |la_oenb[118] -la_oenb[119] |la_oenb[119] -la_oenb[11] |la_oenb[11] -la_oenb[120] |la_oenb[120] -la_oenb[121] |la_oenb[121] -la_oenb[122] |la_oenb[122] -la_oenb[123] |la_oenb[123] -la_oenb[124] |la_oenb[124] -la_oenb[125] |la_oenb[125] -la_oenb[126] |la_oenb[126] -la_oenb[127] |la_oenb[127] -la_oenb[12] |la_oenb[12] -la_oenb[13] |la_oenb[13] -la_oenb[14] |la_oenb[14] -la_oenb[15] |la_oenb[15] -la_oenb[16] |la_oenb[16] -la_oenb[17] |la_oenb[17] -la_oenb[18] |la_oenb[18] -la_oenb[19] |la_oenb[19] -la_oenb[1] |la_oenb[1] -la_oenb[20] |la_oenb[20] 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|la_oenb[56] -la_oenb[57] |la_oenb[57] -la_oenb[58] |la_oenb[58] -la_oenb[59] |la_oenb[59] -la_oenb[5] |la_oenb[5] -la_oenb[60] |la_oenb[60] -la_oenb[61] |la_oenb[61] -la_oenb[62] |la_oenb[62] -la_oenb[63] |la_oenb[63] -la_oenb[64] |la_oenb[64] -la_oenb[65] |la_oenb[65] -la_oenb[66] |la_oenb[66] -la_oenb[67] |la_oenb[67] -la_oenb[68] |la_oenb[68] -la_oenb[69] |la_oenb[69] -la_oenb[6] |la_oenb[6] -la_oenb[70] |la_oenb[70] -la_oenb[71] |la_oenb[71] -la_oenb[72] |la_oenb[72] -la_oenb[73] |la_oenb[73] -la_oenb[74] |la_oenb[74] -la_oenb[75] |la_oenb[75] -la_oenb[76] |la_oenb[76] -la_oenb[77] |la_oenb[77] -la_oenb[78] |la_oenb[78] -la_oenb[79] |la_oenb[79] -la_oenb[7] |la_oenb[7] -la_oenb[80] |la_oenb[80] -la_oenb[81] |la_oenb[81] -la_oenb[82] |la_oenb[82] -la_oenb[83] |la_oenb[83] -la_oenb[84] |la_oenb[84] -la_oenb[85] |la_oenb[85] -la_oenb[86] |la_oenb[86] -la_oenb[87] |la_oenb[87] -la_oenb[88] |la_oenb[88] -la_oenb[89] |la_oenb[89] -la_oenb[8] |la_oenb[8] -la_oenb[90] |la_oenb[90] -la_oenb[91] |la_oenb[91] -la_oenb[92] |la_oenb[92] -la_oenb[93] |la_oenb[93] -la_oenb[94] |la_oenb[94] -la_oenb[95] |la_oenb[95] -la_oenb[96] |la_oenb[96] -la_oenb[97] |la_oenb[97] -la_oenb[98] |la_oenb[98] -la_oenb[99] |la_oenb[99] -la_oenb[9] |la_oenb[9] -user_clock2 |user_clock2 -user_irq[0] |user_irq[0] -user_irq[1] |user_irq[1] -user_irq[2] |user_irq[2] -vccd2 |vccd2 -vdda2 |vdda2 -vssa2 |vssa2 -vssd1 |vssd1 -vssd2 |vssd2 -wb_clk_i |wb_clk_i -wb_rst_i |wb_rst_i -wbs_ack_o |wbs_ack_o -wbs_adr_i[0] |wbs_adr_i[0] -wbs_adr_i[10] |wbs_adr_i[10] -wbs_adr_i[11] |wbs_adr_i[11] -wbs_adr_i[12] |wbs_adr_i[12] -wbs_adr_i[13] |wbs_adr_i[13] -wbs_adr_i[14] |wbs_adr_i[14] -wbs_adr_i[15] |wbs_adr_i[15] -wbs_adr_i[16] |wbs_adr_i[16] -wbs_adr_i[17] |wbs_adr_i[17] -wbs_adr_i[18] |wbs_adr_i[18] -wbs_adr_i[19] |wbs_adr_i[19] -wbs_adr_i[1] |wbs_adr_i[1] -wbs_adr_i[20] |wbs_adr_i[20] -wbs_adr_i[21] |wbs_adr_i[21] -wbs_adr_i[22] |wbs_adr_i[22] -wbs_adr_i[23] |wbs_adr_i[23] -wbs_adr_i[24] |wbs_adr_i[24] -wbs_adr_i[25] |wbs_adr_i[25] -wbs_adr_i[26] |wbs_adr_i[26] -wbs_adr_i[27] |wbs_adr_i[27] -wbs_adr_i[28] |wbs_adr_i[28] -wbs_adr_i[29] |wbs_adr_i[29] -wbs_adr_i[2] |wbs_adr_i[2] -wbs_adr_i[30] |wbs_adr_i[30] -wbs_adr_i[31] |wbs_adr_i[31] -wbs_adr_i[3] |wbs_adr_i[3] -wbs_adr_i[4] |wbs_adr_i[4] -wbs_adr_i[5] |wbs_adr_i[5] -wbs_adr_i[6] |wbs_adr_i[6] -wbs_adr_i[7] |wbs_adr_i[7] -wbs_adr_i[8] |wbs_adr_i[8] -wbs_adr_i[9] |wbs_adr_i[9] -wbs_cyc_i |wbs_cyc_i -wbs_dat_i[0] |wbs_dat_i[0] -wbs_dat_i[10] |wbs_dat_i[10] -wbs_dat_i[11] |wbs_dat_i[11] -wbs_dat_i[12] |wbs_dat_i[12] -wbs_dat_i[13] |wbs_dat_i[13] -wbs_dat_i[14] |wbs_dat_i[14] -wbs_dat_i[15] |wbs_dat_i[15] -wbs_dat_i[16] |wbs_dat_i[16] -wbs_dat_i[17] |wbs_dat_i[17] -wbs_dat_i[18] |wbs_dat_i[18] -wbs_dat_i[19] |wbs_dat_i[19] -wbs_dat_i[1] |wbs_dat_i[1] -wbs_dat_i[20] |wbs_dat_i[20] -wbs_dat_i[21] |wbs_dat_i[21] -wbs_dat_i[22] |wbs_dat_i[22] -wbs_dat_i[23] |wbs_dat_i[23] -wbs_dat_i[24] |wbs_dat_i[24] -wbs_dat_i[25] |wbs_dat_i[25] -wbs_dat_i[26] |wbs_dat_i[26] -wbs_dat_i[27] |wbs_dat_i[27] -wbs_dat_i[28] |wbs_dat_i[28] -wbs_dat_i[29] |wbs_dat_i[29] -wbs_dat_i[2] |wbs_dat_i[2] -wbs_dat_i[30] |wbs_dat_i[30] -wbs_dat_i[31] |wbs_dat_i[31] -wbs_dat_i[3] |wbs_dat_i[3] -wbs_dat_i[4] |wbs_dat_i[4] -wbs_dat_i[5] |wbs_dat_i[5] -wbs_dat_i[6] |wbs_dat_i[6] -wbs_dat_i[7] |wbs_dat_i[7] -wbs_dat_i[8] |wbs_dat_i[8] -wbs_dat_i[9] |wbs_dat_i[9] -wbs_dat_o[0] |wbs_dat_o[0] -wbs_dat_o[10] |wbs_dat_o[10] -wbs_dat_o[11] |wbs_dat_o[11] -wbs_dat_o[12] |wbs_dat_o[12] -wbs_dat_o[13] |wbs_dat_o[13] -wbs_dat_o[14] |wbs_dat_o[14] -wbs_dat_o[15] |wbs_dat_o[15] -wbs_dat_o[16] |wbs_dat_o[16] -wbs_dat_o[17] |wbs_dat_o[17] -wbs_dat_o[18] |wbs_dat_o[18] -wbs_dat_o[19] |wbs_dat_o[19] -wbs_dat_o[1] |wbs_dat_o[1] -wbs_dat_o[20] |wbs_dat_o[20] -wbs_dat_o[21] |wbs_dat_o[21] -wbs_dat_o[22] |wbs_dat_o[22] -wbs_dat_o[23] |wbs_dat_o[23] -wbs_dat_o[24] |wbs_dat_o[24] -wbs_dat_o[25] |wbs_dat_o[25] -wbs_dat_o[26] |wbs_dat_o[26] -wbs_dat_o[27] |wbs_dat_o[27] -wbs_dat_o[28] |wbs_dat_o[28] -wbs_dat_o[29] |wbs_dat_o[29] -wbs_dat_o[2] |wbs_dat_o[2] -wbs_dat_o[30] |wbs_dat_o[30] -wbs_dat_o[31] |wbs_dat_o[31] -wbs_dat_o[3] |wbs_dat_o[3] -wbs_dat_o[4] |wbs_dat_o[4] -wbs_dat_o[5] |wbs_dat_o[5] -wbs_dat_o[6] |wbs_dat_o[6] -wbs_dat_o[7] |wbs_dat_o[7] -wbs_dat_o[8] |wbs_dat_o[8] -wbs_dat_o[9] |wbs_dat_o[9] -wbs_sel_i[0] |wbs_sel_i[0] -wbs_sel_i[1] |wbs_sel_i[1] -wbs_sel_i[2] |wbs_sel_i[2] -wbs_sel_i[3] |wbs_sel_i[3] -wbs_stb_i |wbs_stb_i -wbs_we_i |wbs_we_i -(no matching pin) |io_oeb[16] -(no matching pin) |io_oeb[15] -(no matching pin) |io_oeb[12] -(no matching pin) |io_oeb[11] -(no matching pin) |io_clamp_high[2] -(no matching pin) |io_clamp_high[1] -(no matching pin) |io_clamp_high[0] -(no matching pin) |io_clamp_low[2] -(no matching pin) |io_clamp_low[1] -(no matching pin) |io_clamp_low[0] -------------------------------------------------------------------------------------------------------------------------------------------------- -Instance of user_analog_project_wrapper has only 98 of 653 ports -Cell pin lists for user_analog_project_wrapper and user_analog_project_wrapper altered to match. -The top level cell failed pin matching. -The following cells had property errors: example_por +Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper +-------------------------------------------|------------------------------------------- +vccd1 |vccd1 +vccd2 |vccd2 +vssd2 |vssd2 +vssd1 |vssd1 +vssa1 |vssa1 +io_analog[7] |io_analog[7] +io_analog[8] |io_analog[8] +io_analog[3] |io_analog[3] +io_analog[2] |io_analog[2] +io_analog[0] |io_analog[0] +io_analog[6] |io_analog[6] +io_analog[4] |io_analog[4] +io_analog[1] |io_analog[1] +io_analog[10] |io_analog[10] +vdda1 |vdda1 +vdda2 |vdda2 +vssa2 |vssa2 +io_analog[5] |io_analog[5] +(no matching pin) |wb_clk_i +(no matching pin) |wb_rst_i +(no matching pin) |wbs_stb_i +(no matching pin) |wbs_cyc_i +(no matching pin) |wbs_we_i +(no matching pin) |wbs_sel_i[3] +(no matching pin) |wbs_sel_i[2] +(no matching pin) |wbs_sel_i[1] +(no matching pin) |wbs_sel_i[0] +(no matching pin) |wbs_dat_i[31] +(no matching pin) |wbs_dat_i[30] +(no matching pin) |wbs_dat_i[29] +(no matching pin) |wbs_dat_i[28] +(no matching pin) |wbs_dat_i[27] +(no matching pin) |wbs_dat_i[26] +(no matching pin) |wbs_dat_i[25] +(no matching pin) |wbs_dat_i[24] +(no matching pin) |wbs_dat_i[23] +(no matching pin) |wbs_dat_i[22] +(no matching pin) |wbs_dat_i[21] +(no matching pin) |wbs_dat_i[20] +(no matching pin) |wbs_dat_i[19] +(no matching pin) |wbs_dat_i[18] +(no matching pin) |wbs_dat_i[17] +(no matching pin) |wbs_dat_i[16] +(no matching pin) |wbs_dat_i[15] +(no matching pin) |wbs_dat_i[14] +(no matching pin) |wbs_dat_i[13] +(no matching pin) |wbs_dat_i[12] +(no matching pin) |wbs_dat_i[11] +(no matching pin) |wbs_dat_i[10] +(no matching pin) |wbs_dat_i[9] +(no matching pin) |wbs_dat_i[8] +(no matching pin) |wbs_dat_i[7] +(no matching pin) |wbs_dat_i[6] +(no matching pin) |wbs_dat_i[5] +(no matching pin) |wbs_dat_i[4] +(no matching pin) |wbs_dat_i[3] +(no matching pin) |wbs_dat_i[2] +(no matching pin) |wbs_dat_i[1] +(no matching pin) |wbs_dat_i[0] +(no matching pin) |wbs_adr_i[31] +(no matching pin) |wbs_adr_i[30] +(no matching pin) |wbs_adr_i[29] +(no matching pin) |wbs_adr_i[28] +(no matching pin) |wbs_adr_i[27] +(no matching pin) |wbs_adr_i[26] +(no matching pin) |wbs_adr_i[25] +(no matching pin) |wbs_adr_i[24] +(no matching pin) |wbs_adr_i[23] +(no matching pin) |wbs_adr_i[22] +(no matching pin) |wbs_adr_i[21] +(no matching pin) |wbs_adr_i[20] +(no matching pin) |wbs_adr_i[19] +(no matching pin) |wbs_adr_i[18] +(no matching pin) |wbs_adr_i[17] +(no matching pin) |wbs_adr_i[16] +(no matching pin) |wbs_adr_i[15] +(no matching pin) |wbs_adr_i[14] +(no matching pin) |wbs_adr_i[13] +(no matching pin) |wbs_adr_i[12] +(no matching pin) |wbs_adr_i[11] +(no matching pin) |wbs_adr_i[10] +(no matching pin) |wbs_adr_i[9] +(no matching pin) |wbs_adr_i[8] +(no matching pin) |wbs_adr_i[7] +(no matching pin) |wbs_adr_i[6] +(no matching pin) |wbs_adr_i[5] +(no matching pin) |wbs_adr_i[4] +(no matching pin) |wbs_adr_i[3] +(no matching pin) |wbs_adr_i[2] +(no matching pin) |wbs_adr_i[1] +(no matching pin) |wbs_adr_i[0] +(no matching pin) |wbs_ack_o +(no matching pin) |wbs_dat_o[31] +(no matching pin) |wbs_dat_o[30] +(no matching pin) |wbs_dat_o[29] +(no matching pin) |wbs_dat_o[28] +(no matching pin) |wbs_dat_o[27] +(no matching pin) |wbs_dat_o[26] +(no matching pin) |wbs_dat_o[25] +(no matching pin) |wbs_dat_o[24] +(no matching pin) |wbs_dat_o[23] +(no matching pin) |wbs_dat_o[22] +(no matching pin) |wbs_dat_o[21] +(no matching pin) |wbs_dat_o[20] +(no matching pin) |wbs_dat_o[19] +(no matching pin) |wbs_dat_o[18] +(no matching pin) |wbs_dat_o[17] +(no matching pin) |wbs_dat_o[16] +(no matching pin) |wbs_dat_o[15] +(no matching pin) |wbs_dat_o[14] +(no matching pin) |wbs_dat_o[13] +(no matching pin) |wbs_dat_o[12] +(no matching pin) |wbs_dat_o[11] +(no matching pin) |wbs_dat_o[10] +(no matching pin) |wbs_dat_o[9] +(no matching pin) |wbs_dat_o[8] +(no matching pin) |wbs_dat_o[7] +(no matching pin) |wbs_dat_o[6] +(no matching pin) |wbs_dat_o[5] +(no matching pin) |wbs_dat_o[4] +(no matching pin) |wbs_dat_o[3] +(no matching pin) |wbs_dat_o[2] +(no matching pin) |wbs_dat_o[1] +(no matching pin) |wbs_dat_o[0] +(no matching pin) |la_data_in[127] +(no matching pin) |la_data_in[126] +(no matching pin) |la_data_in[125] +(no matching pin) |la_data_in[124] +(no matching pin) |la_data_in[123] +(no matching pin) |la_data_in[122] +(no matching pin) |la_data_in[121] +(no matching pin) |la_data_in[120] +(no matching pin) |la_data_in[119] +(no matching pin) |la_data_in[118] +(no matching pin) |la_data_in[117] +(no matching pin) |la_data_in[116] +(no matching pin) |la_data_in[115] +(no matching pin) |la_data_in[114] +(no matching pin) |la_data_in[113] +(no matching pin) |la_data_in[112] +(no matching pin) |la_data_in[111] +(no matching pin) |la_data_in[110] +(no matching pin) |la_data_in[109] +(no matching pin) |la_data_in[108] +(no matching pin) |la_data_in[107] +(no matching pin) |la_data_in[106] +(no matching pin) |la_data_in[105] +(no matching pin) |la_data_in[104] +(no matching pin) |la_data_in[103] +(no matching pin) |la_data_in[102] +(no matching pin) |la_data_in[101] +(no matching pin) |la_data_in[100] +(no matching pin) |la_data_in[99] +(no matching pin) |la_data_in[98] +(no matching pin) |la_data_in[97] +(no matching pin) |la_data_in[96] +(no matching pin) |la_data_in[95] +(no matching pin) |la_data_in[94] +(no matching pin) |la_data_in[93] +(no matching pin) |la_data_in[92] +(no matching pin) |la_data_in[91] +(no matching pin) |la_data_in[90] +(no matching pin) |la_data_in[89] +(no matching pin) |la_data_in[88] +(no matching pin) |la_data_in[87] +(no matching pin) |la_data_in[86] +(no matching pin) |la_data_in[85] +(no matching pin) |la_data_in[84] +(no matching pin) |la_data_in[83] +(no matching pin) |la_data_in[82] +(no matching pin) |la_data_in[81] +(no matching pin) |la_data_in[80] +(no matching pin) |la_data_in[79] +(no matching pin) |la_data_in[78] +(no matching pin) |la_data_in[77] +(no matching pin) |la_data_in[76] +(no matching pin) |la_data_in[75] +(no matching pin) |la_data_in[74] +(no matching pin) |la_data_in[73] +(no matching pin) |la_data_in[72] +(no matching pin) |la_data_in[71] +(no matching pin) |la_data_in[70] +(no matching pin) |la_data_in[69] +(no matching pin) |la_data_in[68] +(no matching pin) |la_data_in[67] +(no matching pin) |la_data_in[66] +(no matching pin) |la_data_in[65] +(no matching pin) |la_data_in[64] +(no matching pin) |la_data_in[63] +(no matching pin) |la_data_in[62] +(no matching pin) |la_data_in[61] +(no matching pin) |la_data_in[60] +(no matching pin) |la_data_in[59] +(no matching pin) |la_data_in[58] +(no matching pin) |la_data_in[57] +(no matching pin) |la_data_in[56] +(no matching pin) |la_data_in[55] +(no matching pin) |la_data_in[54] +(no matching pin) |la_data_in[53] +(no matching pin) |la_data_in[52] +(no matching pin) |la_data_in[51] +(no matching pin) |la_data_in[50] +(no matching pin) |la_data_in[49] +(no matching pin) |la_data_in[48] +(no matching pin) |la_data_in[47] +(no matching pin) |la_data_in[46] +(no matching pin) |la_data_in[45] +(no matching pin) |la_data_in[44] +(no matching pin) |la_data_in[43] +(no matching pin) |la_data_in[42] +(no matching pin) |la_data_in[41] +(no matching pin) |la_data_in[40] +(no matching pin) |la_data_in[39] +(no matching pin) |la_data_in[38] +(no matching pin) |la_data_in[37] +(no matching pin) |la_data_in[36] +(no matching pin) |la_data_in[35] +(no matching pin) |la_data_in[34] +(no matching pin) |la_data_in[33] +(no matching pin) |la_data_in[32] +(no matching pin) |la_data_in[31] +(no matching pin) |la_data_in[30] +(no matching pin) |la_data_in[29] +(no matching pin) |la_data_in[28] +(no matching pin) |la_data_in[27] +(no matching pin) |la_data_in[26] +(no matching pin) |la_data_in[25] +(no matching pin) |la_data_in[24] +(no matching pin) |la_data_in[23] +(no matching pin) |la_data_in[22] +(no matching pin) |la_data_in[21] +(no matching pin) |la_data_in[20] +(no matching pin) |la_data_in[19] +(no matching pin) |la_data_in[18] +(no matching pin) |la_data_in[17] +(no matching pin) |la_data_in[16] +(no matching pin) |la_data_in[15] +(no matching pin) |la_data_in[14] +(no matching pin) |la_data_in[13] +(no matching pin) |la_data_in[12] +(no matching pin) |la_data_in[11] +(no matching pin) |la_data_in[10] +(no matching pin) |la_data_in[9] +(no matching pin) |la_data_in[8] +(no matching pin) |la_data_in[7] +(no matching pin) |la_data_in[6] +(no matching pin) |la_data_in[5] +(no matching pin) |la_data_in[4] +(no matching pin) |la_data_in[3] +(no matching pin) |la_data_in[2] +(no matching pin) |la_data_in[1] +(no matching pin) |la_data_in[0] +(no matching pin) |la_data_out[127] +(no matching pin) |la_data_out[126] +(no matching pin) |la_data_out[125] +(no matching pin) |la_data_out[124] +(no matching pin) |la_data_out[123] +(no matching pin) |la_data_out[122] +(no matching pin) |la_data_out[121] +(no matching pin) |la_data_out[120] +(no matching pin) |la_data_out[119] +(no matching pin) |la_data_out[118] +(no matching pin) |la_data_out[117] +(no matching pin) |la_data_out[116] +(no matching pin) |la_data_out[115] +(no matching pin) |la_data_out[114] +(no matching pin) |la_data_out[113] +(no matching pin) |la_data_out[112] +(no matching pin) |la_data_out[111] +(no matching pin) |la_data_out[110] +(no matching pin) |la_data_out[109] +(no matching pin) |la_data_out[108] +(no matching pin) |la_data_out[107] +(no matching pin) |la_data_out[106] +(no matching pin) |la_data_out[105] +(no matching pin) |la_data_out[104] +(no matching pin) |la_data_out[103] +(no matching pin) |la_data_out[102] +(no matching pin) |la_data_out[101] +(no matching pin) |la_data_out[100] +(no matching pin) |la_data_out[99] +(no matching pin) |la_data_out[98] +(no matching pin) |la_data_out[97] +(no matching pin) |la_data_out[96] +(no matching pin) |la_data_out[95] +(no matching pin) |la_data_out[94] +(no matching pin) |la_data_out[93] +(no matching pin) |la_data_out[92] +(no matching pin) |la_data_out[91] +(no matching pin) |la_data_out[90] +(no matching pin) |la_data_out[89] +(no matching pin) |la_data_out[88] +(no matching pin) |la_data_out[87] +(no matching pin) |la_data_out[86] +(no matching pin) |la_data_out[85] +(no matching pin) |la_data_out[84] +(no matching pin) |la_data_out[83] +(no matching pin) |la_data_out[82] +(no matching pin) |la_data_out[81] +(no matching pin) |la_data_out[80] +(no matching pin) |la_data_out[79] +(no matching pin) |la_data_out[78] +(no matching pin) |la_data_out[77] +(no matching pin) |la_data_out[76] +(no matching pin) |la_data_out[75] +(no matching pin) |la_data_out[74] +(no matching pin) |la_data_out[73] +(no matching pin) |la_data_out[72] +(no matching pin) |la_data_out[71] +(no matching pin) |la_data_out[70] +(no matching pin) |la_data_out[69] +(no matching pin) |la_data_out[68] +(no matching pin) |la_data_out[67] +(no matching pin) |la_data_out[66] +(no matching pin) |la_data_out[65] +(no matching pin) |la_data_out[64] +(no matching pin) |la_data_out[63] +(no matching pin) |la_data_out[62] +(no matching pin) |la_data_out[61] +(no matching pin) |la_data_out[60] +(no matching pin) |la_data_out[59] +(no matching pin) |la_data_out[58] +(no matching pin) |la_data_out[57] +(no matching pin) |la_data_out[56] +(no matching pin) |la_data_out[55] +(no matching pin) |la_data_out[54] +(no matching pin) |la_data_out[53] +(no matching pin) |la_data_out[52] +(no matching pin) |la_data_out[51] +(no matching pin) |la_data_out[50] +(no matching pin) |la_data_out[49] +(no matching pin) |la_data_out[48] +(no matching pin) |la_data_out[47] +(no matching pin) |la_data_out[46] +(no matching pin) |la_data_out[45] +(no matching pin) |la_data_out[44] +(no matching pin) |la_data_out[43] +(no matching pin) |la_data_out[42] +(no matching pin) |la_data_out[41] +(no matching pin) |la_data_out[40] +(no matching pin) |la_data_out[39] +(no matching pin) |la_data_out[38] +(no matching pin) |la_data_out[37] +(no matching pin) |la_data_out[36] +(no matching pin) |la_data_out[35] +(no matching pin) |la_data_out[34] +(no matching pin) |la_data_out[33] +(no matching pin) |la_data_out[32] +(no matching pin) |la_data_out[31] +(no matching pin) |la_data_out[30] +(no matching pin) |la_data_out[29] +(no matching pin) |la_data_out[28] +(no matching pin) |la_data_out[27] +(no matching pin) |la_data_out[26] +(no matching pin) |la_data_out[25] +(no matching pin) |la_data_out[24] +(no matching pin) |la_data_out[23] +(no matching pin) |la_data_out[22] +(no matching pin) |la_data_out[21] +(no matching pin) |la_data_out[20] +(no matching pin) |la_data_out[19] +(no matching pin) |la_data_out[18] +(no matching pin) |la_data_out[17] +(no matching pin) |la_data_out[16] +(no matching pin) |la_data_out[15] +(no matching pin) |la_data_out[14] +(no matching pin) |la_data_out[13] +(no matching pin) |la_data_out[12] +(no matching pin) |la_data_out[11] +(no matching pin) |la_data_out[10] +(no matching pin) |la_data_out[9] +(no matching pin) |la_data_out[8] +(no matching pin) |la_data_out[7] +(no matching pin) |la_data_out[6] +(no matching pin) |la_data_out[5] +(no matching pin) |la_data_out[4] +(no matching pin) |la_data_out[3] +(no matching pin) |la_data_out[2] +(no matching pin) |la_data_out[1] +(no matching pin) |la_data_out[0] +(no matching pin) |io_in[26] +(no matching pin) |io_in[25] +(no matching pin) |io_in[24] +(no matching pin) |io_in[23] +(no matching pin) |io_in[22] +(no matching pin) |io_in[21] +(no matching pin) |io_in[20] +(no matching pin) |io_in[19] +(no matching pin) |io_in[18] +(no matching pin) |io_in[17] +(no matching pin) |io_in[16] +(no matching pin) |io_in[15] +(no matching pin) |io_in[14] +(no matching pin) |io_in[13] +(no matching pin) |io_in[12] +(no matching pin) |io_in[11] +(no matching pin) |io_in[10] +(no matching pin) |io_in[9] +(no matching pin) |io_in[8] +(no matching pin) |io_in[7] +(no matching pin) |io_in[6] +(no matching pin) |io_in[5] +(no matching pin) |io_in[4] +(no matching pin) |io_in[3] +(no matching pin) |io_in[2] +(no matching pin) |io_in[1] +(no matching pin) |io_in[0] +(no matching pin) |io_in_3v3[26] +(no matching pin) |io_in_3v3[25] +(no matching pin) |io_in_3v3[24] +(no matching pin) |io_in_3v3[23] +(no matching pin) |io_in_3v3[22] +(no matching pin) |io_in_3v3[21] +(no matching pin) |io_in_3v3[20] +(no matching pin) |io_in_3v3[19] +(no matching pin) |io_in_3v3[18] +(no matching pin) |io_in_3v3[17] +(no matching pin) |io_in_3v3[16] +(no matching pin) |io_in_3v3[15] +(no matching pin) |io_in_3v3[14] +(no matching pin) |io_in_3v3[13] +(no matching pin) |io_in_3v3[12] +(no matching pin) |io_in_3v3[11] +(no matching pin) |io_in_3v3[10] +(no matching pin) |io_in_3v3[9] +(no matching pin) |io_in_3v3[8] +(no matching pin) |io_in_3v3[7] +(no matching pin) |io_in_3v3[6] +(no matching pin) |io_in_3v3[5] +(no matching pin) |io_in_3v3[4] +(no matching pin) |io_in_3v3[3] +(no matching pin) |io_in_3v3[2] +(no matching pin) |io_in_3v3[1] +(no matching pin) |io_in_3v3[0] +(no matching pin) |user_clock2 +(no matching pin) |io_out[26] +(no matching pin) |io_out[25] +(no matching pin) |io_out[24] +(no matching pin) |io_out[23] +(no matching pin) |io_out[22] +(no matching pin) |io_out[21] +(no matching pin) |io_out[20] +(no matching pin) |io_out[19] +(no matching pin) |io_out[18] +(no matching pin) |io_out[17] +(no matching pin) |io_out[16] +(no matching pin) |io_out[15] +(no matching pin) |io_out[14] +(no matching pin) |io_out[13] +(no matching pin) |io_out[12] +(no matching pin) |io_out[11] +(no matching pin) |io_out[10] +(no matching pin) |io_out[9] +(no matching pin) |io_out[8] +(no matching pin) |io_out[7] +(no matching pin) |io_out[6] +(no matching pin) |io_out[5] +(no matching pin) |io_out[4] +(no matching pin) |io_out[3] +(no matching pin) |io_out[2] +(no matching pin) |io_out[1] +(no matching pin) |io_out[0] +(no matching pin) |io_oeb[26] +(no matching pin) |io_oeb[25] +(no matching pin) |io_oeb[24] +(no matching pin) |io_oeb[23] +(no matching pin) |io_oeb[22] +(no matching pin) |io_oeb[21] +(no matching pin) |io_oeb[20] +(no matching pin) |io_oeb[19] +(no matching pin) |io_oeb[18] +(no matching pin) |io_oeb[17] +(no matching pin) |io_oeb[16] +(no matching pin) |io_oeb[15] +(no matching pin) |io_oeb[14] +(no matching pin) |io_oeb[13] +(no matching pin) |io_oeb[12] +(no matching pin) |io_oeb[11] +(no matching pin) |io_oeb[10] +(no matching pin) |io_oeb[9] +(no matching pin) |io_oeb[8] +(no matching pin) |io_oeb[7] +(no matching pin) |io_oeb[6] +(no matching pin) |io_oeb[5] +(no matching pin) |io_oeb[4] +(no matching pin) |io_oeb[3] +(no matching pin) |io_oeb[2] +(no matching pin) |io_oeb[1] +(no matching pin) |io_oeb[0] +(no matching pin) |gpio_analog[17] +(no matching pin) |gpio_analog[16] +(no matching pin) |gpio_analog[15] +(no matching pin) |gpio_analog[14] +(no matching pin) |gpio_analog[13] +(no matching pin) |gpio_analog[12] +(no matching pin) |gpio_analog[11] +(no matching pin) |gpio_analog[10] +(no matching pin) |gpio_analog[9] +(no matching pin) |gpio_analog[8] +(no matching pin) |gpio_analog[7] +(no matching pin) |gpio_analog[6] +(no matching pin) |gpio_analog[5] +(no matching pin) |gpio_analog[4] +(no matching pin) |gpio_analog[3] +(no matching pin) |gpio_analog[2] +(no matching pin) |gpio_analog[1] +(no matching pin) |gpio_analog[0] +(no matching pin) |gpio_noesd[17] +(no matching pin) |gpio_noesd[16] +(no matching pin) |gpio_noesd[15] +(no matching pin) |gpio_noesd[14] +(no matching pin) |gpio_noesd[13] +(no matching pin) |gpio_noesd[12] +(no matching pin) |gpio_noesd[11] +(no matching pin) |gpio_noesd[10] +(no matching pin) |gpio_noesd[9] +(no matching pin) |gpio_noesd[8] +(no matching pin) |gpio_noesd[7] +(no matching pin) |gpio_noesd[6] +(no matching pin) |gpio_noesd[5] +(no matching pin) |gpio_noesd[4] +(no matching pin) |gpio_noesd[3] +(no matching pin) |gpio_noesd[2] +(no matching pin) |gpio_noesd[1] +(no matching pin) |gpio_noesd[0] +(no matching pin) |io_analog[9] +(no matching pin) |io_clamp_high[2] +(no matching pin) |io_clamp_high[1] +(no matching pin) |io_clamp_high[0] +(no matching pin) |io_clamp_low[2] +(no matching pin) |io_clamp_low[1] +(no matching pin) |io_clamp_low[0] +(no matching pin) |user_irq[2] +(no matching pin) |user_irq[1] +(no matching pin) |user_irq[0] +(no matching pin) |la_oenb[127] +(no matching pin) |la_oenb[126] +(no matching pin) |la_oenb[125] +(no matching pin) |la_oenb[124] +(no matching pin) |la_oenb[123] +(no matching pin) |la_oenb[122] +(no matching pin) |la_oenb[121] +(no matching pin) |la_oenb[120] +(no matching pin) |la_oenb[119] +(no matching pin) |la_oenb[118] +(no matching pin) |la_oenb[117] +(no matching pin) |la_oenb[116] +(no matching pin) |la_oenb[115] +(no matching pin) |la_oenb[114] +(no matching pin) |la_oenb[113] +(no matching pin) |la_oenb[112] +(no matching pin) |la_oenb[111] +(no matching pin) |la_oenb[110] +(no matching pin) |la_oenb[109] +(no matching pin) |la_oenb[108] +(no matching pin) |la_oenb[107] +(no matching pin) |la_oenb[106] +(no matching pin) |la_oenb[105] +(no matching pin) |la_oenb[104] +(no matching pin) |la_oenb[103] +(no matching pin) |la_oenb[102] +(no matching pin) |la_oenb[101] +(no matching pin) |la_oenb[100] +(no matching pin) |la_oenb[99] +(no matching pin) |la_oenb[98] +(no matching pin) |la_oenb[97] +(no matching pin) |la_oenb[96] +(no matching pin) |la_oenb[95] +(no matching pin) |la_oenb[94] +(no matching pin) |la_oenb[93] +(no matching pin) |la_oenb[92] +(no matching pin) |la_oenb[91] +(no matching pin) |la_oenb[90] +(no matching pin) |la_oenb[89] +(no matching pin) |la_oenb[88] +(no matching pin) |la_oenb[87] +(no matching pin) |la_oenb[86] +(no matching pin) |la_oenb[85] +(no matching pin) |la_oenb[84] +(no matching pin) |la_oenb[83] +(no matching pin) |la_oenb[82] +(no matching pin) |la_oenb[81] +(no matching pin) |la_oenb[80] +(no matching pin) |la_oenb[79] +(no matching pin) |la_oenb[78] +(no matching pin) |la_oenb[77] +(no matching pin) |la_oenb[76] +(no matching pin) |la_oenb[75] +(no matching pin) |la_oenb[74] +(no matching pin) |la_oenb[73] +(no matching pin) |la_oenb[72] +(no matching pin) |la_oenb[71] +(no matching pin) |la_oenb[70] +(no matching pin) |la_oenb[69] +(no matching pin) |la_oenb[68] +(no matching pin) |la_oenb[67] +(no matching pin) |la_oenb[66] +(no matching pin) |la_oenb[65] +(no matching pin) |la_oenb[64] +(no matching pin) |la_oenb[63] +(no matching pin) |la_oenb[62] +(no matching pin) |la_oenb[61] +(no matching pin) |la_oenb[60] +(no matching pin) |la_oenb[59] +(no matching pin) |la_oenb[58] +(no matching pin) |la_oenb[57] +(no matching pin) |la_oenb[56] +(no matching pin) |la_oenb[55] +(no matching pin) |la_oenb[54] +(no matching pin) |la_oenb[53] +(no matching pin) |la_oenb[52] +(no matching pin) |la_oenb[51] +(no matching pin) |la_oenb[50] +(no matching pin) |la_oenb[49] +(no matching pin) |la_oenb[48] +(no matching pin) |la_oenb[47] +(no matching pin) |la_oenb[46] +(no matching pin) |la_oenb[45] +(no matching pin) |la_oenb[44] +(no matching pin) |la_oenb[43] +(no matching pin) |la_oenb[42] +(no matching pin) |la_oenb[41] +(no matching pin) |la_oenb[40] +(no matching pin) |la_oenb[39] +(no matching pin) |la_oenb[38] +(no matching pin) |la_oenb[37] +(no matching pin) |la_oenb[36] +(no matching pin) |la_oenb[35] +(no matching pin) |la_oenb[34] +(no matching pin) |la_oenb[33] +(no matching pin) |la_oenb[32] +(no matching pin) |la_oenb[31] +(no matching pin) |la_oenb[30] +(no matching pin) |la_oenb[29] +(no matching pin) |la_oenb[28] +(no matching pin) |la_oenb[27] +(no matching pin) |la_oenb[26] +(no matching pin) |la_oenb[25] +(no matching pin) |la_oenb[24] +(no matching pin) |la_oenb[23] +(no matching pin) |la_oenb[22] +(no matching pin) |la_oenb[21] +(no matching pin) |la_oenb[20] +(no matching pin) |la_oenb[19] +(no matching pin) |la_oenb[18] +(no matching pin) |la_oenb[17] +(no matching pin) |la_oenb[16] +(no matching pin) |la_oenb[15] +(no matching pin) |la_oenb[14] +(no matching pin) |la_oenb[13] +(no matching pin) |la_oenb[12] +(no matching pin) |la_oenb[11] +(no matching pin) |la_oenb[10] +(no matching pin) |la_oenb[9] +(no matching pin) |la_oenb[8] +(no matching pin) |la_oenb[7] +(no matching pin) |la_oenb[6] +(no matching pin) |la_oenb[5] +(no matching pin) |la_oenb[4] +(no matching pin) |la_oenb[3] +(no matching pin) |la_oenb[2] +(no matching pin) |la_oenb[1] +(no matching pin) |la_oenb[0] +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes user_analog_project_wrapper and user_analog_project_wrapper are equivalent. +Circuits match uniquely.
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index a3f3994..d3f24eb 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -1,223 +1,1130 @@ * NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A -.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW c2_n3079_n3000# m4_n3179_n3100# VSUBS -X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +.subckt io_clamp vdd vss +D0 w_96698_n78672# vss sky130_fd_pr__diode_pd2nw_05v5 area=2.25e+16p +D1 w_96698_n6672# w_96698_n42672# sky130_fd_pr__diode_pd2nw_05v5 area=2.25e+16p +D2 vdd w_96698_n6672# sky130_fd_pr__diode_pd2nw_05v5 area=2.25e+16p +D3 w_96698_n42672# w_96698_n78672# sky130_fd_pr__diode_pd2nw_05v5 area=2.25e+16p .ends -.subckt sky130_fd_sc_hvl__buf_8 A VGND VNB VPB VPWR X -X0 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X2 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X3 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X4 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X5 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X6 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X8 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X9 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X10 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X12 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X14 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X15 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X16 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X18 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X19 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X20 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X21 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u +.subckt Class_D_post vp_p out_p vin_p vcmp_p vin avdd vin_n vn_p dvdd vn_n out_n vref ++ vtriang vss vcmp_n iin_15u vp_n w_n49798_13484# w_n49798_65757# w_n47900_14200# +X0 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1 out_n vn_p dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4e+06u l=150000u M=3000 +X2 vss vn_n out_n vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=4e+06u l=150000u M=600 +X3 out_p vp_p dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4e+06u l=150000u M=3000 +X4 out_p vp_n vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=4e+06u l=150000u M=600 +X5 a_n61221_57011# a_n63453_57011# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=64 +X6 avdd a_n91733_42923# vin_p avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=48 +X7 vss a_n64397_22887# a_n64397_22887# vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X8 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X9 vss a_n16362_6492# vn_p vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=80 +X10 a_n59836_35385# a_n91733_39491# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=48 +X11 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X12 a_n65384_39513# a_n91733_41779# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=48 +X13 a_n91733_45211# iin_15u vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=2e+06u M=8 +X14 a_n62068_35385# a_n63012_35297# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X15 avdd a_n91733_37203# a_n61221_22975# avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=48 +X16 a_n61221_57011# a_n91733_44067# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=48 +X17 w_n48521_59023# a_n59836_35385# a_n48325_56923# w_n48521_59023# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X18 avdd a_n91733_41779# a_n91733_41779# avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X19 a_n48544_35385# a_n49488_35297# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X20 avdd a_n91733_45211# a_n91733_45211# avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X21 vcmp_n a_n47381_18289# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=64 +X22 w_n78659_43954# vin a_n77519_44173# w_n78659_43954# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X23 vp_p a_n16362_71100# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=80 +X24 vss a_n19274_79650# a_n22132_76606# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=4 +X25 a_n61221_22975# a_n63453_18290# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=64 +X26 avdd a_n91733_44067# w_n64593_59023# avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X27 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X28 vss a_n77519_31129# vin_n vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=64 +X29 a_n78463_31041# a_n79461_37096# w_n78659_33141# w_n78659_33141# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X30 a_n91733_42923# a_n91733_42923# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X31 vp_p a_n16362_71100# dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=160 +X32 w_n78659_43954# a_n91733_42923# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X33 vss a_n22132_76606# vp_n vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=18 +X34 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X35 a_n48544_35385# a_n48744_37519# w_n49684_37397# w_n49684_37397# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X36 vcmp_n a_n91733_36059# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=48 +X37 a_n63453_57011# vref w_n64593_59023# w_n64593_59023# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X38 a_n48744_37519# a_n65384_39513# vss sky130_fd_pr__res_xhigh_po w=350000u l=9e+06u +X39 vcmp_p a_n47381_57011# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=64 +X40 a_n63012_35297# a_n63012_35297# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X41 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X42 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X43 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X44 w_n64593_18071# a_n68715_22497# a_n64397_22887# w_n64593_18071# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X45 vss a_n64397_56923# a_n63453_57011# vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X46 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X47 a_n78463_48770# a_n78463_48770# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X48 dvdd a_n21974_78024# a_n16362_71100# dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=36 +X49 a_n16362_6492# a_n21974_3362# dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=36 +X50 a_n91733_44067# iin_15u vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=2e+06u M=8 +X51 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X52 dvdd a_n19274_79650# a_n22132_76606# dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=8 +X53 vcmp_p a_n91733_45211# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=48 +X54 a_n91733_44067# a_n91733_44067# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X55 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X56 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X57 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X58 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X59 a_n59836_35385# a_n62068_35385# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=64 +X60 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X61 a_n65384_39513# a_n48544_35385# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=64 +X62 a_n47381_18289# a_n61221_22975# w_n48521_18070# w_n48521_18070# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X63 vn_p a_n16362_6492# dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=160 +X64 avdd a_n91733_36059# w_n48521_18070# avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X65 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X66 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X67 vss a_n48325_22886# a_n48325_22886# vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X68 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X69 w_n63208_37397# vref a_n62068_35385# w_n63208_37397# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X70 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X71 a_n68715_23451# a_n67283_23133# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X72 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X73 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X74 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X75 avdd a_n91733_45211# w_n48521_59023# avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X76 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X77 avdd a_n91733_38347# vin_n avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=48 +X78 a_n91733_36059# a_n91733_36059# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X79 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X80 avdd a_n91733_37203# a_n91733_37203# avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X81 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X82 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X83 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X84 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X85 a_n63453_18290# vref w_n64593_18071# w_n64593_18071# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X86 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X87 dvdd a_n22132_4780# vn_n dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=36 +X88 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X89 a_n91733_38347# a_n91733_38347# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X90 a_n91733_39491# a_n91733_39491# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X91 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X92 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X93 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X94 vss a_n77519_44173# vin_p vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=64 +X95 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X96 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X97 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X98 vss a_n64397_22887# a_n63453_18290# vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X99 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X100 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X101 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X102 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X103 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X104 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X105 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X106 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X107 a_n63012_35297# a_n65384_41739# w_n63208_37397# w_n63208_37397# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X108 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X109 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X110 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X111 w_n78659_33141# a_n91733_38347# avdd avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X112 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X113 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X114 dvdd a_n22132_76606# vp_n dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=36 +X115 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X116 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X117 vss a_n78463_31041# a_n78463_31041# vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X118 dvdd vcmp_p a_n22016_76698# dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X119 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X120 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X121 a_n22132_4780# a_n19274_n434# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=4 +X122 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X123 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X124 a_n66616_40149# a_n65384_40467# vss sky130_fd_pr__res_xhigh_po w=350000u l=4e+06u +X125 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X126 a_n21974_3362# a_n19274_6492# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=4 +X127 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X128 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X129 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X130 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X131 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X132 a_n78463_48770# vin_p w_n78659_43954# w_n78659_43954# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X133 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X134 a_n16362_71100# a_n21974_78024# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=18 +X135 a_n77519_31129# a_n78463_31041# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X136 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X137 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X138 w_n64593_59023# a_n68715_58873# a_n64397_56923# w_n64593_59023# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X139 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X140 vss a_n64397_56923# a_n64397_56923# vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X141 vss a_n78463_48770# a_n77519_44173# vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X142 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X143 a_n47381_57011# a_n48325_56923# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X144 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X145 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X146 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X147 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X148 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X149 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X150 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X151 w_n78659_33141# vref a_n77519_31129# w_n78659_33141# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X152 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X153 avdd a_n91733_41779# w_n49684_37397# avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X154 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X155 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X156 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X157 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X158 w_n48521_59023# a_n61221_57011# a_n47381_57011# w_n48521_59023# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X159 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X160 a_n49488_35297# a_n49488_35297# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X161 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X162 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X163 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X164 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X165 dvdd a_n22016_76698# a_n19274_72724# dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=2 +X166 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X167 a_n47381_18289# a_n48325_22886# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X168 avdd a_n91733_39491# w_n63208_37397# avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X169 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X170 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X171 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X172 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X173 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X174 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X175 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X176 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X177 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X178 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X179 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X180 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X181 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X182 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X183 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X184 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X185 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X186 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X187 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X188 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X189 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X190 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X191 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X192 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X193 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X194 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X195 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X196 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X197 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X198 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X199 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X200 dvdd a_n22016_77504# a_n19274_79650# dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=2 +X201 vn_n a_n22132_4780# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=18 +X202 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X203 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X204 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X205 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X206 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X207 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X208 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X209 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X210 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X211 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X212 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X213 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X214 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X215 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X216 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X217 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X218 dvdd a_n19274_6492# a_n21974_3362# dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=8 +X219 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X220 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X221 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X222 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X223 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X224 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X225 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X226 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X227 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X228 a_n73329_46276# a_n77519_44173# vss sky130_fd_pr__res_xhigh_po w=350000u l=500000u +X229 avdd a_n91733_37203# w_n64593_18071# avdd sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=1e+06u M=24 +X230 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X231 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X232 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X233 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X234 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X235 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X236 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X237 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X238 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X239 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X240 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X241 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X242 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X243 w_n49684_37397# vref a_n49488_35297# w_n49684_37397# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X244 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X245 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X246 a_n22016_2920# a_n22542_3082# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X247 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X248 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X249 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X250 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X251 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X252 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X253 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X254 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X255 vss iin_15u a_n91733_38347# vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=2e+06u M=8 +X256 a_n22016_4346# a_n22132_4780# dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X257 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X258 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X259 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X260 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X261 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X262 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X263 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X264 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X265 vss a_n21974_3362# a_n16362_6492# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=18 +X266 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X267 a_n48325_56923# a_n48325_56923# vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=1e+06u M=16 +X268 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X269 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X270 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X271 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X272 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X273 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X274 dvdd a_n21974_3362# a_n22016_3540# dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X275 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X276 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X277 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X278 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X279 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X280 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X281 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X282 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X283 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X284 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X285 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X286 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X287 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X288 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X289 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X290 a_n66616_39513# a_n65384_39831# vss sky130_fd_pr__res_xhigh_po w=350000u l=4e+06u +X291 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X292 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X293 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X294 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X295 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X296 a_n66616_41421# a_n65384_41103# vss sky130_fd_pr__res_xhigh_po w=350000u l=4e+06u +X297 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X298 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X299 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X300 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X301 a_n68715_58873# a_n67283_58555# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X302 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X303 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X304 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X305 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X306 a_n74623_35024# a_n79461_37096# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X307 a_n60801_60857# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=1.4e+07u +X308 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X309 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X310 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X311 a_n21974_78024# a_n19274_72724# dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=8 +X312 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X313 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X314 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X315 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X316 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X317 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X318 a_n91733_42923# iin_15u vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=2e+06u M=8 +X319 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X320 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X321 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X322 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X323 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X324 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X325 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X326 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X327 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X328 vss a_n19274_72724# a_n21974_78024# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=4 +X329 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X330 a_n68715_22815# a_n67283_23133# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X331 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X332 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X333 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X334 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X335 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X336 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X337 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X338 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X339 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X340 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X341 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X342 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X343 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X344 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X345 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X346 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X347 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X348 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X349 a_n22542_77506# vcmp_p dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X350 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X351 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X352 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X353 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X354 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X355 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X356 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X357 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X358 vss iin_15u a_n91733_39491# vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=2e+06u M=8 +X359 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X360 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X361 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X362 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X363 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X364 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X365 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X366 a_n66616_40149# a_n65384_39831# vss sky130_fd_pr__res_xhigh_po w=350000u l=4e+06u +X367 a_n19274_6492# a_n22016_4346# dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=2 +X368 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X369 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X370 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X371 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X372 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X373 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X374 dvdd a_n19274_n434# a_n22132_4780# dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=8 +X375 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X376 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X377 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X378 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X379 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X380 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X381 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X382 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X383 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X384 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X385 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X386 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X387 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X388 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X389 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X390 a_n59415_38846# a_n59836_35385# sky130_fd_pr__cap_mim_m3_1 l=1.8e+07u w=2.7e+07u +X391 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X392 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X393 a_n68715_58873# a_n66877_84715# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X394 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X395 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X396 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X397 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X398 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X399 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X400 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X401 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X402 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X403 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X404 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X405 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X406 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X407 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X408 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X409 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X410 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X411 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X412 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X413 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X414 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X415 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X416 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X417 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X418 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X419 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X420 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X421 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X422 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X423 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X424 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X425 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X426 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X427 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X428 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X429 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X430 a_n68715_57601# a_n67283_57283# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X431 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X432 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X433 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X434 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X435 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X436 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X437 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X438 a_n68715_24087# a_n67283_23769# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X439 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X440 w_n48521_18070# a_n59836_35385# a_n48325_22886# w_n48521_18070# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=1e+06u M=16 +X441 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X442 a_n65384_41739# a_n59836_35385# sky130_fd_pr__cap_mim_m3_1 l=1.5e+07u w=1.5e+07u +X443 vss iin_15u iin_15u vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=2e+06u M=8 +X444 a_n22016_78124# a_n22542_77506# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X445 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X446 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X447 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X448 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X449 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X450 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X451 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X452 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X453 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X454 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X455 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X456 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X457 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X458 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X459 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X460 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X461 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X462 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X463 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X464 a_n66559_83283# a_n66241_84715# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X465 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X466 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X467 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X468 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X469 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X470 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X471 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X472 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X473 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X474 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X475 a_n74623_35024# vin_n vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X476 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X477 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X478 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X479 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X480 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X481 a_n91733_41779# iin_15u vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=2e+06u M=8 +X482 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X483 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X484 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X485 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X486 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X487 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X488 a_n73329_46276# vin_p sky130_fd_pr__cap_mim_m3_1 l=1.4e+07u w=1.4e+07u +X489 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X490 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X491 a_n66877_n3717# a_n68715_22497# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X492 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X493 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X494 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X495 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X496 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X497 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X498 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X499 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X500 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X501 a_n19274_79650# a_n22016_77504# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u +X502 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X503 a_n68715_22815# a_n67283_22497# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X504 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X505 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X506 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X507 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X508 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X509 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X510 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X511 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X512 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X513 a_n66616_39513# a_n65384_39513# vss sky130_fd_pr__res_xhigh_po w=350000u l=4e+06u +X514 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X515 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X516 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X517 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X518 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X519 a_n66616_40785# a_n65384_41103# vss sky130_fd_pr__res_xhigh_po w=350000u l=4e+06u +X520 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X521 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X522 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X523 a_n68715_58237# a_n67283_58555# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X524 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X525 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X526 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X527 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X528 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X529 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X530 a_n19274_n434# a_n22016_3540# dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u M=2 +X531 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X532 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X533 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X534 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X535 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X536 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X537 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X538 a_n63453_57011# a_n60801_60857# vss sky130_fd_pr__res_xhigh_po w=350000u l=2.8e+06u +X539 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X540 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X541 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X542 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X543 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X544 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X545 a_n22542_77506# vcmp_p vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X546 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X547 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X548 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X549 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X550 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X551 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X552 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X553 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X554 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X555 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X556 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X557 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X558 a_n66559_83283# a_n66877_84715# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X559 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X560 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X561 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X562 a_n66241_n3717# a_n66559_n2285# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X563 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X564 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X565 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X566 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X567 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X568 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X569 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X570 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X571 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X572 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X573 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X574 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X575 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X576 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X577 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X578 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X579 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X580 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X581 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X582 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X583 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X584 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X585 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X586 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X587 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X588 a_n22542_3082# vcmp_n dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X589 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X590 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X591 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X592 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X593 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X594 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X595 a_n22016_77504# a_n21974_78024# a_n22016_78124# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X596 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X597 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X598 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X599 a_n68715_23451# a_n67283_23769# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X600 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X601 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X602 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X603 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X604 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X605 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X606 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X607 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X608 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X609 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X610 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X611 a_n73329_34733# vin_n sky130_fd_pr__cap_mim_m3_1 l=1.4e+07u w=1.4e+07u +X612 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X613 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X614 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X615 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X616 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X617 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X618 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X619 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X620 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X621 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X622 a_n22016_4346# vcmp_n a_n22016_4966# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X623 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X624 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X625 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X626 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X627 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X628 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X629 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X630 a_n65384_41739# a_n59836_35385# sky130_fd_pr__cap_mim_m3_1 l=1.5e+07u w=1.5e+07u +X631 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X632 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X633 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X634 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X635 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X636 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X637 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X638 a_n22016_76078# a_n22132_76606# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X639 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X640 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X641 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X642 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X643 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X644 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X645 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X646 a_n66877_n3717# a_n66559_n2285# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X647 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X648 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X649 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X650 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X651 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X652 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X653 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X654 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X655 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X656 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X657 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X658 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X659 a_n22016_3540# a_n22542_3082# dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X660 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X661 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X662 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X663 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X664 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X665 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X666 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X667 a_n22016_77504# a_n22542_77506# dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X668 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X669 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X670 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X671 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X672 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X673 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X674 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X675 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X676 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X677 a_n65384_41739# a_n59836_35385# sky130_fd_pr__cap_mim_m3_1 l=1.5e+07u w=1.5e+07u +X678 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X679 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X680 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X681 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X682 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X683 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X684 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X685 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X686 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X687 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X688 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X689 a_n91733_37203# iin_15u vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=2e+06u M=8 +X690 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X691 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X692 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X693 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X694 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X695 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X696 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X697 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X698 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X699 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X700 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X701 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X702 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X703 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X704 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X705 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X706 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X707 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X708 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X709 a_n48544_35385# a_n44354_38989# vss sky130_fd_pr__res_xhigh_po w=350000u l=500000u +X710 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X711 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X712 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X713 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X714 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X715 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X716 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X717 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X718 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X719 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X720 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X721 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X722 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X723 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X724 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X725 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X726 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X727 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X728 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X729 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X730 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X731 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X732 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X733 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X734 a_n65287_83283# a_n65605_84715# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X735 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X736 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X737 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X738 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X739 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X740 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X741 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X742 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X743 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X744 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X745 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X746 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X747 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X748 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X749 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X750 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X751 a_n65923_83283# a_n66241_84715# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X752 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X753 a_n19274_72724# a_n22016_76698# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u +X754 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X755 a_n68715_58237# a_n67283_57919# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X756 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X757 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X758 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X759 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X760 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X761 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X762 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X763 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X764 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X765 a_n22542_3082# vcmp_n vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X766 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X767 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X768 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X769 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X770 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X771 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X772 a_n60801_60857# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.4e+07u w=3e+07u +X773 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X774 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X775 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X776 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X777 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X778 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X779 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X780 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X781 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X782 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X783 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X784 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X785 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X786 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X787 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X788 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X789 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X790 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X791 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X792 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X793 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X794 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X795 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X796 a_n66616_41421# a_n65384_41739# vss sky130_fd_pr__res_xhigh_po w=350000u l=4e+06u +X797 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X798 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X799 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X800 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X801 a_n59836_35385# a_n48744_37519# vss sky130_fd_pr__res_xhigh_po w=350000u l=4e+06u +X802 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X803 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X804 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X805 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X806 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X807 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X808 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X809 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X810 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X811 a_n22016_76698# vcmp_p a_n22016_76078# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X812 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X813 a_n65384_41739# a_n59836_35385# sky130_fd_pr__cap_mim_m3_1 l=1.5e+07u w=1.5e+07u +X814 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X815 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X816 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X817 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X818 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X819 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X820 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X821 a_n65605_n3717# a_n65287_n2285# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X822 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X823 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X824 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X825 dvdd a_n21974_78024# a_n22016_77504# dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X826 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X827 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X828 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X829 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X830 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X831 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X832 a_n65384_41739# a_n59836_35385# sky130_fd_pr__cap_mim_m3_1 l=1.5e+07u w=1.5e+07u +X833 a_n77519_31129# a_n73329_34733# vss sky130_fd_pr__res_xhigh_po w=350000u l=500000u +X834 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X835 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X836 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X837 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X838 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X839 a_n60801_20151# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.4e+07u w=3e+07u +X840 a_n66241_n3717# a_n65923_n2285# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X841 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X842 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X843 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X844 a_n65384_41739# a_n59836_35385# sky130_fd_pr__cap_mim_m3_1 l=1.5e+07u w=1.5e+07u +X845 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X846 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X847 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X848 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X849 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X850 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X851 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X852 a_n91733_36059# iin_15u vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4e+06u l=2e+06u M=8 +X853 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X854 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X855 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X856 a_n60801_20151# a_n63453_18290# vss sky130_fd_pr__res_xhigh_po w=350000u l=2.8e+06u +X857 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X858 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X859 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X860 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X861 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X862 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X863 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X864 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X865 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X866 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X867 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X868 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X869 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X870 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X871 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X872 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X873 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X874 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X875 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X876 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X877 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X878 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X879 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X880 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X881 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X882 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X883 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X884 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X885 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X886 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X887 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X888 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X889 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X890 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X891 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X892 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X893 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X894 a_n68715_56965# a_n67283_57283# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X895 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X896 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X897 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X898 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X899 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X900 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X901 a_n22016_3540# a_n21974_3362# a_n22016_2920# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X902 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X903 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X904 a_n62068_35385# a_n59415_38846# vss sky130_fd_pr__res_xhigh_po w=350000u l=1.4e+06u +X905 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X906 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X907 a_n65923_83283# a_n65605_84715# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X908 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X909 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X910 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X911 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X912 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X913 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X914 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X915 dvdd vcmp_n a_n22016_4346# dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X916 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X917 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X918 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X919 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X920 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X921 a_n68715_57601# a_n67283_57919# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X922 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X923 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X924 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X925 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X926 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X927 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X928 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X929 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X930 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X931 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X932 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X933 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X934 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X935 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X936 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X937 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X938 a_n66616_40785# a_n65384_40467# vss sky130_fd_pr__res_xhigh_po w=350000u l=4e+06u +X939 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X940 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X941 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X942 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X943 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X944 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X945 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X946 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X947 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X948 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X949 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X950 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X951 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X952 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X953 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X954 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X955 a_n44354_38989# a_n65384_39513# sky130_fd_pr__cap_mim_m3_1 l=1.4e+07u w=1.4e+07u +X956 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X957 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X958 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X959 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X960 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X961 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X962 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X963 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X964 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X965 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X966 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X967 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X968 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X969 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X970 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X971 a_n68715_22497# a_n67283_22497# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X972 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X973 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X974 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X975 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X976 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X977 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X978 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X979 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X980 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X981 a_n68715_24087# vin_n vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X982 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X983 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X984 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X985 a_n79779_35664# a_n79461_37096# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X986 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X987 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X988 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X989 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X990 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X991 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X992 a_n22016_76698# a_n22132_76606# dvdd dvdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X993 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X994 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X995 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X996 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X997 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X998 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X999 a_n65605_n3717# a_n65923_n2285# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X1000 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1001 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1002 a_n65287_83283# out_p vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X1003 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1004 a_n22016_77504# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1005 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1006 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1007 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1008 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1009 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1010 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1011 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1012 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1013 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1014 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1015 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1016 a_n60801_20151# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=1.4e+07u +X1017 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1018 a_n22016_4966# a_n22132_4780# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=150000u +X1019 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1020 a_n68715_58873# a_n61221_57011# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X1021 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1022 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1023 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1024 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1025 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1026 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1027 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1028 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1029 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1030 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1031 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1032 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1033 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1034 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1035 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1036 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1037 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1038 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X1039 a_n68715_22497# a_n61221_22975# sky130_fd_pr__cap_mim_m3_1 l=1.75e+07u w=1.75e+07u +X1040 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1041 a_n65384_41739# a_n59836_35385# sky130_fd_pr__cap_mim_m3_1 l=1.5e+07u w=1.5e+07u +X1042 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X1043 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X1044 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1045 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X1046 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1047 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1048 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1049 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1050 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1051 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1052 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1053 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1054 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1055 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1056 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1057 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1058 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1059 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1060 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1061 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1062 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1063 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1064 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1065 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1066 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1067 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1068 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1069 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1070 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1071 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1072 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1073 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1074 a_n65384_41739# a_n59836_35385# sky130_fd_pr__cap_mim_m3_1 l=1.5e+07u w=1.5e+07u +X1075 a_n68715_56965# vin_p vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X1076 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1077 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1078 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1079 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1080 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X1081 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1082 a_n19274_n434# a_n22016_3540# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u +X1083 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1084 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1085 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1086 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X1087 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1088 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1089 a_n79779_35664# vin vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X1090 a_n19274_6492# a_n22016_4346# vss vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=5e+06u l=150000u +X1091 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1092 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1093 a_n22016_76698# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1094 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1095 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1096 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X1097 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1098 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1099 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1100 dvdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1101 a_n22016_4346# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1102 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1103 vss dvdd sky130_fd_pr__cap_mim_m3_2 l=1.6e+07u w=1.6e+07u +X1104 out_n a_n65287_n2285# vss sky130_fd_pr__res_xhigh_po w=350000u l=5e+06u +X1105 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1106 iin_15u vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1107 a_n22016_3540# vss sky130_fd_pr__cap_mim_m3_1 l=1.775e+07u w=1.775e+07u +X1108 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1109 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +X1110 avdd vss sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u .ends -.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ a_n683_n200# a_n189_n297# a_29_n297# a_189_n200# -+ a_n901_n200# a_247_n297# a_n407_n297# a_465_n297# a_407_n200# a_n625_n297# a_683_n297# -+ a_625_n200# a_n843_n297# w_n1101_n497# a_843_n200# a_n29_n200# a_n247_n200# a_n465_n200# -+ VSUBS -X0 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X2 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X4 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X5 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X6 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X7 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -.ends - -.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS a_n792_n200# a_298_n200# a_516_n200# a_734_n200# -+ w_n962_n458# a_138_n288# a_n298_n288# a_80_n200# a_356_n288# a_n516_n288# a_574_n288# -+ a_n734_n288# a_n138_n200# a_n356_n200# a_n574_n200# a_n80_n288# -X0 a_n574_n200# a_n734_n288# a_n792_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X1 a_734_n200# a_574_n288# a_516_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X2 a_298_n200# a_138_n288# a_80_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X3 a_n138_n200# a_n298_n288# a_n356_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X4 a_n356_n200# a_n516_n288# a_n574_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X5 a_516_n200# a_356_n288# a_298_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X6 a_80_n200# a_n80_n288# a_n138_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -.ends - -.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 a_n1806_2500# a_n4122_n2932# a_n5280_2500# -+ a_2054_n2932# a_896_n2932# a_4756_2500# a_3598_n2932# a_3212_2500# a_n3736_n2932# -+ a_1668_n2932# a_n1806_n2932# a_5142_n2932# a_896_2500# a_510_n2932# a_n3350_2500# -+ a_n4508_2500# a_3212_n2932# a_n4894_2500# a_1282_2500# w_n5446_n3098# a_4756_n2932# -+ a_2826_2500# a_2826_n2932# a_n2192_n2932# a_n1034_2500# a_n2578_2500# a_n1420_2500# -+ a_n2964_2500# a_n648_n2932# a_n648_2500# a_n5280_n2932# a_n3350_n2932# a_4370_2500# -+ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_n4894_n2932# a_124_2500# a_n2964_n2932# -+ a_n4122_2500# a_2054_2500# a_510_2500# a_n4508_n2932# a_4370_n2932# a_3598_2500# -+ a_3984_2500# a_2440_n2932# a_2440_2500# a_3984_n2932# a_n2192_2500# a_n3736_2500# -+ a_1668_2500# a_n262_n2932# a_n262_2500# a_n1034_n2932# a_5142_2500# a_n2578_n2932# -X0 a_n1420_n2932# a_n1420_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X1 a_n2578_n2932# a_n2578_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X2 a_n1806_n2932# a_n1806_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X3 a_3212_n2932# a_3212_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X4 a_3598_n2932# a_3598_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X5 a_n2964_n2932# a_n2964_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X6 a_2826_n2932# a_2826_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X7 a_4370_n2932# a_4370_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X8 a_3984_n2932# a_3984_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X9 a_n262_n2932# a_n262_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X10 a_n3350_n2932# a_n3350_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X11 a_n4122_n2932# a_n4122_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X12 a_n3736_n2932# a_n3736_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X13 a_5142_n2932# a_5142_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X14 a_n4894_n2932# a_n4894_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X15 a_1282_n2932# a_1282_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X16 a_4756_n2932# a_4756_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X17 a_124_n2932# a_124_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X18 a_510_n2932# a_510_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X19 a_896_n2932# a_896_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X20 a_n5280_n2932# a_n5280_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X21 a_n648_n2932# a_n648_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X22 a_n1034_n2932# a_n1034_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X23 a_n4508_n2932# a_n4508_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X24 a_n2192_n2932# a_n2192_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X25 a_2054_n2932# a_2054_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X26 a_1668_n2932# a_1668_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -X27 a_2440_n2932# a_2440_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u -.ends - -.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200# -+ VSUBS -X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -.ends - -.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VNB VPB VPWR X -X0 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X1 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u -X2 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X3 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u -X4 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u -X5 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X6 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X7 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X8 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u -X9 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u -.ends - -.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200# -+ VSUBS -X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -.ends - -.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288# -X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -.ends - -.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288# -X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -.ends - -.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW c1_n3036_n3000# m3_n3136_n3100# VSUBS -X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u -.ends - -.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV a_n792_n200# a_138_n297# a_n298_n297# -+ a_298_n200# a_356_n297# a_n516_n297# a_574_n297# a_516_n200# a_n734_n297# a_734_n200# -+ a_n80_n297# a_80_n200# a_n138_n200# a_n356_n200# a_n574_n200# w_n992_n497# VSUBS -X0 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X1 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X2 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X3 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X4 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X5 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -X6 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -.ends - -.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200# -+ VSUBS -X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u -.ends - -.subckt sky130_fd_sc_hvl__inv_8 A VGND VNB VPB VPWR Y -X0 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X1 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X2 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X3 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X4 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X5 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X6 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X7 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X8 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X9 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X10 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X11 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X12 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X13 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u -X14 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -X15 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u -.ends - -.subckt example_por vdd3v3 vdd1v8 vss porb_h por_l porb_l -Xsky130_fd_pr__cap_mim_m3_2_W5U4AW_0 vss sky130_fd_sc_hvl__schmittbuf_1_0/A vss sky130_fd_pr__cap_mim_m3_2_W5U4AW -Xsky130_fd_sc_hvl__buf_8_1 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd1v8 vdd1v8 porb_l -+ sky130_fd_sc_hvl__buf_8 -Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# -+ vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# -+ m1_502_7653# vdd3v3 vdd3v3 vdd3v3 m1_502_7653# vdd3v3 vss sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ -Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 m1_721_6815# vss m1_721_6815# vss vss m1_721_6815# -+ m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# vss -+ m1_721_6815# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS -Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 li_3322_5813# li_1391_165# vss li_7567_165# -+ li_6023_165# vdd3v3 li_9111_165# li_8726_5813# li_1391_165# li_6795_165# li_3707_165# -+ vss li_6410_5813# li_6023_165# li_1778_5813# li_1006_5813# li_8339_165# vss li_6410_5813# -+ vss li_9883_165# li_7954_5813# li_8339_165# li_2935_165# li_4094_5813# li_2550_5813# -+ li_4094_5813# li_2550_5813# li_4479_165# li_4866_5813# vss li_2163_165# li_9498_5813# -+ li_6795_165# li_5251_165# li_3707_165# li_619_165# li_5638_5813# li_2163_165# li_1006_5813# -+ li_7182_5813# li_5638_5813# li_619_165# li_9883_165# li_8726_5813# li_9498_5813# -+ li_7567_165# li_7954_5813# li_9111_165# li_3322_5813# li_1778_5813# li_7182_5813# -+ li_5251_165# li_4866_5813# li_4479_165# vss li_2935_165# sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 -Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 m1_185_6573# m1_721_6815# vdd3v3 m1_2993_7658# -+ vss sky130_fd_pr__pfet_g5v0d10v5_3YBPVB -Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vss vdd3v3 -+ vdd3v3 sky130_fd_sc_hvl__inv_8_0/A sky130_fd_sc_hvl__schmittbuf_1 -Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 m1_2756_6573# m1_4283_8081# vdd3v3 m1_2756_6573# -+ vss sky130_fd_pr__pfet_g5v0d10v5_3YBPVB -Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 m1_2756_6573# sky130_fd_sc_hvl__schmittbuf_1_0/A -+ vdd3v3 m1_6249_7690# vss sky130_fd_pr__pfet_g5v0d10v5_3YBPVB -Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 m1_185_6573# m1_502_7653# vdd3v3 m1_185_6573# -+ vss sky130_fd_pr__pfet_g5v0d10v5_3YBPVB -Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 m1_4283_8081# m1_6249_7690# vdd3v3 vdd3v3 vss -+ sky130_fd_pr__pfet_g5v0d10v5_YUHPXE -Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 vss m1_2756_6573# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_PKVMTM -Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 vss m1_185_6573# vss li_2550_5813# sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC -Xsky130_fd_pr__cap_mim_m3_1_WRT4AW_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vss sky130_fd_pr__cap_mim_m3_1_WRT4AW -Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081# -+ m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081# -+ vdd3v3 m1_4283_8081# vdd3v3 m1_4283_8081# vdd3v3 vss sky130_fd_pr__pfet_g5v0d10v5_YEUEBV -Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 m1_502_7653# m1_2993_7658# vdd3v3 vdd3v3 vss -+ sky130_fd_pr__pfet_g5v0d10v5_YUHPBG -Xsky130_fd_sc_hvl__inv_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd1v8 vdd1v8 por_l -+ sky130_fd_sc_hvl__inv_8 -Xsky130_fd_sc_hvl__buf_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd3v3 vdd3v3 porb_h -+ sky130_fd_sc_hvl__buf_8 -.ends - -.subckt user_analog_proj_example example_por_0/por_l VSUBS example_por_1/por_l example_por_0/vdd1v8 -+ example_por_1/vdd3v3 example_por_1/porb_l example_por_0/vdd3v3 example_por_1/porb_h -+ example_por_0/porb_l example_por_0/porb_h example_por_1/vdd1v8 -Xexample_por_0 example_por_0/vdd3v3 example_por_0/vdd1v8 VSUBS example_por_0/porb_h -+ example_por_0/por_l example_por_0/porb_l example_por -Xexample_por_1 example_por_1/vdd3v3 example_por_1/vdd1v8 VSUBS example_por_1/porb_h -+ example_por_1/por_l example_por_1/porb_l example_por +.subckt ESD vin vdd vss w_61637_n30343# +D0 vss vin sky130_fd_pr__diode_pw2nd_05v5 area=2.25e+16p +D1 vin vdd sky130_fd_pr__diode_pd2nw_05v5 area=2.25e+16p .ends .subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11] @@ -227,8 +1134,8 @@ + gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16] + gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5] + gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10] -+ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[7] io_analog[8] io_analog[9] -+ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0] ++ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7] ++ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0] + io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] + io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] + io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] @@ -326,7 +1233,26 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -Xuser_analog_proj_example_0 io_out[16] vssa1 io_out[12] vccd1 vdda1 io_out[11] io_clamp_high[0] -+ gpio_analog[3] io_out[15] gpio_analog[7] vccd1 user_analog_proj_example +Xio_clamp_1 io_analog[5] vssa2 io_clamp +Xio_clamp_0 vdda2 vssa2 io_clamp +XClass_D_post_0 Class_D_post_0/vp_p io_analog[6] Class_D_post_0/vin_p Class_D_post_0/vcmp_p ++ io_analog[10] vdda2 Class_D_post_0/vin_n Class_D_post_0/vn_p io_analog[5] Class_D_post_0/vn_n ++ io_analog[4] io_analog[1] Class_D_post_0/vtriang vssa2 Class_D_post_0/vcmp_n io_analog[0] ++ Class_D_post_0/vp_n vssa2 vssa2 vssa2 Class_D_post +XESD_0 io_analog[6] io_analog[5] vssa2 vssa2 ESD +XESD_1 io_analog[4] io_analog[5] vssa2 vssa2 ESD +XESD_2 io_analog[10] vdda2 vssa2 vssa2 ESD +XESD_3 io_analog[1] vdda1 vssa2 vssa2 ESD +XESD_4 io_analog[0] vdda1 vssa2 vssa2 ESD +R0 vssd2 vssa2 sky130_fd_pr__res_generic_m3 w=7.4e+07u l=2.055e+07u +R1 vccd2 io_analog[5] sky130_fd_pr__res_generic_m5 w=7.42e+07u l=1.885e+07u +R2 io_analog[5] vccd1 sky130_fd_pr__res_generic_m5 w=7.42e+07u l=1.77e+07u +R3 vdda2 vdda1 sky130_fd_pr__res_generic_m5 w=7.4e+07u l=1.005e+07u +R4 vssa2 vssa1 sky130_fd_pr__res_generic_m4 w=7.4e+07u l=1.68e+07u +R5 io_analog[4] io_analog[2] sky130_fd_pr__res_generic_m3 w=2.505e+07u l=4.15e+06u +R6 vssa2 vssd1 sky130_fd_pr__res_generic_m4 w=7.815e+07u l=1.755e+07u +R7 io_analog[6] io_analog[8] sky130_fd_pr__res_generic_m3 w=2.505e+07u l=6.55e+06u +R8 io_analog[6] io_analog[7] sky130_fd_pr__res_generic_m3 w=2.505e+07u l=7.55e+06u +R9 io_analog[4] io_analog[3] sky130_fd_pr__res_generic_m3 w=2.505e+07u l=3.7e+06u .ends
diff --git a/xschem/src/Class_D/Class_D.sch b/xschem/src/Class_D/Class_D.sch new file mode 100644 index 0000000..89cb1c9 --- /dev/null +++ b/xschem/src/Class_D/Class_D.sch
@@ -0,0 +1,274 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 270 -390 320 -390 { lab=vin_p} +N 930 -430 930 -400 { lab=avdd} +N 930 -360 930 -330 { lab=vss} +N 270 -10 320 -10 { lab=vin_n} +N 920 -30 920 0 { lab=avdd} +N 920 40 920 70 { lab=vss} +N 250 -390 270 -390 { lab=vin_p} +N 970 20 980 20 { lab=vcmp_n} +N 1130 -440 1130 -420 { lab=dvdd} +N 1130 -340 1130 -320 { lab=vss} +N 1130 -40 1130 -20 { lab=dvdd} +N 1130 60 1130 80 { lab=vss} +N 980 20 1000 20 { lab=vcmp_n} +N 590 -240 800 -240 { lab=vtriang} +N -60 -170 -30 -170 { lab=vref} +N -60 -190 -30 -190 { lab=vin} +N 90 -260 90 -240 { lab=avdd} +N 90 -160 90 -140 { lab=vss} +N 320 -410 320 -390 { lab=vin_p} +N 380 -410 400 -410 { lab=feedback_p} +N 380 -10 400 -10 { lab=feedback_n} +N 980 -380 1000 -380 { lab=vcmp_p} +N 650 -340 650 -330 { lab=vss} +N 430 -230 460 -230 { lab=vbias4} +N 430 -210 460 -210 { lab=vref} +N 590 -210 640 -210 { lab=vsquare} +N 430 -230 460 -230 { lab=vbias4} +N -70 -190 -60 -190 { lab=vin} +N -60 -210 -30 -210 { lab=vbias6} +N -60 -230 -30 -230 { lab=vbias3} +N 520 -300 520 -280 { lab=avdd} +N 520 -280 520 -270 { lab=avdd} +N 250 -10 270 -10 { lab=vin_n} +N 210 -390 210 -210 { lab=vin_p} +N 210 -390 250 -390 { lab=vin_p} +N 210 -190 210 -10 { lab=vin_n} +N 210 -10 250 -10 { lab=vin_n} +N 1260 10 1290 10 { lab=vn_p} +N 1290 -160 1290 10 { lab=vn_p} +N 1290 -160 1320 -160 { lab=vn_p} +N 1250 30 1320 30 { lab=vn_n} +N 1320 -140 1320 30 { lab=vn_n} +N 1250 -390 1310 -390 { lab=vp_p} +N 1310 -390 1320 -390 { lab=vp_p} +N 1320 -390 1320 -200 { lab=vp_p} +N 1250 -370 1280 -370 { lab=vp_n} +N 1280 -370 1280 -180 { lab=vp_n} +N 1280 -180 1320 -180 { lab=vp_n} +N 1620 30 1740 30 { lab=out_n} +N 1620 -380 1750 -380 { lab=out_p} +N 1470 -130 1470 -80 { lab=vss} +N 1250 10 1260 10 { lab=vn_p} +N 400 -10 410 -10 { lab=feedback_n} +N 650 -490 650 -440 { lab=avdd} +N 650 -380 650 -340 { lab=vss} +N 480 -390 500 -390 { lab=vref} +N 400 -430 450 -430 { lab=feedback_p} +N 450 -430 500 -430 { lab=feedback_p} +N 480 -410 500 -410 { lab=vbias2} +N 800 -410 820 -410 { lab=error_p} +N 820 -410 820 -400 { lab=error_p} +N 820 -400 870 -400 { lab=error_p} +N 800 -380 870 -380 { lab=vtriang} +N 800 -380 800 -240 { lab=vtriang} +N 820 -360 870 -360 { lab=vbias1} +N 520 -190 520 -150 { lab=vss} +N 650 -60 650 -20 { lab=avdd} +N 650 40 650 60 { lab=vss} +N 410 -10 500 -10 { lab=feedback_n} +N 460 10 500 10 { lab=vbias7} +N 460 30 500 30 { lab=vref} +N 830 40 860 40 { lab=vbias8} +N 800 0 800 10 { lab=error_n} +N 800 0 860 0 { lab=error_n} +N 800 -240 800 -30 { lab=vtriang} +N 800 -30 840 -30 { lab=vtriang} +N 840 -30 840 20 { lab=vtriang} +N 840 20 860 20 { lab=vtriang} +N 1620 -160 1620 30 { lab=out_n} +N 350 -390 350 -360 { lab=vss} +N 350 -70 350 -30 { lab=vss} +N 1620 -380 1620 -180 { lab=out_p} +N 650 60 650 90 { lab=vss} +N 800 -220 850 -220 { lab=vtriang} +N -0 300 -0 350 { lab=vss} +N 0 60 -0 100 { lab=iin_15u} +N 100 130 140 130 { lab=vbias1} +N 100 150 140 150 { lab=vbias2} +N 100 170 140 170 { lab=vbias3} +N 100 190 140 190 { lab=vbias4} +N 100 210 140 210 { lab=vbias5} +N 100 230 140 230 { lab=vbias6} +N 100 250 140 250 { lab=vbias7} +N 100 270 140 270 { lab=vbias8} +N 430 -250 460 -250 { lab=vbias5} +N -360 -180 -260 -180 { lab=avdd} +N -360 -110 -270 -110 { lab=vss} +N -360 -30 -270 -30 { lab=dvdd} +N -360 40 -260 40 { lab=vss} +N -370 160 -310 160 { lab=iin_15u} +N -150 -190 -70 -190 { lab=vin} +N 210 -300 250 -300 { lab=vin_p} +N 210 -120 250 -120 { lab=vin_n} +N 990 -380 990 -290 { lab=vcmp_p} +N 990 -290 1000 -290 { lab=vcmp_p} +N 990 -90 1000 -90 { lab=vcmp_n} +N 990 -90 990 20 { lab=vcmp_n} +N 1320 -390 1380 -390 { lab=vp_p} +N 1280 -330 1380 -330 { lab=vp_n} +N 1320 30 1380 30 { lab=vn_n} +N 1290 -50 1380 -50 { lab=vn_p} +N -360 90 -280 90 { lab=vref} +N -270 -30 -210 -30 { lab=dvdd} +N -260 40 -210 40 { lab=vss} +N -210 30 -210 40 { lab=vss} +N 1450 -240 1450 -220 { lab=dvdd} +N 1450 -240 1480 -240 { lab=dvdd} +N 1480 -240 1480 -220 { lab=dvdd} +N -210 -30 -110 -30 { lab=dvdd} +N -110 30 -110 40 { lab=vss} +N -210 40 -110 40 { lab=vss} +N -260 -180 -230 -180 { lab=avdd} +N -270 -110 -230 -110 { lab=vss} +N -230 -120 -230 -110 { lab=vss} +N -230 -180 -190 -180 { lab=avdd} +N -230 -110 -190 -110 { lab=vss} +N -190 -120 -190 -110 { lab=vss} +N -440 40 -360 40 { lab=vss} +N -440 -110 -440 40 { lab=vss} +N -440 -110 -360 -110 { lab=vss} +N 400 -540 710 -540 { lab=feedback_p} +N 770 -540 1660 -540 { lab=out_p} +N 1660 -540 1660 -380 { lab=out_p} +N 740 -520 740 -480 { lab=vss} +N 410 150 700 150 { lab=feedback_n} +N 760 150 1640 150 { lab=out_n} +N 1640 30 1640 150 { lab=out_n} +N 730 170 730 210 { lab=vss} +N 400 -540 400 -430 { lab=feedback_p} +N 400 -430 400 -410 { lab=feedback_p} +N 410 -10 410 150 { lab=feedback_n} +N -310 160 -280 160 { lab=iin_15u} +N -280 160 -280 180 { lab=iin_15u} +N -280 240 -280 280 { lab=vss} +C {lab_wire.sym} 720 -240 0 0 {name=l9 sig_type=std_logic lab=vtriang} +C {lab_wire.sym} 270 -390 0 1 {name=l1 sig_type=std_logic lab=vin_p} +C {lab_wire.sym} 400 -480 0 0 {name=l18 sig_type=std_logic lab=feedback_p} +C {lab_wire.sym} 990 -380 0 0 {name=l19 sig_type=std_logic lab=vcmp_p} +C {lab_wire.sym} 850 -400 0 0 {name=l8 sig_type=std_logic lab=error_p} +C {lab_wire.sym} 480 30 0 0 {name=l27 sig_type=std_logic lab=vref} +C {lab_wire.sym} 810 0 0 0 {name=l29 sig_type=std_logic lab=error_n} +C {lab_wire.sym} 410 70 0 0 {name=l30 sig_type=std_logic lab=feedback_n} +C {lab_wire.sym} 980 20 0 1 {name=l40 sig_type=std_logic lab=vcmp_n} +C {lab_wire.sym} 1280 10 0 0 {name=l51 sig_type=std_logic lab=vn_p} +C {lab_wire.sym} 1290 30 0 0 {name=l52 sig_type=std_logic lab=vn_n} +C {lab_wire.sym} 440 -210 0 0 {name=l46 sig_type=std_logic lab=vref} +C {lab_wire.sym} 600 -210 0 1 {name=l60 sig_type=std_logic lab=vsquare} +C {lab_wire.sym} 260 -10 0 1 {name=l23 sig_type=std_logic lab=vin_n} +C {lab_wire.sym} 1300 -390 0 1 {name=l15 sig_type=std_logic lab=vp_p} +C {lab_wire.sym} 1280 -340 0 1 {name=l25 sig_type=std_logic lab=vp_n} +C {lab_wire.sym} 1670 -380 0 1 {name=l33 sig_type=std_logic lab=out_p} +C {lab_wire.sym} 1680 30 0 1 {name=l37 sig_type=std_logic lab=out_n} +C {lab_wire.sym} 490 -390 0 0 {name=l7 sig_type=std_logic lab=vref} +C {src/S_to_D/S_to_D.sym} 120 -200 0 0 {name=x1} +C {src/triangle/triangle.sym} 520 -230 0 0 {name=x2} +C {src/integrator/integrator.sym} 650 -410 0 0 {name=x3} +C {src/integrator/integrator.sym} 650 10 0 0 {name=x4} +C {src/comparator/comparator.sym} 960 -340 0 0 {name=x5} +C {src/comparator/comparator.sym} 950 60 0 0 {name=x6} +C {src/dead_time/dead_time.sym} 1100 -380 0 0 {name=x7} +C {src/dead_time/dead_time.sym} 1100 20 0 0 {name=x8} +C {src/biasing_network/biasing_network.sym} -50 200 0 0 {name=x10} +C {sky130_fd_pr/res_xhigh_po.sym} 350 -410 3 0 {name=R1 +W=0.35 +L=35 +model=res_xhigh_po +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_xhigh_po.sym} 350 -10 1 0 {name=R2 +W=0.35 +L=35 +model=res_xhigh_po +spiceprefix=X +mult=1} +C {ipin.sym} -150 -190 0 0 {name=p1 lab=vin} +C {iopin.sym} -370 -180 0 0 {name=p2 lab=avdd} +C {opin.sym} 1740 30 0 0 {name=p3 lab=out_n} +C {lab_wire.sym} 90 -250 0 0 {name=l3 sig_type=std_logic lab=avdd} +C {lab_wire.sym} -40 -170 0 0 {name=l6 sig_type=std_logic lab=vref} +C {lab_wire.sym} 650 -470 0 0 {name=l11 sig_type=std_logic lab=avdd} +C {lab_wire.sym} 650 -40 0 0 {name=l12 sig_type=std_logic lab=avdd} +C {lab_wire.sym} 930 -420 0 0 {name=l13 sig_type=std_logic lab=avdd} +C {lab_wire.sym} 920 -20 0 0 {name=l14 sig_type=std_logic lab=avdd} +C {lab_wire.sym} 1130 -430 0 0 {name=l20 sig_type=std_logic lab=dvdd} +C {src/output_driver/output_driver.sym} 1470 -170 0 0 {name=x9} +C {lab_wire.sym} 350 -360 0 0 {name=l32 sig_type=std_logic lab=vss} +C {lab_wire.sym} 350 -60 0 0 {name=l34 sig_type=std_logic lab=vss} +C {iopin.sym} -370 -110 0 0 {name=p4 lab=vss} +C {iopin.sym} -380 160 0 0 {name=p5 lab=iin_15u} +C {opin.sym} 1750 -380 0 0 {name=p7 lab=out_p} +C {opin.sym} 840 -220 0 0 {name=p10 lab=vtriang} +C {iopin.sym} -370 -30 0 0 {name=p11 lab=dvdd} +C {lab_wire.sym} 130 130 0 1 {name=l35 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 130 150 0 1 {name=l38 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 130 170 0 1 {name=l39 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 130 190 0 1 {name=l41 sig_type=std_logic lab=vbias4} +C {lab_wire.sym} 130 210 0 1 {name=l42 sig_type=std_logic lab=vbias5} +C {lab_wire.sym} 130 230 0 1 {name=l43 sig_type=std_logic lab=vbias6} +C {lab_wire.sym} 130 250 0 1 {name=l44 sig_type=std_logic lab=vbias7} +C {lab_wire.sym} 130 270 0 1 {name=l45 sig_type=std_logic lab=vbias8} +C {lab_wire.sym} 830 -360 0 1 {name=l47 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 480 -410 0 1 {name=l48 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} -60 -230 0 1 {name=l49 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 430 -230 0 1 {name=l50 sig_type=std_logic lab=vbias4} +C {lab_wire.sym} 430 -250 0 1 {name=l53 sig_type=std_logic lab=vbias5} +C {lab_wire.sym} -60 -210 0 1 {name=l54 sig_type=std_logic lab=vbias6} +C {lab_wire.sym} 460 10 0 1 {name=l55 sig_type=std_logic lab=vbias7} +C {lab_wire.sym} 830 40 0 1 {name=l56 sig_type=std_logic lab=vbias8} +C {lab_wire.sym} -270 -180 0 0 {name=l57 sig_type=std_logic lab=avdd} +C {lab_wire.sym} -280 -30 0 0 {name=l59 sig_type=std_logic lab=dvdd} +C {lab_wire.sym} -270 40 0 0 {name=l62 sig_type=std_logic lab=vss} +C {opin.sym} 250 -300 0 0 {name=p13 lab=vin_p} +C {opin.sym} 250 -120 0 0 {name=p14 lab=vin_n} +C {opin.sym} 1000 -290 0 0 {name=p15 lab=vcmp_p} +C {opin.sym} 1000 -90 0 0 {name=p16 lab=vcmp_n} +C {opin.sym} 1380 -390 0 0 {name=p17 lab=vp_p} +C {opin.sym} 1380 -330 0 0 {name=p18 lab=vp_n} +C {opin.sym} 1380 -50 0 0 {name=p19 lab=vn_p} +C {opin.sym} 1380 30 0 0 {name=p20 lab=vn_n} +C {ipin.sym} -360 90 0 0 {name=p21 lab=vref} +C {lab_wire.sym} -310 90 0 0 {name=l65 sig_type=std_logic lab=vref} +C {lab_wire.sym} 520 -290 0 0 {name=l66 sig_type=std_logic lab=avdd} +C {lab_wire.sym} 1130 -40 0 0 {name=l28 sig_type=std_logic lab=dvdd} +C {sky130_fd_pr/cap_mim_m3_2.sym} -210 0 2 0 {name=C1 model=cap_mim_m3_2 W=16 L=16 MF=90 spiceprefix=X} +C {lab_wire.sym} 1460 -240 0 0 {name=l22 sig_type=std_logic lab=dvdd} +C {sky130_fd_pr/cap_mim_m3_2.sym} -110 0 0 0 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=262 spiceprefix=X} +C {sky130_fd_pr/cap_mim_m3_2.sym} -230 -150 0 0 {name=C3 model=cap_mim_m3_2 W=30 L=30 MF=132 spiceprefix=X} +C {sky130_fd_pr/cap_mim_m3_2.sym} -190 -150 0 0 {name=C4 model=cap_mim_m3_2 W=30 L=30 MF=132 spiceprefix=X} +C {lab_wire.sym} 90 -140 0 0 {name=l2 sig_type=std_logic lab=vss} +C {lab_wire.sym} 0 340 0 0 {name=l31 sig_type=std_logic lab=vss} +C {lab_wire.sym} 520 -150 0 0 {name=l4 sig_type=std_logic lab=vss} +C {lab_wire.sym} 650 80 0 0 {name=l10 sig_type=std_logic lab=vss} +C {lab_wire.sym} 650 -340 0 0 {name=l5 sig_type=std_logic lab=vss} +C {lab_wire.sym} 930 -330 0 0 {name=l16 sig_type=std_logic lab=vss} +C {lab_wire.sym} 920 70 0 0 {name=l17 sig_type=std_logic lab=vss} +C {lab_wire.sym} 1130 80 0 0 {name=l21 sig_type=std_logic lab=vss} +C {lab_wire.sym} 1130 -320 0 0 {name=l26 sig_type=std_logic lab=vss} +C {lab_wire.sym} 1470 -90 0 0 {name=l24 sig_type=std_logic lab=vss} +C {sky130_fd_pr/res_xhigh_po.sym} 740 -540 3 0 {name=R3 +W=0.35 +L=35 +model=res_xhigh_po +spiceprefix=X +mult=1} +C {lab_wire.sym} 650 -340 0 0 {name=l36 sig_type=std_logic lab=vss} +C {lab_wire.sym} 740 -490 0 0 {name=l58 sig_type=std_logic lab=vss} +C {sky130_fd_pr/res_xhigh_po.sym} 730 150 3 0 {name=R4 +W=0.35 +L=35 +model=res_xhigh_po +spiceprefix=X +mult=1} +C {lab_wire.sym} 650 80 0 0 {name=l61 sig_type=std_logic lab=vss} +C {lab_wire.sym} 730 210 0 0 {name=l67 sig_type=std_logic lab=vss} +C {lab_wire.sym} 0 80 0 0 {name=l63 sig_type=std_logic lab=iin_15u} +C {lab_wire.sym} -340 160 0 1 {name=l64 sig_type=std_logic lab=iin_15u} +C {sky130_fd_pr/cap_mim_m3_2.sym} -280 210 0 0 {name=C5 model=cap_mim_m3_2 W=30 L=30 MF=210 spiceprefix=X} +C {lab_wire.sym} -280 280 0 0 {name=l68 sig_type=std_logic lab=vss}
diff --git a/xschem/src/Class_D/Class_D.sym b/xschem/src/Class_D/Class_D.sym new file mode 100644 index 0000000..b1a54fb --- /dev/null +++ b/xschem/src/Class_D/Class_D.sym
@@ -0,0 +1,66 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -150 130 -150 {} +L 4 -130 150 130 150 {} +L 4 -130 -150 -130 150 {} +L 4 130 -150 130 150 {} +L 4 130 -140 150 -140 {} +L 4 130 -120 150 -120 {} +L 4 130 -100 150 -100 {} +L 4 130 -80 150 -80 {} +L 4 130 -60 150 -60 {} +L 4 130 -40 150 -40 {} +L 4 -150 -140 -130 -140 {} +L 4 130 0 150 0 {} +L 4 130 40 150 40 {} +L 4 130 80 150 80 {} +L 4 130 120 150 120 {} +L 4 130 140 150 140 {} +L 4 -150 -120 -130 -120 {} +L 7 130 -20 150 -20 {} +L 7 130 20 150 20 {} +L 7 130 60 150 60 {} +L 7 130 100 150 100 {} +B 5 147.5 -142.5 152.5 -137.5 {name=vp_p dir=out } +B 5 147.5 -122.5 152.5 -117.5 {name=out_p dir=out } +B 5 147.5 -102.5 152.5 -97.5 {name=vp_n dir=out } +B 5 147.5 -82.5 152.5 -77.5 {name=vin_p dir=out } +B 5 147.5 -62.5 152.5 -57.5 {name=vcmp_p dir=out } +B 5 147.5 -42.5 152.5 -37.5 {name=vtriang dir=out } +B 5 -152.5 -142.5 -147.5 -137.5 {name=vin dir=in } +B 5 147.5 -22.5 152.5 -17.5 {name=avdd dir=inout } +B 5 147.5 -2.5 152.5 2.5 {name=vin_n dir=out } +B 5 147.5 17.5 152.5 22.5 {name=vss dir=inout } +B 5 147.5 37.5 152.5 42.5 {name=vcmp_n dir=out } +B 5 147.5 57.5 152.5 62.5 {name=iin_15u dir=inout } +B 5 147.5 77.5 152.5 82.5 {name=vn_p dir=out } +B 5 147.5 97.5 152.5 102.5 {name=dvdd dir=inout } +B 5 147.5 117.5 152.5 122.5 {name=vn_n dir=out } +B 5 147.5 137.5 152.5 142.5 {name=out_n dir=out } +B 5 -152.5 -122.5 -147.5 -117.5 {name=vref dir=in } +T {@symname} -49.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -162 0 0 0.2 0.2 {} +T {vp_p} 125 -144 0 1 0.2 0.2 {} +T {out_p} 125 -124 0 1 0.2 0.2 {} +T {vp_n} 125 -104 0 1 0.2 0.2 {} +T {vin_p} 125 -84 0 1 0.2 0.2 {} +T {vcmp_p} 125 -64 0 1 0.2 0.2 {} +T {vtriang} 125 -44 0 1 0.2 0.2 {} +T {vin} -125 -144 0 0 0.2 0.2 {} +T {avdd} 125 -24 0 1 0.2 0.2 {} +T {vin_n} 125 -4 0 1 0.2 0.2 {} +T {vss} 125 16 0 1 0.2 0.2 {} +T {vcmp_n} 125 36 0 1 0.2 0.2 {} +T {iin_15u} 125 56 0 1 0.2 0.2 {} +T {vn_p} 125 76 0 1 0.2 0.2 {} +T {dvdd} 125 96 0 1 0.2 0.2 {} +T {vn_n} 125 116 0 1 0.2 0.2 {} +T {out_n} 125 136 0 1 0.2 0.2 {} +T {vref} -125 -124 0 0 0.2 0.2 {}
diff --git a/xschem/src/Class_D/Class_D_bondwire.sch b/xschem/src/Class_D/Class_D_bondwire.sch new file mode 100644 index 0000000..e96bc0e --- /dev/null +++ b/xschem/src/Class_D/Class_D_bondwire.sch
@@ -0,0 +1,330 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 1050 -530 1060 -530 { lab=#net1} +N 970 -530 990 -530 { lab=out_p_f} +N 1120 -530 1140 -530 { lab=out_p} +N 970 -470 970 -450 { lab=vss} +N 1140 -470 1140 -450 { lab=vss} +N 360 -450 500 -450 { lab=out_p_f} +N 500 -530 500 -450 { lab=out_p_f} +N 500 -530 670 -530 { lab=out_p_f} +N 1050 -400 1060 -400 { lab=#net2} +N 970 -400 990 -400 { lab=avdd_f} +N 1120 -400 1140 -400 { lab=avdd} +N 970 -340 970 -320 { lab=vss} +N 1140 -340 1140 -320 { lab=vss} +N 360 -350 490 -350 { lab=avdd_f} +N 490 -400 490 -350 { lab=avdd_f} +N 1050 -160 1060 -160 { lab=#net3} +N 970 -160 990 -160 { lab=iin_15u_f} +N 1120 -160 1140 -160 { lab=iin_15u} +N 970 -100 970 -80 { lab=vss} +N 1140 -100 1140 -80 { lab=vss} +N 1050 -40 1060 -40 { lab=#net4} +N 970 -40 990 -40 { lab=dvdd_f} +N 1120 -40 1140 -40 { lab=dvdd} +N 970 20 970 40 { lab=vss} +N 1140 20 1140 40 { lab=vss} +N 1050 70 1060 70 { lab=#net5} +N 970 70 990 70 { lab=out_n_f} +N 1120 70 1140 70 { lab=out_n} +N 970 130 970 150 { lab=vss} +N 1140 130 1140 150 { lab=vss} +N 360 -190 470 -190 { lab=out_n_f} +N 470 -190 470 -50 { lab=out_n_f} +N -440 -470 -430 -470 { lab=#net6} +N -370 -470 -350 -470 { lab=vin_f} +N -520 -470 -500 -470 { lab=vin} +N -350 -410 -350 -390 { lab=vss} +N -520 -410 -520 -390 { lab=vss} +N -90 -470 60 -470 { lab=vin_f} +N -440 -320 -430 -320 { lab=#net7} +N -370 -320 -350 -320 { lab=#net8} +N -520 -320 -500 -320 { lab=vref} +N -350 -260 -350 -240 { lab=vss} +N -520 -260 -520 -240 { lab=vss} +N -90 -320 50 -320 { lab=#net8} +N 50 -450 50 -320 { lab=#net8} +N 50 -450 60 -450 { lab=#net8} +N 470 -50 470 -40 { lab=out_n_f} +N 470 -40 470 70 { lab=out_n_f} +N 470 70 670 70 { lab=out_n_f} +N 360 -230 540 -230 { lab=dvdd_f} +N 540 -230 540 -160 { lab=dvdd_f} +N 540 -160 540 -40 { lab=dvdd_f} +N 540 -40 670 -40 { lab=dvdd_f} +N 360 -270 570 -270 { lab=iin_15u_f} +N 570 -270 570 -160 { lab=iin_15u_f} +N 570 -160 670 -160 { lab=iin_15u_f} +N 1050 -280 1060 -280 { lab=#net9} +N 970 -280 990 -280 { lab=fgnd} +N 1120 -280 1140 -280 { lab=vss} +N 970 -220 970 -200 { lab=vss} +N 1140 -220 1140 -200 { lab=vss} +N 360 -310 630 -310 { lab=fgnd} +N 630 -310 630 -280 { lab=fgnd} +N 360 -470 410 -470 { lab=vp_p} +N 360 -430 410 -430 { lab=vp_n} +N 360 -410 410 -410 { lab=vin_p} +N 360 -390 410 -390 { lab=vcmp_p} +N 360 -370 410 -370 { lab=vtriang} +N 360 -330 410 -330 { lab=vin_n} +N 360 -290 410 -290 { lab=vcmp_n} +N 360 -250 410 -250 { lab=vn_p} +N 360 -210 410 -210 { lab=vn_n} +N -600 -470 -520 -470 { lab=vin} +N -600 -320 -520 -320 { lab=vref} +N 1140 -530 1260 -530 { lab=out_p} +N 1140 70 1250 70 { lab=out_n} +N 1140 -160 1260 -160 { lab=iin_15u} +N 1140 -40 1260 -40 { lab=dvdd} +N 1140 -280 1260 -280 { lab=vss} +N 1140 -400 1260 -400 { lab=avdd} +N 1250 70 1260 70 { lab=out_n} +N -350 -470 -90 -470 { lab=vin_f} +N -350 -320 -90 -320 { lab=#net8} +N 670 -530 970 -530 { lab=out_p_f} +N 670 -160 970 -160 { lab=iin_15u_f} +N 670 70 970 70 { lab=out_n_f} +N 660 -280 980 -280 { lab=fgnd} +N 640 -280 660 -280 { lab=fgnd} +N 630 -280 640 -280 { lab=fgnd} +N 490 -400 970 -400 { lab=avdd_f} +N 610 -380 650 -380 { lab=fgnd} +N 670 -40 970 -40 { lab=dvdd_f} +N 600 -20 670 -20 { lab=fgnd} +N 770 -210 770 -190 { lab=avdd_f} +N 770 20 770 40 { lab=dvdd_f} +N 770 -600 770 -560 { lab=dvdd_f} +N 770 -130 770 -110 { lab=fgnd} +N 770 100 770 120 { lab=fgnd} +N 770 -500 770 -480 { lab=fgnd} +N -190 -520 -190 -500 { lab=avdd_f} +N -190 -370 -190 -350 { lab=avdd_f} +N -190 -440 -190 -420 { lab=fgnd} +N -190 -290 -190 -270 { lab=fgnd} +C {src/Class_D/Class_D.sym} 210 -330 0 0 {name=x1} +C {res.sym} 1020 -530 1 0 {name=R1 +value=0.2m +footprint=1206 +device=resistor +m=1} +C {ind.sym} 1090 -530 1 0 {name=L1 +m=1 +value=0.011n +footprint=1206 +device=inductor} +C {capa.sym} 1140 -500 0 0 {name=C1 +m=1 +value=0.06p +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 970 -500 0 0 {name=C2 +m=1 +value=0.06p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} 970 -450 0 0 {name=l1 sig_type=std_logic lab=vss} +C {lab_wire.sym} 1140 -450 0 0 {name=l2 sig_type=std_logic lab=vss} +C {res.sym} 1020 -400 1 0 {name=R2 +value=0.3m +footprint=1206 +device=resistor +m=1} +C {ind.sym} 1090 -400 1 0 {name=L2 +m=1 +value=0.016n +footprint=1206 +device=inductor} +C {capa.sym} 1140 -370 0 0 {name=C3 +m=1 +value=0.04p +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 970 -370 0 0 {name=C4 +m=1 +value=0.04p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} 970 -320 0 0 {name=l3 sig_type=std_logic lab=vss} +C {lab_wire.sym} 1140 -320 0 0 {name=l4 sig_type=std_logic lab=vss} +C {res.sym} 1020 -160 1 0 {name=R3 +value=0.6m +footprint=1206 +device=resistor +m=1} +C {ind.sym} 1090 -160 1 0 {name=L3 +m=1 +value=0.032n +footprint=1206 +device=inductor} +C {capa.sym} 1140 -130 0 0 {name=C5 +m=1 +value=0.02p +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 970 -130 0 0 {name=C6 +m=1 +value=0.02p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} 970 -80 0 0 {name=l5 sig_type=std_logic lab=vss} +C {lab_wire.sym} 1140 -80 0 0 {name=l6 sig_type=std_logic lab=vss} +C {res.sym} 1020 -40 1 0 {name=R4 +value=0.2m +footprint=1206 +device=resistor +m=1} +C {ind.sym} 1090 -40 1 0 {name=L4 +m=1 +value=0.011n +footprint=1206 +device=inductor} +C {capa.sym} 1140 -10 0 0 {name=C7 +m=1 +value=0.06p +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 970 -10 0 0 {name=C8 +m=1 +value=0.06p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} 970 40 0 0 {name=l7 sig_type=std_logic lab=vss} +C {lab_wire.sym} 1140 40 0 0 {name=l8 sig_type=std_logic lab=vss} +C {res.sym} 1020 70 1 0 {name=R5 +value=0.2m +footprint=1206 +device=resistor +m=1} +C {ind.sym} 1090 70 1 0 {name=L5 +m=1 +value=0.011n +footprint=1206 +device=inductor} +C {capa.sym} 1140 100 0 0 {name=C9 +m=1 +value=0.06p +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 970 100 0 0 {name=C10 +m=1 +value=0.06p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} 970 150 0 0 {name=l9 sig_type=std_logic lab=vss} +C {lab_wire.sym} 1140 150 0 0 {name=l10 sig_type=std_logic lab=vss} +C {res.sym} -400 -470 3 1 {name=R6 +value=0.6m +footprint=1206 +device=resistor +m=1} +C {ind.sym} -470 -470 3 1 {name=L6 +m=1 +value=0.032n +footprint=1206 +device=inductor} +C {capa.sym} -520 -440 0 1 {name=C11 +m=1 +value=0.02p +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} -350 -440 0 1 {name=C12 +m=1 +value=0.02p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} -350 -390 0 1 {name=l11 sig_type=std_logic lab=vss} +C {lab_wire.sym} -520 -390 0 1 {name=l12 sig_type=std_logic lab=vss} +C {res.sym} -400 -320 3 1 {name=R7 +value=0.6m +footprint=1206 +device=resistor +m=1} +C {ind.sym} -470 -320 3 1 {name=L7 +m=1 +value=0.032n +footprint=1206 +device=inductor} +C {capa.sym} -520 -290 0 1 {name=C13 +m=1 +value=0.02p +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} -350 -290 0 1 {name=C14 +m=1 +value=0.02p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} -350 -240 0 1 {name=l13 sig_type=std_logic lab=vss} +C {lab_wire.sym} -520 -240 0 1 {name=l14 sig_type=std_logic lab=vss} +C {res.sym} 1020 -280 1 0 {name=R8 +value=0.15m +footprint=1206 +device=resistor +m=1} +C {ind.sym} 1090 -280 1 0 {name=L8 +m=1 +value=0.008n +footprint=1206 +device=inductor} +C {capa.sym} 1140 -250 0 0 {name=C15 +m=1 +value=0.08p +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 970 -250 0 0 {name=C16 +m=1 +value=0.08p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} 970 -200 0 0 {name=l15 sig_type=std_logic lab=vss} +C {lab_wire.sym} 1140 -200 0 0 {name=l16 sig_type=std_logic lab=vss} +C {lab_wire.sym} 430 -270 0 0 {name=l17 sig_type=std_logic lab=iin_15u_f} +C {lab_wire.sym} 400 -310 0 0 {name=l18 sig_type=std_logic lab=fgnd} +C {lab_wire.sym} 400 -470 0 0 {name=l19 sig_type=std_logic lab=vp_p} +C {lab_wire.sym} 420 -450 0 0 {name=l20 sig_type=std_logic lab=out_p_f} +C {lab_wire.sym} 420 -190 0 0 {name=l21 sig_type=std_logic lab=out_n_f} +C {lab_wire.sym} 400 -430 0 0 {name=l22 sig_type=std_logic lab=vp_n} +C {lab_wire.sym} 400 -250 0 0 {name=l23 sig_type=std_logic lab=vn_p} +C {lab_wire.sym} 400 -210 0 0 {name=l24 sig_type=std_logic lab=vn_n} +C {lab_wire.sym} 400 -410 0 0 {name=l25 sig_type=std_logic lab=vin_p} +C {lab_wire.sym} 400 -330 0 0 {name=l26 sig_type=std_logic lab=vin_n} +C {lab_wire.sym} 400 -370 0 0 {name=l27 sig_type=std_logic lab=vtriang} +C {lab_wire.sym} 410 -390 0 0 {name=l28 sig_type=std_logic lab=vcmp_p} +C {lab_wire.sym} 410 -290 0 0 {name=l29 sig_type=std_logic lab=vcmp_n} +C {lab_wire.sym} 420 -350 0 0 {name=l30 sig_type=std_logic lab=avdd_f} +C {lab_wire.sym} 420 -230 0 0 {name=l31 sig_type=std_logic lab=dvdd_f} +C {lab_wire.sym} 20 -470 0 0 {name=l32 sig_type=std_logic lab=vin_f} +C {lab_wire.sym} 20 -470 0 0 {name=l33 sig_type=std_logic lab=vin_f} +C {opin.sym} 1260 -530 0 0 {name=p1 lab=out_p} +C {opin.sym} 1260 70 0 0 {name=p2 lab=out_n} +C {ipin.sym} -600 -470 0 0 {name=p3 lab=vin} +C {ipin.sym} -600 -320 0 0 {name=p4 lab=vref} +C {iopin.sym} 1260 -400 0 0 {name=p5 lab=avdd} +C {iopin.sym} 1260 -280 0 0 {name=p6 lab=vss} +C {iopin.sym} 1260 -160 0 0 {name=p7 lab=iin_15u} +C {iopin.sym} 1260 -40 0 0 {name=p8 lab=dvdd} +C {src/ESD/ESD.sym} 720 -530 0 1 {name=x2} +C {src/ESD/ESD.sym} 720 -160 0 1 {name=x3} +C {src/ESD/ESD.sym} 720 70 0 1 {name=x4} +C {src/ESD/ESD.sym} -140 -470 0 0 {name=x5} +C {src/ESD/ESD.sym} -140 -320 0 0 {name=x6} +C {src/ESD/io_clamp.sym} 800 -390 0 1 {name=x7} +C {lab_wire.sym} 630 -380 0 0 {name=l34 sig_type=std_logic lab=fgnd} +C {src/ESD/io_clamp.sym} 820 -30 0 1 {name=x8} +C {lab_wire.sym} 640 -20 0 0 {name=l35 sig_type=std_logic lab=fgnd} +C {lab_wire.sym} 770 -200 0 0 {name=l36 sig_type=std_logic lab=avdd_f} +C {lab_wire.sym} 770 30 0 0 {name=l37 sig_type=std_logic lab=dvdd_f} +C {lab_wire.sym} 770 -580 0 0 {name=l38 sig_type=std_logic lab=dvdd_f} +C {lab_wire.sym} 770 -110 0 0 {name=l39 sig_type=std_logic lab=fgnd} +C {lab_wire.sym} 770 120 0 0 {name=l40 sig_type=std_logic lab=fgnd} +C {lab_wire.sym} 770 -480 0 0 {name=l41 sig_type=std_logic lab=fgnd} +C {lab_wire.sym} -190 -510 0 0 {name=l42 sig_type=std_logic lab=avdd_f} +C {lab_wire.sym} -190 -360 0 0 {name=l43 sig_type=std_logic lab=avdd_f} +C {lab_wire.sym} -190 -420 0 0 {name=l44 sig_type=std_logic lab=fgnd} +C {lab_wire.sym} -190 -270 0 0 {name=l45 sig_type=std_logic lab=fgnd}
diff --git a/xschem/src/Class_D/Class_D_bondwire.sym b/xschem/src/Class_D/Class_D_bondwire.sym new file mode 100644 index 0000000..aecdd09 --- /dev/null +++ b/xschem/src/Class_D/Class_D_bondwire.sym
@@ -0,0 +1,35 @@ +v {xschem version=2.9.9 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +T {@symname} -90 -6 0 0 0.3 0.3 {} +T {@name} 135 -72 0 0 0.2 0.2 {} +L 4 -130 -60 130 -60 {} +L 4 -130 60 130 60 {} +L 4 -130 -60 -130 60 {} +L 4 130 -60 130 60 {} +B 5 147.5 -52.5 152.5 -47.5 {name=out_p dir=out } +L 4 130 -50 150 -50 {} +T {out_p} 125 -54 0 1 0.2 0.2 {} +B 5 -152.5 -52.5 -147.5 -47.5 {name=vin dir=in } +L 4 -150 -50 -130 -50 {} +T {vin} -125 -54 0 0 0.2 0.2 {} +B 5 147.5 -32.5 152.5 -27.5 {name=avdd dir=inout } +L 7 130 -30 150 -30 {} +T {avdd} 125 -34 0 1 0.2 0.2 {} +B 5 -152.5 -32.5 -147.5 -27.5 {name=vref dir=in } +L 4 -150 -30 -130 -30 {} +T {vref} -125 -34 0 0 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=vss dir=inout } +L 7 130 -10 150 -10 {} +T {vss} 125 -14 0 1 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=iin_15u dir=inout } +L 7 130 10 150 10 {} +T {iin_15u} 125 6 0 1 0.2 0.2 {} +B 5 147.5 27.5 152.5 32.5 {name=dvdd dir=inout } +L 7 130 30 150 30 {} +T {dvdd} 125 26 0 1 0.2 0.2 {} +B 5 147.5 47.5 152.5 52.5 {name=out_n dir=out } +L 4 130 50 150 50 {} +T {out_n} 125 46 0 1 0.2 0.2 {}
diff --git a/xschem/src/Class_D/Class_D_post.sym b/xschem/src/Class_D/Class_D_post.sym new file mode 100644 index 0000000..9ef2285 --- /dev/null +++ b/xschem/src/Class_D/Class_D_post.sym
@@ -0,0 +1,66 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 90 -180 350 -180 {} +L 4 90 120 350 120 {} +L 4 90 -180 90 120 {} +L 4 350 -180 350 120 {} +L 4 350 -170 370 -170 {} +L 4 350 -150 370 -150 {} +L 4 350 -130 370 -130 {} +L 4 350 -110 370 -110 {} +L 4 350 -90 370 -90 {} +L 4 350 -70 370 -70 {} +L 4 70 -170 90 -170 {} +L 4 350 -30 370 -30 {} +L 4 350 10 370 10 {} +L 4 350 50 370 50 {} +L 4 350 90 370 90 {} +L 4 350 110 370 110 {} +L 4 70 -150 90 -150 {} +L 7 350 -50 370 -50 {} +L 7 350 -10 370 -10 {} +L 7 350 30 370 30 {} +L 7 350 70 370 70 {} +B 5 367.5 -172.5 372.5 -167.5 {name=vp_p dir=out } +B 5 367.5 -152.5 372.5 -147.5 {name=out_p dir=out } +B 5 367.5 -132.5 372.5 -127.5 {name=vp_n dir=out } +B 5 367.5 -112.5 372.5 -107.5 {name=vin_p dir=out } +B 5 367.5 -92.5 372.5 -87.5 {name=vcmp_p dir=out } +B 5 367.5 -72.5 372.5 -67.5 {name=vtriang dir=out } +B 5 67.5 -172.5 72.5 -167.5 {name=vin dir=in } +B 5 367.5 -52.5 372.5 -47.5 {name=avdd dir=inout } +B 5 367.5 -32.5 372.5 -27.5 {name=vin_n dir=out } +B 5 367.5 -12.5 372.5 -7.5 {name=vss dir=inout } +B 5 367.5 7.5 372.5 12.5 {name=vcmp_n dir=out } +B 5 367.5 27.5 372.5 32.5 {name=iin_15u dir=inout } +B 5 367.5 47.5 372.5 52.5 {name=vn_p dir=out } +B 5 367.5 67.5 372.5 72.5 {name=dvdd dir=inout } +B 5 367.5 87.5 372.5 92.5 {name=vn_n dir=out } +B 5 367.5 107.5 372.5 112.5 {name=out_n dir=out } +B 5 67.5 -152.5 72.5 -147.5 {name=vref dir=in } +T {@symname} 170.5 -36 0 0 0.3 0.3 {} +T {@name} 355 -192 0 0 0.2 0.2 {} +T {vp_p} 345 -174 0 1 0.2 0.2 {} +T {out_p} 345 -154 0 1 0.2 0.2 {} +T {vp_n} 345 -134 0 1 0.2 0.2 {} +T {vin_p} 345 -114 0 1 0.2 0.2 {} +T {vcmp_p} 345 -94 0 1 0.2 0.2 {} +T {vtriang} 345 -74 0 1 0.2 0.2 {} +T {vin} 95 -174 0 0 0.2 0.2 {} +T {avdd} 345 -54 0 1 0.2 0.2 {} +T {vin_n} 345 -34 0 1 0.2 0.2 {} +T {vss} 345 -14 0 1 0.2 0.2 {} +T {vcmp_n} 345 6 0 1 0.2 0.2 {} +T {iin_15u} 345 26 0 1 0.2 0.2 {} +T {vn_p} 345 46 0 1 0.2 0.2 {} +T {dvdd} 345 66 0 1 0.2 0.2 {} +T {vn_n} 345 86 0 1 0.2 0.2 {} +T {out_n} 345 106 0 1 0.2 0.2 {} +T {vref} 95 -154 0 0 0.2 0.2 {}
diff --git a/xschem/src/Class_D/Class_D_revised_tb.sch b/xschem/src/Class_D/Class_D_revised_tb.sch new file mode 100644 index 0000000..3143b64 --- /dev/null +++ b/xschem/src/Class_D/Class_D_revised_tb.sch
@@ -0,0 +1,473 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +T {140mA} 1790 -160 0 0 0.2 0.2 {} +T {140mA} 1790 80 0 0 0.2 0.2 {} +N -380 50 -380 80 { lab=vref} +N -380 140 -380 180 { lab=GND} +N 550 -450 920 -450 { lab=feedback_p} +N 420 -270 470 -270 { lab=vin_p} +N 1080 -310 1080 -280 { lab=vdd} +N 1080 -240 1080 -210 { lab=GND} +N 420 110 470 110 { lab=vin_n} +N 1070 90 1070 120 { lab=vdd} +N 1070 160 1070 190 { lab=GND} +N 1960 -260 2040 -260 { lab=audio_p} +N 1980 -260 1980 -250 { lab=audio_p} +N 1980 -190 1980 -170 { lab=GND} +N 1980 210 1980 230 { lab=GND} +N 400 -270 420 -270 { lab=vin_p} +N 1120 140 1130 140 { lab=vcmp_n} +N -290 50 -290 80 { lab=vdd} +N -290 140 -290 170 { lab=GND} +N 1280 -320 1280 -300 { lab=vdd} +N 1280 -220 1280 -200 { lab=GND} +N 1280 80 1280 100 { lab=vdd} +N 1280 180 1280 200 { lab=GND} +N 1130 140 1150 140 { lab=vcmp_n} +N 1950 150 1980 150 { lab=audio_n} +N 2040 -260 2040 -50 { lab=audio_p} +N 2040 -50 2040 -40 { lab=audio_p} +N 2040 20 2040 150 { lab=audio_n} +N 1980 150 2040 150 { lab=audio_n} +N 740 -120 950 -120 { lab=vtriang} +N -80 -70 80 -70 { lab=#net1} +N 90 -50 120 -50 { lab=vref} +N 90 -70 120 -70 { lab=#net1} +N 240 -140 240 -120 { lab=vdd} +N 240 -40 240 -20 { lab=GND} +N 550 -450 550 -290 { lab=feedback_p} +N 470 -290 470 -270 { lab=vin_p} +N 530 -290 550 -290 { lab=feedback_p} +N 530 110 550 110 { lab=feedback_n} +N 1130 -260 1150 -260 { lab=vcmp_p} +N 800 -220 800 -210 { lab=GND} +N 580 -110 610 -110 { lab=vbias2} +N 580 -90 610 -90 { lab=vref} +N 740 -90 790 -90 { lab=vsquare} +N 560 360 940 360 { lab=feedback_n} +N 560 110 560 360 { lab=feedback_n} +N -80 -10 -80 10 { lab=GND} +N 70 300 70 380 { lab=v1} +N 70 330 140 330 { lab=v1} +N 70 220 70 240 { lab=vdd} +N 70 440 70 450 { lab=GND} +N 70 410 70 440 { lab=GND} +N 110 410 150 410 { lab=v1} +N 140 330 140 410 { lab=v1} +N 150 410 190 410 { lab=v1} +N 190 410 630 410 { lab=v1} +N 220 450 250 450 { lab=GND} +N 400 450 430 450 { lab=GND} +N 570 450 600 450 { lab=GND} +N 240 450 240 480 { lab=GND} +N 420 450 420 480 { lab=GND} +N 580 450 580 480 { lab=GND} +N 190 450 220 450 { lab=GND} +N 250 450 280 450 { lab=GND} +N 370 450 400 450 { lab=GND} +N 430 450 460 450 { lab=GND} +N 540 450 570 450 { lab=GND} +N 600 450 630 450 { lab=GND} +N 630 410 790 410 { lab=v1} +N 740 450 760 450 { lab=GND} +N 750 450 750 480 { lab=GND} +N 760 450 790 450 { lab=GND} +N 710 450 740 450 { lab=GND} +N 980 -450 1580 -450 { lab=out_p} +N 1000 360 1570 360 { lab=out_n} +N 580 -130 610 -130 { lab=vbias1} +N 80 -70 90 -70 { lab=#net1} +N 90 -90 120 -90 { lab=vbias4} +N 90 -110 120 -110 { lab=vbias3} +N 160 450 160 500 { lab=vbias1} +N 310 450 310 500 { lab=vbias2} +N 340 450 340 500 { lab=vbias3} +N 490 450 490 500 { lab=vbias4} +N 510 450 510 500 { lab=vbias5} +N 660 450 660 500 { lab=vbias6} +N 680 450 680 500 { lab=vbias7} +N 820 450 820 500 { lab=vbias8} +N 470 -180 470 -150 { lab=#net2} +N 470 -180 670 -180 { lab=#net2} +N 670 -180 670 -160 { lab=#net2} +N 670 -160 670 -150 { lab=#net2} +N 470 -90 470 -70 { lab=GND} +N 400 110 420 110 { lab=vin_n} +N 360 -270 360 -90 { lab=vin_p} +N 360 -270 400 -270 { lab=vin_p} +N 360 -70 360 110 { lab=vin_n} +N 360 110 400 110 { lab=vin_n} +N 1770 350 1770 360 { lab=out_n} +N 1570 360 1770 360 { lab=out_n} +N 1580 -450 1770 -450 { lab=out_p} +N 1410 130 1440 130 { lab=vn_p} +N 1440 -40 1440 130 { lab=vn_p} +N 1440 -40 1470 -40 { lab=vn_p} +N 1400 150 1470 150 { lab=vn_n} +N 1470 -20 1470 150 { lab=vn_n} +N 1400 -270 1460 -270 { lab=vp_p} +N 1460 -270 1470 -270 { lab=vp_p} +N 1470 -270 1470 -80 { lab=vp_p} +N 1400 -250 1430 -250 { lab=vp_n} +N 1430 -250 1430 -60 { lab=vp_n} +N 1430 -60 1470 -60 { lab=vp_n} +N 1530 -230 1530 -180 { lab=GND} +N 1530 -330 1530 -290 { lab=#net3} +N 1530 -330 1590 -330 { lab=#net3} +N 1770 150 1890 150 { lab=out_n} +N 1770 -260 1900 -260 { lab=out_p} +N 1400 130 1410 130 { lab=vn_p} +N 550 110 560 110 { lab=feedback_n} +N 800 -370 800 -320 { lab=vdd} +N 800 -260 800 -220 { lab=GND} +N 630 -270 650 -270 { lab=vref} +N 550 -310 600 -310 { lab=feedback_p} +N 600 -310 650 -310 { lab=feedback_p} +N 630 -290 650 -290 { lab=vbias5} +N 950 -290 970 -290 { lab=error_p} +N 970 -290 970 -280 { lab=error_p} +N 970 -280 1020 -280 { lab=error_p} +N 950 -260 1020 -260 { lab=vtriang} +N 950 -260 950 -120 { lab=vtriang} +N 970 -240 1020 -240 { lab=vbias7} +N 670 -70 670 -30 { lab=GND} +N 800 60 800 100 { lab=vdd} +N 800 160 800 180 { lab=GND} +N 560 110 650 110 { lab=feedback_n} +N 610 130 650 130 { lab=vbias6} +N 610 150 650 150 { lab=vref} +N 980 160 1010 160 { lab=vbias8} +N 950 120 950 130 { lab=error_n} +N 950 120 1010 120 { lab=error_n} +N 950 -120 950 90 { lab=vtriang} +N 950 90 990 90 { lab=vtriang} +N 990 90 990 140 { lab=vtriang} +N 990 140 1010 140 { lab=vtriang} +N 1600 -330 1600 -100 { lab=#net3} +N 1590 -330 1600 -330 { lab=#net3} +N 1630 -330 1630 -100 { lab=#net3} +N 1600 -330 1630 -330 { lab=#net3} +N 1620 0 1620 40 { lab=GND} +N 1770 100 1770 150 { lab=out_n} +N 1770 -40 1770 40 { lab=#net4} +N 1770 -150 1770 -60 { lab=#net5} +N 1770 -260 1770 -210 { lab=out_p} +N 1770 150 1770 350 { lab=out_n} +N 1770 -450 1770 -260 { lab=out_p} +C {vsource.sym} -80 -40 0 0 {name=V1 value="sin(0.9 0.8 5k)"} +C {code_shown.sym} -1130 -450 0 0 {name=s2 only_toplevel=false value=" +.option rshunt=1e20 +.nodeset V(audio_p)=0.9 V(audio_n)=0.9 V(vp_p)=0.79 V(vn_p)=0 V(vcmp_p)=0.859 ++ V(vp_n)=0.79 V(vn_n)=0 V(vcmp_n)=0.859 v(vin_p)=0.9 v(vin_n)=0.9 v(vtriang)=0.9 +*.nodeset all=0.9 +*.option VNTOL=1e-6 ABSTOL=1e-9 +*.option savecurrents +*set the absolute voltage error tolerance and absolute current error tolerance +.control +save out_p out_n audio_p audio_n I(V4) I(V2) @r6[i] @r1[i] i(v3) i(v6) vtriang vin_p vin_n error_p error_n vcmp_p vcmp_n vp_p vp_n vn_p vn_n i(v7) +*save vtriang audio_p audio_n I(V2) @r6[i] out_p out_n +*op +tran 3n 10m +*linearize V(audio) +*linearize V(out) +*fft V(out) +*fft V(audio) +*plot mag(V(audio)) +*plot mag(V(out)) +let pout=@r6[i]*(V(audio_p)-V(audio_n)) +let pin=1.8*(I(V4)+I(V2)+I(V3)) +meas tran pload avg pout from=2m to=9m +meas tran p_supply avg pin from=2m to=9m +*print pload/p_supply +set nfreqs=20 +*fourier 10k V(out_p)-V(out_n) + +fourier 5k V(audio_p)-V(audio_n) +write class_d_5k_08_output_current_test.raw + +.endc + + +"} +C {netlist_not_shown.sym} -310 -140 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice +.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_post.spice +.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_post.spice +.include /home/eda/magic/class_d_audio_amplifier/comparator/comparator_post.spice +.include /home/eda/magic/class_d_audio_amplifier/dead_time/dead_time_post.spice +.include /home/eda/magic/class_d_audio_amplifier/output_driver/output_driver_post.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {lab_wire.sym} 870 -120 0 0 {name=l9 sig_type=std_logic lab=vtriang} +C {vsource.sym} -380 110 0 0 {name=V5 value=0.9} +C {lab_wire.sym} -380 70 0 0 {name=l26 sig_type=std_logic lab=vref} +C {lab_wire.sym} 420 -270 0 1 {name=l1 sig_type=std_logic lab=vin_p} +C {lab_wire.sym} 800 -350 0 0 {name=l6 sig_type=std_logic lab=vdd} +C {ind.sym} 1930 -260 1 0 {name=L1 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 1980 -220 0 0 {name=C1 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} 950 -450 1 0 {name=R1 +value=200k +footprint=1206 +device=resistor +m=1} +C {res.sym} 500 -290 1 0 {name=R3 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 550 -360 0 0 {name=l18 sig_type=std_logic lab=feedback_p} +C {lab_wire.sym} 1140 -260 0 0 {name=l19 sig_type=std_logic lab=vcmp_p} +C {lab_wire.sym} 1080 -300 0 0 {name=l21 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 1000 -280 0 0 {name=l8 sig_type=std_logic lab=error_p} +C {lab_wire.sym} 800 80 0 0 {name=l24 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 630 150 0 0 {name=l27 sig_type=std_logic lab=vref} +C {res.sym} 970 360 1 0 {name=R4 +value=200k +footprint=1206 +device=resistor +m=1} +C {res.sym} 500 110 1 0 {name=R5 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 1070 100 0 0 {name=l38 sig_type=std_logic lab=vdd} +C {ind.sym} 1920 150 3 1 {name=L2 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 1980 180 0 1 {name=C4 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} 2040 -10 2 0 {name=R6 +value=8 +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 960 120 0 0 {name=l29 sig_type=std_logic lab=error_n} +C {lab_wire.sym} 560 190 0 0 {name=l30 sig_type=std_logic lab=feedback_n} +C {lab_wire.sym} 1130 140 0 1 {name=l40 sig_type=std_logic lab=vcmp_n} +C {lab_wire.sym} 1990 -260 0 1 {name=l43 sig_type=std_logic lab=audio_p} +C {lab_wire.sym} 1990 150 0 1 {name=l44 sig_type=std_logic lab=audio_n} +C {vsource.sym} -290 110 0 0 {name=V4 value="pulse(0 1.8 0 10n 10n 10 20)"} +C {lab_wire.sym} -290 60 0 0 {name=l16 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 1280 -320 0 0 {name=l17 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 1280 80 0 0 {name=l34 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 1430 130 0 0 {name=l51 sig_type=std_logic lab=vn_p} +C {lab_wire.sym} 1440 150 0 0 {name=l52 sig_type=std_logic lab=vn_n} +C {lab_wire.sym} 110 -110 0 0 {name=l36 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 110 -50 0 0 {name=l56 sig_type=std_logic lab=vref} +C {lab_wire.sym} 240 -130 0 0 {name=l57 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 640 -290 0 0 {name=l3 sig_type=std_logic lab=vbias5} +C {lab_wire.sym} 630 130 0 0 {name=l14 sig_type=std_logic lab=vbias6} +C {lab_wire.sym} 1010 -240 0 0 {name=l20 sig_type=std_logic lab=vbias7} +C {lab_wire.sym} 590 -110 0 0 {name=l45 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 590 -90 0 0 {name=l46 sig_type=std_logic lab=vref} +C {lab_wire.sym} 750 -90 0 1 {name=l60 sig_type=std_logic lab=vsquare} +C {lab_wire.sym} 990 160 0 0 {name=l61 sig_type=std_logic lab=vbias8} +C {gnd.sym} -290 170 0 0 {name=l63 lab=GND} +C {gnd.sym} -380 180 0 0 {name=l2 lab=GND} +C {gnd.sym} -80 10 0 0 {name=l4 lab=GND} +C {gnd.sym} 240 -20 0 0 {name=l5 lab=GND} +C {gnd.sym} 800 -210 0 0 {name=l11 lab=GND} +C {gnd.sym} 1080 -210 0 0 {name=l13 lab=GND} +C {gnd.sym} 1280 -200 0 0 {name=l22 lab=GND} +C {gnd.sym} 1280 200 0 0 {name=l41 lab=GND} +C {gnd.sym} 1070 190 0 0 {name=l42 lab=GND} +C {gnd.sym} 800 180 0 0 {name=l48 lab=GND} +C {gnd.sym} 1980 230 0 0 {name=l55 lab=GND} +C {gnd.sym} 1980 -170 0 0 {name=l58 lab=GND} +C {isource.sym} 70 270 0 0 {name=I0 value=15u} +C {lab_wire.sym} 70 220 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} 70 450 0 0 {name=l10 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 90 410 0 1 {name=M5 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 190 430 3 1 {name=M6 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} 120 330 0 1 {name=l62 sig_type=std_logic lab=v1} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 280 430 1 0 {name=M7 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 370 430 3 1 {name=M8 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 460 430 1 0 {name=M9 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 540 430 3 1 {name=M10 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 630 430 1 0 {name=M11 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} 240 480 0 0 {name=l54 lab=GND} +C {gnd.sym} 420 480 0 0 {name=l59 lab=GND} +C {gnd.sym} 580 480 0 0 {name=l64 lab=GND} +C {gnd.sym} 750 480 0 0 {name=l65 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 710 430 1 0 {name=M12 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 790 430 1 0 {name=M13 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} 590 -130 0 0 {name=l32 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 110 -90 0 0 {name=l35 sig_type=std_logic lab=vbias4} +C {lab_wire.sym} 160 490 0 0 {name=l39 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 310 500 0 0 {name=l66 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 340 500 0 1 {name=l67 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 490 500 0 0 {name=l68 sig_type=std_logic lab=vbias4} +C {lab_wire.sym} 510 500 0 1 {name=l69 sig_type=std_logic lab=vbias5} +C {lab_wire.sym} 660 490 0 0 {name=l70 sig_type=std_logic lab=vbias6} +C {lab_wire.sym} 680 500 0 1 {name=l71 sig_type=std_logic lab=vbias7} +C {lab_wire.sym} 820 490 0 1 {name=l72 sig_type=std_logic lab=vbias8} +C {vsource.sym} 470 -120 0 0 {name=V2 value=1.8} +C {gnd.sym} 470 -70 0 0 {name=l47 lab=GND} +C {lab_wire.sym} 410 110 0 1 {name=l23 sig_type=std_logic lab=vin_n} +C {lab_wire.sym} 1450 -270 0 1 {name=l15 sig_type=std_logic lab=vp_p} +C {lab_wire.sym} 1430 -220 0 1 {name=l25 sig_type=std_logic lab=vp_n} +C {vsource.sym} 1530 -260 0 0 {name=V3 value=1.8} +C {gnd.sym} 1530 -180 0 0 {name=l28 lab=GND} +C {gnd.sym} 1620 40 0 0 {name=l31 lab=GND} +C {lab_wire.sym} 1820 -260 0 1 {name=l33 sig_type=std_logic lab=out_p} +C {lab_wire.sym} 1830 150 0 1 {name=l37 sig_type=std_logic lab=out_n} +C {lab_wire.sym} 640 -270 0 0 {name=l7 sig_type=std_logic lab=vref} +C {gnd.sym} 670 -30 0 0 {name=l12 lab=GND} +C {src/S_to_D/S_to_D.sym} 270 -80 0 0 {name=x1} +C {src/triangle/triangle.sym} 670 -110 0 0 {name=x2} +C {src/integrator/integrator.sym} 800 -290 0 0 {name=x3} +C {src/integrator/integrator.sym} 800 130 0 0 {name=x4} +C {src/comparator/comparator.sym} 1110 -220 0 0 {name=x5} +C {src/comparator/comparator.sym} 1100 180 0 0 {name=x6} +C {src/dead_time/dead_time.sym} 1250 -260 0 0 {name=x7} +C {src/dead_time/dead_time.sym} 1250 140 0 0 {name=x8} +C {src/output_driver/output_driver.sym} 1620 -50 0 0 {name=x9} +C {vsource.sym} 1770 -180 0 0 {name=V6 value=0} +C {vsource.sym} 1770 70 0 0 {name=V7 value=0}
diff --git a/xschem/src/Class_D/Class_D_revised_tb_2.sch b/xschem/src/Class_D/Class_D_revised_tb_2.sch new file mode 100644 index 0000000..4ee1c6b --- /dev/null +++ b/xschem/src/Class_D/Class_D_revised_tb_2.sch
@@ -0,0 +1,320 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -110 80 -110 110 { lab=vref} +N -110 170 -110 210 { lab=GND} +N 820 -420 1190 -420 { lab=feedback_p} +N 690 -240 740 -240 { lab=vin_p} +N 1350 -280 1350 -250 { lab=vdd} +N 1350 -210 1350 -180 { lab=GND} +N 690 140 740 140 { lab=vin_n} +N 1340 120 1340 150 { lab=vdd} +N 1340 190 1340 220 { lab=GND} +N 2230 -230 2310 -230 { lab=audio_p} +N 2250 -230 2250 -220 { lab=audio_p} +N 2250 -160 2250 -140 { lab=GND} +N 2250 240 2250 260 { lab=GND} +N 670 -240 690 -240 { lab=vin_p} +N 1390 170 1400 170 { lab=vcmp_n} +N -20 80 -20 110 { lab=vdd} +N -20 170 -20 200 { lab=GND} +N 1550 -290 1550 -270 { lab=vdd} +N 1550 -190 1550 -170 { lab=GND} +N 1550 110 1550 130 { lab=vdd} +N 1550 210 1550 230 { lab=GND} +N 1400 170 1420 170 { lab=vcmp_n} +N 2220 180 2250 180 { lab=audio_n} +N 2310 -230 2310 -20 { lab=audio_p} +N 2310 -20 2310 -10 { lab=audio_p} +N 2310 50 2310 180 { lab=audio_n} +N 2250 180 2310 180 { lab=audio_n} +N 1010 -90 1220 -90 { lab=vtriang} +N 190 -40 350 -40 { lab=#net1} +N 360 -20 390 -20 { lab=vref} +N 360 -40 390 -40 { lab=#net1} +N 510 -110 510 -90 { lab=vdd} +N 510 -10 510 10 { lab=GND} +N 820 -420 820 -260 { lab=feedback_p} +N 740 -260 740 -240 { lab=vin_p} +N 800 -260 820 -260 { lab=feedback_p} +N 800 140 820 140 { lab=feedback_n} +N 1400 -230 1420 -230 { lab=vcmp_p} +N 1070 -190 1070 -180 { lab=GND} +N 850 -80 880 -80 { lab=vbias2} +N 850 -60 880 -60 { lab=vref} +N 1010 -60 1060 -60 { lab=vsquare} +N 830 390 1210 390 { lab=feedback_n} +N 830 140 830 390 { lab=feedback_n} +N 190 20 190 40 { lab=GND} +N 1250 -420 1850 -420 { lab=out_p} +N 1270 390 1840 390 { lab=out_n} +N 850 -100 880 -100 { lab=vbias1} +N 350 -40 360 -40 { lab=#net1} +N 360 -60 390 -60 { lab=vbias4} +N 360 -80 390 -80 { lab=vbias3} +N 740 -150 740 -120 { lab=#net2} +N 740 -150 940 -150 { lab=#net2} +N 940 -150 940 -130 { lab=#net2} +N 940 -130 940 -120 { lab=#net2} +N 740 -60 740 -40 { lab=GND} +N 670 140 690 140 { lab=vin_n} +N 630 -240 630 -60 { lab=vin_p} +N 630 -240 670 -240 { lab=vin_p} +N 630 -40 630 140 { lab=vin_n} +N 630 140 670 140 { lab=vin_n} +N 2040 -420 2040 -30 { lab=out_p} +N 2040 -10 2040 380 { lab=out_n} +N 2040 380 2040 390 { lab=out_n} +N 1840 390 2040 390 { lab=out_n} +N 1850 -420 2040 -420 { lab=out_p} +N 1680 160 1710 160 { lab=vn_p} +N 1710 -10 1710 160 { lab=vn_p} +N 1710 -10 1740 -10 { lab=vn_p} +N 1670 180 1740 180 { lab=vn_n} +N 1740 10 1740 180 { lab=vn_n} +N 1670 -240 1730 -240 { lab=vp_p} +N 1730 -240 1740 -240 { lab=vp_p} +N 1740 -240 1740 -50 { lab=vp_p} +N 1670 -220 1700 -220 { lab=vp_n} +N 1700 -220 1700 -30 { lab=vp_n} +N 1700 -30 1740 -30 { lab=vp_n} +N 1860 -100 1860 -60 { lab=#net3} +N 1890 -100 1890 -60 { lab=#net3} +N 1800 -200 1800 -150 { lab=GND} +N 1800 -300 1800 -260 { lab=#net3} +N 1800 -300 1860 -300 { lab=#net3} +N 1860 -300 1860 -100 { lab=#net3} +N 1860 -100 1890 -100 { lab=#net3} +N 2040 180 2160 180 { lab=out_n} +N 2040 -230 2170 -230 { lab=out_p} +N 1890 20 1890 70 { lab=GND} +N 1670 160 1680 160 { lab=vn_p} +N 820 140 830 140 { lab=feedback_n} +N 1070 -340 1070 -290 { lab=vdd} +N 1070 -230 1070 -190 { lab=GND} +N 900 -240 920 -240 { lab=vref} +N 820 -280 870 -280 { lab=feedback_p} +N 870 -280 920 -280 { lab=feedback_p} +N 900 -260 920 -260 { lab=vbias5} +N 1220 -260 1240 -260 { lab=error_p} +N 1240 -260 1240 -250 { lab=error_p} +N 1240 -250 1290 -250 { lab=error_p} +N 1220 -230 1290 -230 { lab=vtriang} +N 1220 -230 1220 -90 { lab=vtriang} +N 1240 -210 1290 -210 { lab=vbias7} +N 940 -40 940 0 { lab=GND} +N 1070 90 1070 130 { lab=vdd} +N 1070 190 1070 210 { lab=GND} +N 830 140 920 140 { lab=feedback_n} +N 880 160 920 160 { lab=vbias6} +N 880 180 920 180 { lab=vref} +N 1250 190 1280 190 { lab=vbias8} +N 1220 150 1220 160 { lab=error_n} +N 1220 150 1280 150 { lab=error_n} +N 1220 -90 1220 120 { lab=vtriang} +N 1220 120 1260 120 { lab=vtriang} +N 1260 120 1260 170 { lab=vtriang} +N 1260 170 1280 170 { lab=vtriang} +N 480 280 480 360 { lab=#net4} +N 480 560 480 610 { lab=GND} +N 480 190 480 220 { lab=vdd} +N 580 390 630 390 { lab=vbias1} +N 580 410 630 410 { lab=vbias2} +N 580 430 630 430 { lab=vbias3} +N 580 450 630 450 { lab=vbias4} +N 580 470 630 470 { lab=vbias5} +N 580 490 630 490 { lab=vbias6} +N 580 510 630 510 { lab=vbias7} +N 580 530 630 530 { lab=vbias8} +C {vsource.sym} 190 -10 0 0 {name=V1 value="sin(0.9 0.4 5k)"} +C {code_shown.sym} -860 -420 0 0 {name=s2 only_toplevel=false value=" +.option rshunt=1e20 +.nodeset V(audio_p)=0.9 V(audio_n)=0.9 V(vp_p)=0.79 V(vn_p)=0 V(vcmp_p)=0.859 ++ V(vp_n)=0.79 V(vn_n)=0 V(vcmp_n)=0.859 v(vin_p)=0.9 v(vin_n)=0.9 v(vtriang)=0.9 +*.nodeset all=0.9 +*.option VNTOL=1e-6 ABSTOL=1e-9 +*.option savecurrents +*set the absolute voltage error tolerance and absolute current error tolerance +.control +save out_p out_n audio_p audio_n I(V4) I(V2) @r6[i] @r1[i] i(v3) i(v6) vtriang vin_p vin_n error_p error_n vcmp_p vcmp_n vp_p vp_n vn_p vn_n +*save vtriang audio_p audio_n I(V2) @r6[i] out_p out_n +*op +tran 3n 10m 0.1m +*linearize V(audio) +*linearize V(out) +*fft V(out) +*fft V(audio) +*plot mag(V(audio)) +*plot mag(V(out)) +let pout=@r6[i]*(V(audio_p)-V(audio_n)) +let pin=1.8*(I(V4)+I(V2)+I(V3)) +meas tran pload avg pout from=2m to=9m +meas tran p_supply avg pin from=2m to=9m +*print pload/p_supply +set nfreqs=20 +*fourier 10k V(out_p)-V(out_n) + +fourier 5k V(audio_p)-V(audio_n) +write class_d_5k_04_post_notflat.raw + +.endc + + +"} +C {netlist_not_shown.sym} 370 -350 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice +.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_post.spice +.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_revised_post.spice +.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_post.spice +.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_revised_post.spice +.include /home/eda/magic/class_d_audio_amplifier/comparator/comparator_post.spice +.include /home/eda/magic/class_d_audio_amplifier/dead_time/dead_time_post.spice +.include /home/eda/magic/class_d_audio_amplifier/output_driver/output_driver_post_r.spice +.include /home/eda/magic/class_d_audio_amplifier/integrator/integrator_post.spice +.include /home/eda/magic/class_d_audio_amplifier/biasing_network.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {lab_wire.sym} 1140 -90 0 0 {name=l9 sig_type=std_logic lab=vtriang} +C {vsource.sym} -110 140 0 0 {name=V5 value=0.9} +C {lab_wire.sym} -110 100 0 0 {name=l26 sig_type=std_logic lab=vref} +C {lab_wire.sym} 690 -240 0 1 {name=l1 sig_type=std_logic lab=vin_p} +C {lab_wire.sym} 1070 -320 0 0 {name=l6 sig_type=std_logic lab=vdd} +C {ind.sym} 2200 -230 1 0 {name=L1 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 2250 -190 0 0 {name=C1 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} 1220 -420 1 0 {name=R1 +value=200k +footprint=1206 +device=resistor +m=1} +C {res.sym} 770 -260 1 0 {name=R3 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 820 -330 0 0 {name=l18 sig_type=std_logic lab=feedback_p} +C {lab_wire.sym} 1410 -230 0 0 {name=l19 sig_type=std_logic lab=vcmp_p} +C {lab_wire.sym} 1350 -270 0 0 {name=l21 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 1270 -250 0 0 {name=l8 sig_type=std_logic lab=error_p} +C {lab_wire.sym} 1070 110 0 0 {name=l24 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 900 180 0 0 {name=l27 sig_type=std_logic lab=vref} +C {res.sym} 1240 390 1 0 {name=R4 +value=200k +footprint=1206 +device=resistor +m=1} +C {res.sym} 770 140 1 0 {name=R5 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 1340 130 0 0 {name=l38 sig_type=std_logic lab=vdd} +C {ind.sym} 2190 180 3 1 {name=L2 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 2250 210 0 1 {name=C4 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} 2310 20 2 0 {name=R6 +value=8 +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 1230 150 0 0 {name=l29 sig_type=std_logic lab=error_n} +C {lab_wire.sym} 830 220 0 0 {name=l30 sig_type=std_logic lab=feedback_n} +C {lab_wire.sym} 1400 170 0 1 {name=l40 sig_type=std_logic lab=vcmp_n} +C {lab_wire.sym} 2260 -230 0 1 {name=l43 sig_type=std_logic lab=audio_p} +C {lab_wire.sym} 2260 180 0 1 {name=l44 sig_type=std_logic lab=audio_n} +C {vsource.sym} -20 140 0 0 {name=V4 value="pulse(0 1.8 0 10n 10n 10 20)"} +C {lab_wire.sym} -20 90 0 0 {name=l16 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 1550 -290 0 0 {name=l17 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 1550 110 0 0 {name=l34 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 1700 160 0 0 {name=l51 sig_type=std_logic lab=vn_p} +C {lab_wire.sym} 1710 180 0 0 {name=l52 sig_type=std_logic lab=vn_n} +C {lab_wire.sym} 380 -80 0 0 {name=l36 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 380 -20 0 0 {name=l56 sig_type=std_logic lab=vref} +C {lab_wire.sym} 510 -100 0 0 {name=l57 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 910 -260 0 0 {name=l3 sig_type=std_logic lab=vbias5} +C {lab_wire.sym} 900 160 0 0 {name=l14 sig_type=std_logic lab=vbias6} +C {lab_wire.sym} 1280 -210 0 0 {name=l20 sig_type=std_logic lab=vbias7} +C {lab_wire.sym} 860 -80 0 0 {name=l45 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 860 -60 0 0 {name=l46 sig_type=std_logic lab=vref} +C {lab_wire.sym} 1020 -60 0 1 {name=l60 sig_type=std_logic lab=vsquare} +C {lab_wire.sym} 1260 190 0 0 {name=l61 sig_type=std_logic lab=vbias8} +C {gnd.sym} -20 200 0 0 {name=l63 lab=GND} +C {gnd.sym} -110 210 0 0 {name=l2 lab=GND} +C {gnd.sym} 190 40 0 0 {name=l4 lab=GND} +C {gnd.sym} 510 10 0 0 {name=l5 lab=GND} +C {gnd.sym} 1070 -180 0 0 {name=l11 lab=GND} +C {gnd.sym} 1350 -180 0 0 {name=l13 lab=GND} +C {gnd.sym} 1550 -170 0 0 {name=l22 lab=GND} +C {gnd.sym} 1550 230 0 0 {name=l41 lab=GND} +C {gnd.sym} 1340 220 0 0 {name=l42 lab=GND} +C {gnd.sym} 1070 210 0 0 {name=l48 lab=GND} +C {gnd.sym} 2250 260 0 0 {name=l55 lab=GND} +C {gnd.sym} 2250 -140 0 0 {name=l58 lab=GND} +C {lab_wire.sym} 860 -100 0 0 {name=l32 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 380 -60 0 0 {name=l35 sig_type=std_logic lab=vbias4} +C {vsource.sym} 740 -90 0 0 {name=V2 value=1.8} +C {gnd.sym} 740 -40 0 0 {name=l47 lab=GND} +C {lab_wire.sym} 680 140 0 1 {name=l23 sig_type=std_logic lab=vin_n} +C {src/output_driver/output_driver_post.sym} 1910 -10 0 0 {name=x9} +C {lab_wire.sym} 1720 -240 0 1 {name=l15 sig_type=std_logic lab=vp_p} +C {lab_wire.sym} 1700 -190 0 1 {name=l25 sig_type=std_logic lab=vp_n} +C {vsource.sym} 1800 -230 0 0 {name=V3 value=1.8} +C {gnd.sym} 1800 -150 0 0 {name=l28 lab=GND} +C {gnd.sym} 1890 70 0 0 {name=l31 lab=GND} +C {lab_wire.sym} 2090 -230 0 1 {name=l33 sig_type=std_logic lab=out_p} +C {lab_wire.sym} 2100 180 0 1 {name=l37 sig_type=std_logic lab=out_n} +C {lab_wire.sym} 910 -240 0 0 {name=l7 sig_type=std_logic lab=vref} +C {gnd.sym} 940 0 0 0 {name=l12 lab=GND} +C {src/dead_time/dead_time_post.sym} 1480 -250 0 0 {name=x7} +C {src/dead_time/dead_time_post.sym} 1480 150 0 0 {name=x8} +C {src/comparator/comparator_post.sym} 1300 -250 0 0 {name=x5} +C {src/comparator/comparator_post.sym} 1290 150 0 0 {name=x6} +C {src/integrator/integrator_post.sym} 950 -260 0 0 {name=x3} +C {src/integrator/integrator_post.sym} 950 160 0 0 {name=x4} +C {src/S_to_D/S_to_D_revised_post.sym} 390 -70 0 0 {name=x1} +C {src/triangle/triangle_revised_post.sym} 870 -80 0 0 {name=x2} +C {src/biasing_network/biasing_network.sym} 430 460 0 0 {name=x10} +C {gnd.sym} 480 610 0 0 {name=l10 lab=GND} +C {res.sym} 480 250 2 0 {name=R2 +value=83k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 480 200 0 0 {name=l39 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 630 390 0 0 {name=l49 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 630 410 0 0 {name=l50 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 630 430 0 0 {name=l53 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 630 450 0 0 {name=l54 sig_type=std_logic lab=vbias4} +C {lab_wire.sym} 630 470 0 0 {name=l59 sig_type=std_logic lab=vbias5} +C {lab_wire.sym} 630 490 0 0 {name=l62 sig_type=std_logic lab=vbias6} +C {lab_wire.sym} 630 510 0 0 {name=l64 sig_type=std_logic lab=vbias7} +C {lab_wire.sym} 630 530 0 0 {name=l65 sig_type=std_logic lab=vbias8}
diff --git a/xschem/src/Class_D/Class_D_tb.sch b/xschem/src/Class_D/Class_D_tb.sch new file mode 100644 index 0000000..1446a4c --- /dev/null +++ b/xschem/src/Class_D/Class_D_tb.sch
@@ -0,0 +1,482 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -1160 100 -1160 130 { lab=vref} +N -1160 190 -1160 230 { lab=GND} +N -100 -260 -40 -260 { lab=vref} +N 20 -290 20 -260 { lab=vdd} +N 20 -220 20 -180 { lab=GND} +N -230 -400 140 -400 { lab=feedback_p} +N -360 -220 -310 -220 { lab=vin_p} +N 300 -260 300 -230 { lab=vdd} +N 300 -190 300 -160 { lab=GND} +N -100 140 -40 140 { lab=vref} +N 70 160 110 160 { lab=error_n} +N 20 110 20 140 { lab=vdd} +N 20 180 20 220 { lab=GND} +N -100 280 -30 280 { lab=feedback_n} +N -100 180 -100 280 { lab=feedback_n} +N 30 280 100 280 { lab=error_n} +N 100 160 100 280 { lab=error_n} +N -360 160 -310 160 { lab=vin_n} +N 290 140 290 170 { lab=vdd} +N 290 210 290 240 { lab=GND} +N 1180 -210 1260 -210 { lab=audio_p} +N 1200 -210 1200 -200 { lab=audio_p} +N 1200 -140 1200 -120 { lab=GND} +N 1200 260 1200 280 { lab=GND} +N -380 -220 -360 -220 { lab=vin_p} +N 340 190 350 190 { lab=vcmp_n} +N -1070 100 -1070 130 { lab=vdd} +N -1070 190 -1070 220 { lab=GND} +N 500 -270 500 -250 { lab=vdd} +N 500 -170 500 -150 { lab=GND} +N 500 130 500 150 { lab=vdd} +N 500 230 500 250 { lab=GND} +N 350 190 370 190 { lab=vcmp_n} +N 1170 200 1200 200 { lab=audio_n} +N 1260 -210 1260 0 { lab=audio_p} +N 1260 0 1260 10 { lab=audio_p} +N 1260 70 1260 200 { lab=audio_n} +N 1200 200 1260 200 { lab=audio_n} +N 70 -240 100 -240 { lab=error_p} +N -100 -220 -100 -160 { lab=feedback_p} +N -40 -160 80 -160 { lab=error_p} +N 80 -240 80 -160 { lab=error_p} +N -40 -70 170 -70 { lab=vtriang} +N 170 -180 170 -70 { lab=vtriang} +N -860 -20 -700 -20 { lab=#net1} +N -690 0 -660 0 { lab=vref} +N -690 -20 -660 -20 { lab=#net1} +N -540 -90 -540 -70 { lab=vdd} +N -540 10 -540 30 { lab=GND} +N -230 -240 -40 -240 { lab=feedback_p} +N -100 -240 -100 -220 { lab=feedback_p} +N -230 -400 -230 -240 { lab=feedback_p} +N -310 -240 -310 -220 { lab=vin_p} +N -250 -240 -230 -240 { lab=feedback_p} +N -60 -220 -40 -220 { lab=vbias5} +N -230 160 -40 160 { lab=feedback_n} +N -250 160 -230 160 { lab=feedback_n} +N -100 160 -100 180 { lab=feedback_n} +N -80 180 -40 180 { lab=vbias6} +N 100 -240 100 -230 { lab=error_p} +N 100 -230 240 -230 { lab=error_p} +N 170 -210 170 -180 { lab=vtriang} +N 170 -210 240 -210 { lab=vtriang} +N 200 -190 240 -190 { lab=vbias7} +N 350 -210 370 -210 { lab=vcmp_p} +N -110 -20 -110 -10 { lab=GND} +N -200 -60 -170 -60 { lab=vbias2} +N -200 -40 -170 -40 { lab=vref} +N -40 -40 10 -40 { lab=vsquare} +N 130 -70 130 190 { lab=vtriang} +N 130 190 230 190 { lab=vtriang} +N 200 170 230 170 { lab=error_n} +N 110 160 110 170 { lab=error_n} +N 110 170 200 170 { lab=error_n} +N 200 210 230 210 { lab=vbias8} +N -220 410 160 410 { lab=feedback_n} +N -220 160 -220 410 { lab=feedback_n} +N -860 40 -860 60 { lab=GND} +N -710 350 -710 430 { lab=v1} +N -710 380 -640 380 { lab=v1} +N -710 270 -710 290 { lab=vdd} +N -710 490 -710 500 { lab=GND} +N -710 460 -710 490 { lab=GND} +N -670 460 -630 460 { lab=v1} +N -640 380 -640 460 { lab=v1} +N -630 460 -590 460 { lab=v1} +N -590 460 -150 460 { lab=v1} +N -560 500 -530 500 { lab=GND} +N -380 500 -350 500 { lab=GND} +N -210 500 -180 500 { lab=GND} +N -540 500 -540 530 { lab=GND} +N -360 500 -360 530 { lab=GND} +N -200 500 -200 530 { lab=GND} +N -590 500 -560 500 { lab=GND} +N -530 500 -500 500 { lab=GND} +N -410 500 -380 500 { lab=GND} +N -350 500 -320 500 { lab=GND} +N -240 500 -210 500 { lab=GND} +N -180 500 -150 500 { lab=GND} +N -150 460 10 460 { lab=v1} +N -40 500 -20 500 { lab=GND} +N -30 500 -30 530 { lab=GND} +N -20 500 10 500 { lab=GND} +N -70 500 -40 500 { lab=GND} +N 200 -400 800 -400 { lab=out_p} +N 220 410 790 410 { lab=out_n} +N -200 -80 -170 -80 { lab=vbias1} +N -700 -20 -690 -20 { lab=#net1} +N -690 -40 -660 -40 { lab=vbias4} +N -690 -60 -660 -60 { lab=vbias3} +N -620 500 -620 550 { lab=vbias1} +N -470 500 -470 550 { lab=vbias2} +N -440 500 -440 550 { lab=vbias3} +N -290 500 -290 550 { lab=vbias4} +N -270 500 -270 550 { lab=vbias5} +N -120 500 -120 550 { lab=vbias6} +N -100 500 -100 550 { lab=vbias7} +N 40 500 40 550 { lab=vbias8} +N -310 -130 -310 -100 { lab=#net2} +N -310 -130 -110 -130 { lab=#net2} +N -110 -130 -110 -110 { lab=#net2} +N -110 -110 -110 -100 { lab=#net2} +N -310 -40 -310 -20 { lab=GND} +N -380 160 -360 160 { lab=vin_n} +N -420 -220 -420 -40 { lab=vin_p} +N -420 -220 -380 -220 { lab=vin_p} +N -420 -20 -420 160 { lab=vin_n} +N -420 160 -380 160 { lab=vin_n} +N 990 -400 990 -10 { lab=out_p} +N 990 10 990 400 { lab=out_n} +N 990 400 990 410 { lab=out_n} +N 790 410 990 410 { lab=out_n} +N 800 -400 990 -400 { lab=out_p} +N 630 180 660 180 { lab=vn_p} +N 660 10 660 180 { lab=vn_p} +N 660 10 690 10 { lab=vn_p} +N 620 200 690 200 { lab=vn_n} +N 690 30 690 200 { lab=vn_n} +N 620 -220 680 -220 { lab=vp_p} +N 680 -220 690 -220 { lab=vp_p} +N 690 -220 690 -30 { lab=vp_p} +N 620 -200 650 -200 { lab=vp_n} +N 650 -200 650 -10 { lab=vp_n} +N 650 -10 690 -10 { lab=vp_n} +N 810 -80 810 -40 { lab=#net3} +N 840 -80 840 -40 { lab=#net3} +N 750 -180 750 -130 { lab=GND} +N 750 -280 750 -240 { lab=#net3} +N 750 -280 810 -280 { lab=#net3} +N 810 -280 810 -80 { lab=#net3} +N 810 -80 840 -80 { lab=#net3} +N 990 200 1110 200 { lab=out_n} +N 990 -210 1120 -210 { lab=out_p} +N 840 40 840 90 { lab=GND} +N 620 180 630 180 { lab=vn_p} +C {vsource.sym} -860 10 0 0 {name=V1 value="sin(0.9 0.4 5k)"} +C {code_shown.sym} -1910 -400 0 0 {name=s2 only_toplevel=false value=" +.option rshunt=1e20 +.nodeset V(audio_p)=0.9 V(audio_n)=0.9 V(vp_p)=0.79 V(vn_p)=0 V(vcmp_p)=0.859 ++ V(vp_n)=0.79 V(vn_n)=0 V(vcmp_n)=0.859 v(vin_p)=0.9 v(vin_n)=0.9 v(vtriang)=0.9 +*.nodeset all=0.9 +.option VNTOL=1e-6 ABSTOL=1e-9 +*.option savecurrents +*set the absolute voltage error tolerance and absolute current error tolerance +.control +save out_p out_n audio_p audio_n I(V4) I(V2) @r6[i] @r1[i] i(v3) i(v6) vtriang vin_p vin_n error_p error_n vcmp_p vcmp_n vp_p vp_n vn_p vn_n +*save vtriang audio_p audio_n I(V2) @r6[i] out_p out_n +*op +tran 3n 2m 0.1m +*linearize V(audio) +*linearize V(out) +*fft V(out) +*fft V(audio) +*plot mag(V(audio)) +*plot mag(V(out)) +let pout=@r6[i]*(V(audio_p)-V(audio_n)) +let pin=1.8*(I(V4)+I(V2)+I(V3)) +meas tran pload avg pout from=4m to=9m +meas tran p_supply avg pin from=4m to=9m +*print pload/p_supply +set nfreqs=20 +*fourier 10k V(out_p)-V(out_n) + +fourier 5k V(audio_p)-V(audio_n) +write class_d_5k_04_post.raw + +.endc + + +"} +C {netlist_not_shown.sym} -680 -330 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice +.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_post.spice +.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_post.spice +.include /home/eda/magic/class_d_audio_amplifier/comparator/comparator_post.spice +.include /home/eda/magic/class_d_audio_amplifier/dead_time/dead_time_post.spice +.include /home/eda/magic/class_d_audio_amplifier/output_driver/output_driver_post.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {lab_wire.sym} 90 -70 0 0 {name=l9 sig_type=std_logic lab=vtriang} +C {vsource.sym} -1160 160 0 0 {name=V5 value=0.9} +C {lab_wire.sym} -1160 120 0 0 {name=l26 sig_type=std_logic lab=vref} +C {lab_wire.sym} -360 -220 0 1 {name=l1 sig_type=std_logic lab=vin_p} +C {lab_wire.sym} 20 -280 0 0 {name=l6 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -70 -260 0 0 {name=l7 sig_type=std_logic lab=vref} +C {ind.sym} 1150 -210 1 0 {name=L1 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 1200 -170 0 0 {name=C1 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} 170 -400 1 0 {name=R1 +value=200k +footprint=1206 +device=resistor +m=1} +C {res.sym} -280 -240 1 0 {name=R3 +value=200k +footprint=1206 +device=resistor +m=1} +C {capa.sym} -70 -160 1 0 {name=C2 +m=1 +value=10p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} -230 -310 0 0 {name=l18 sig_type=std_logic lab=feedback_p} +C {lab_wire.sym} 360 -210 0 0 {name=l19 sig_type=std_logic lab=vcmp_p} +C {lab_wire.sym} 300 -250 0 0 {name=l21 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 170 -230 0 0 {name=l8 sig_type=std_logic lab=error_p} +C {lab_wire.sym} 20 120 0 0 {name=l24 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -70 140 0 0 {name=l27 sig_type=std_logic lab=vref} +C {res.sym} 190 410 1 0 {name=R4 +value=200k +footprint=1206 +device=resistor +m=1} +C {res.sym} -280 160 1 0 {name=R5 +value=200k +footprint=1206 +device=resistor +m=1} +C {capa.sym} 0 280 1 0 {name=C3 +m=1 +value=10p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} 290 150 0 0 {name=l38 sig_type=std_logic lab=vdd} +C {ind.sym} 1140 200 3 1 {name=L2 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 1200 230 0 1 {name=C4 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} 1260 40 2 0 {name=R6 +value=8 +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 180 170 0 0 {name=l29 sig_type=std_logic lab=error_n} +C {lab_wire.sym} -220 240 0 0 {name=l30 sig_type=std_logic lab=feedback_n} +C {lab_wire.sym} 350 190 0 1 {name=l40 sig_type=std_logic lab=vcmp_n} +C {lab_wire.sym} 1210 -210 0 1 {name=l43 sig_type=std_logic lab=audio_p} +C {lab_wire.sym} 1210 200 0 1 {name=l44 sig_type=std_logic lab=audio_n} +C {vsource.sym} -1070 160 0 0 {name=V4 value="pulse(0 1.8 0 10n 10n 10 20)"} +C {lab_wire.sym} -1070 110 0 0 {name=l16 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 500 -270 0 0 {name=l17 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 500 130 0 0 {name=l34 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 650 180 0 0 {name=l51 sig_type=std_logic lab=vn_p} +C {lab_wire.sym} 660 200 0 0 {name=l52 sig_type=std_logic lab=vn_n} +C {lab_wire.sym} -670 -60 0 0 {name=l36 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} -670 0 0 0 {name=l56 sig_type=std_logic lab=vref} +C {lab_wire.sym} -540 -80 0 0 {name=l57 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -50 -220 0 0 {name=l3 sig_type=std_logic lab=vbias5} +C {lab_wire.sym} -60 180 0 0 {name=l14 sig_type=std_logic lab=vbias6} +C {lab_wire.sym} 220 -190 0 0 {name=l20 sig_type=std_logic lab=vbias7} +C {lab_wire.sym} -190 -60 0 0 {name=l45 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} -190 -40 0 0 {name=l46 sig_type=std_logic lab=vref} +C {lab_wire.sym} -30 -40 0 1 {name=l60 sig_type=std_logic lab=vsquare} +C {lab_wire.sym} 210 210 0 0 {name=l61 sig_type=std_logic lab=vbias8} +C {gnd.sym} -1070 220 0 0 {name=l63 lab=GND} +C {gnd.sym} -1160 230 0 0 {name=l2 lab=GND} +C {gnd.sym} -860 60 0 0 {name=l4 lab=GND} +C {gnd.sym} -540 30 0 0 {name=l5 lab=GND} +C {gnd.sym} -110 -10 0 0 {name=l11 lab=GND} +C {gnd.sym} 20 -180 0 0 {name=l12 lab=GND} +C {gnd.sym} 300 -160 0 0 {name=l13 lab=GND} +C {gnd.sym} 500 -150 0 0 {name=l22 lab=GND} +C {gnd.sym} 500 250 0 0 {name=l41 lab=GND} +C {gnd.sym} 290 240 0 0 {name=l42 lab=GND} +C {gnd.sym} 20 220 0 0 {name=l48 lab=GND} +C {gnd.sym} 1200 280 0 0 {name=l55 lab=GND} +C {gnd.sym} 1200 -120 0 0 {name=l58 lab=GND} +C {isource.sym} -710 320 0 0 {name=I0 value=15u} +C {lab_wire.sym} -710 270 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} -710 500 0 0 {name=l10 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -690 460 0 1 {name=M5 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -590 480 3 1 {name=M6 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} -660 380 0 1 {name=l62 sig_type=std_logic lab=v1} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -500 480 1 0 {name=M7 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -410 480 3 1 {name=M8 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -320 480 1 0 {name=M9 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -240 480 3 1 {name=M10 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -150 480 1 0 {name=M11 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} -540 530 0 0 {name=l54 lab=GND} +C {gnd.sym} -360 530 0 0 {name=l59 lab=GND} +C {gnd.sym} -200 530 0 0 {name=l64 lab=GND} +C {gnd.sym} -30 530 0 0 {name=l65 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -70 480 1 0 {name=M12 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 10 480 1 0 {name=M13 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} -190 -80 0 0 {name=l32 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} -670 -40 0 0 {name=l35 sig_type=std_logic lab=vbias4} +C {lab_wire.sym} -620 540 0 0 {name=l39 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} -470 550 0 0 {name=l66 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} -440 550 0 1 {name=l67 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} -290 550 0 0 {name=l68 sig_type=std_logic lab=vbias4} +C {lab_wire.sym} -270 550 0 1 {name=l69 sig_type=std_logic lab=vbias5} +C {lab_wire.sym} -120 540 0 0 {name=l70 sig_type=std_logic lab=vbias6} +C {lab_wire.sym} -100 550 0 1 {name=l71 sig_type=std_logic lab=vbias7} +C {lab_wire.sym} 40 540 0 1 {name=l72 sig_type=std_logic lab=vbias8} +C {vsource.sym} -310 -70 0 0 {name=V2 value=1.8} +C {gnd.sym} -310 -20 0 0 {name=l47 lab=GND} +C {src/S_to_D/S_to_D_post.sym} -520 -10 0 0 {name=x1} +C {lab_wire.sym} -370 160 0 1 {name=l23 sig_type=std_logic lab=vin_n} +C {src/triangle/triangle_post.sym} -100 -60 0 0 {name=x7} +C {src/comparator/comparator_post.sym} 250 -230 0 0 {name=x4} +C {src/comparator/comparator_post.sym} 240 170 0 0 {name=x5} +C {src/dead_time/dead_time_post.sym} 430 -230 0 0 {name=x2} +C {src/dead_time/dead_time_post.sym} 430 170 0 0 {name=x8} +C {src/output_driver/output_driver_post.sym} 860 10 0 0 {name=x9} +C {lab_wire.sym} 670 -220 0 1 {name=l15 sig_type=std_logic lab=vp_p} +C {lab_wire.sym} 650 -170 0 1 {name=l25 sig_type=std_logic lab=vp_n} +C {vsource.sym} 750 -210 0 0 {name=V3 value=1.8} +C {gnd.sym} 750 -130 0 0 {name=l28 lab=GND} +C {gnd.sym} 840 90 0 0 {name=l31 lab=GND} +C {lab_wire.sym} 1040 -210 0 1 {name=l33 sig_type=std_logic lab=out_p} +C {lab_wire.sym} 1050 200 0 1 {name=l37 sig_type=std_logic lab=out_n} +C {src/OTA_int/OTA_int_post.sym} 0 -230 0 0 {name=x3} +C {src/OTA_int/OTA_int_post.sym} 0 170 0 0 {name=x6}
diff --git a/xschem/src/Class_D/Class_D_tb2.sch b/xschem/src/Class_D/Class_D_tb2.sch new file mode 100644 index 0000000..dba9e59 --- /dev/null +++ b/xschem/src/Class_D/Class_D_tb2.sch
@@ -0,0 +1,146 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -460 -60 -460 -30 { lab=vref} +N -460 30 -460 70 { lab=GND} +N -340 30 -340 50 { lab=GND} +N -400 30 -400 60 { lab=GND} +N -380 -160 -380 -130 { lab=GND} +N 350 -250 430 -250 { lab=audio_p} +N 370 -250 370 -240 { lab=audio_p} +N 370 -180 370 -160 { lab=GND} +N 370 -10 370 10 { lab=GND} +N 340 -70 370 -70 { lab=audio_n} +N 430 -200 430 -190 { lab=audio_p} +N 370 -70 430 -70 { lab=audio_n} +N 430 -130 430 -70 { lab=audio_n} +N 430 -250 430 -200 { lab=audio_p} +N -400 -60 -400 -30 { lab=avdd} +N -340 -60 -340 -30 { lab=dvdd} +N -380 -220 -270 -220 { lab=#net1} +N 30 -220 110 -220 { lab=out_p} +N 110 -250 110 -220 { lab=out_p} +N 110 -250 220 -250 { lab=out_p} +N 30 -120 110 -120 { lab=out_n} +N 110 -120 110 -70 { lab=out_n} +N 110 -70 210 -70 { lab=out_n} +N -320 -200 -270 -200 { lab=vref} +N 30 -140 110 -140 { lab=dvdd} +N 30 -200 110 -200 { lab=avdd} +N 30 -180 110 -180 { lab=GND} +N 30 -160 150 -160 { lab=#net2} +N 280 -160 320 -160 { lab=avdd} +N 220 -250 290 -250 { lab=out_p} +N 150 -160 220 -160 { lab=#net2} +N 210 -70 280 -70 { lab=out_n} +C {gnd.sym} -460 70 0 0 {name=l2 lab=GND} +C {netlist_not_shown.sym} 1240 -610 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/Class_D/Class_D_post.spice + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {vsource.sym} -460 0 0 0 {name=V5 value=0.9} +C {vsource.sym} -340 0 0 0 {name=V1 value=1.8} +C {gnd.sym} -340 50 0 0 {name=l4 lab=GND} +C {vsource.sym} -400 0 0 0 {name=V2 value="pulse(0 1.8 0 1u 1u 1 2)"} +C {gnd.sym} -400 60 0 0 {name=l6 lab=GND} +C {lab_wire.sym} -460 -40 0 0 {name=l5 sig_type=std_logic lab=vref} +C {lab_wire.sym} -340 -40 0 0 {name=l7 sig_type=std_logic lab=dvdd} +C {lab_wire.sym} -400 -40 0 0 {name=l8 sig_type=std_logic lab=avdd} +C {vsource.sym} -380 -190 0 0 {name=V3 value="sin(0.9 0.4 5k)"} +C {gnd.sym} -380 -130 0 0 {name=l10 lab=GND} +C {ind.sym} 320 -250 1 0 {name=L1 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 370 -210 0 0 {name=C1 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {ind.sym} 310 -70 3 1 {name=L2 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 370 -40 0 1 {name=C4 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} 430 -160 2 0 {name=R6 +value=8 +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 380 -250 0 1 {name=l43 sig_type=std_logic lab=audio_p} +C {lab_wire.sym} 380 -70 0 1 {name=l44 sig_type=std_logic lab=audio_n} +C {gnd.sym} 370 10 0 0 {name=l55 lab=GND} +C {gnd.sym} 370 -160 0 0 {name=l58 lab=GND} +C {code_shown.sym} -860 -840 0 0 {name=s2 only_toplevel=false value=" +.option rshunt=1e20 +.nodeset all=0.7 +*.option VNTOL=1e-6 ABSTOL=1e-9 +*.option savecurrents +*set the absolute voltage error tolerance and absolute current error tolerance +.control +save out_p out_n audio_p audio_n I(V1) I(V2) @r6[i] x1.vtriang x1.vin_p x1.vin_n x1.vcmp_p x1.vcmp_n x1.vp_p x1.vp_n x1.vn_p x1.vn_n x1.iin_15u_f x1.fgnd +*save all +*save vtriang audio_p audio_n I(V2) @r6[i] out_p out_n +*op +tran 1n 5m +*linearize V(audio) +*linearize V(out) +*fft V(out) +*fft V(audio) +*plot mag(V(audio)) +*plot mag(V(out)) +let pout=(V(audio_p)-V(audio_n))*(V(audio_p)-V(audio_n))/@r6[i] +let pin=1.8*(I(V2)+I(V1)) +meas tran pload avg pout from=1m to=5m +meas tran p_supply avg pin from=1m to=5m +*print pload/p_supply +set nfreqs=5 +*fourier 10k V(out_p)-V(out_n) + +fourier 5k V(audio_p)-V(audio_n) +write class_d_5k_04_presim_withesd.raw + +.endc + + +"} +C {lab_wire.sym} 190 -70 0 1 {name=l20 sig_type=std_logic lab=out_n} +C {src/Class_D/Class_D_bondwire.sym} -120 -170 0 0 {name=x1} +C {lab_wire.sym} 160 -250 0 1 {name=l1 sig_type=std_logic lab=out_p} +C {lab_wire.sym} -290 -200 0 0 {name=l3 sig_type=std_logic lab=vref} +C {lab_wire.sym} 90 -140 0 0 {name=l9 sig_type=std_logic lab=dvdd} +C {lab_wire.sym} 100 -200 0 0 {name=l11 sig_type=std_logic lab=avdd} +C {gnd.sym} 110 -180 0 0 {name=l12 lab=GND} +C {res.sym} 250 -160 3 0 {name=R1 +value=83k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 300 -160 0 1 {name=l13 sig_type=std_logic lab=avdd} +C {capa.sym} 180 -130 0 1 {name=C2 +m=1 +value=50n +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 180 -100 0 0 {name=l14 lab=GND}
diff --git a/xschem/src/ESD/ESD.sch b/xschem/src/ESD/ESD.sch new file mode 100644 index 0000000..1289205 --- /dev/null +++ b/xschem/src/ESD/ESD.sch
@@ -0,0 +1,23 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 150 -30 150 0 { lab=vin} +N 150 -90 300 -90 { lab=vdd} +N 150 0 150 20 { lab=vin} +N 150 80 150 100 { lab=vss} +N 150 -0 190 -0 { lab=vin} +C {sky130_fd_pr/diode.sym} 150 -60 0 0 {name=D17 +model=diode_pd2nw_05v5 +area=22500 +} +C {sky130_fd_pr/diode.sym} 150 50 0 0 {name=D1 +model=diode_pw2nd_05v5 +area=22500 +} +C {lab_wire.sym} 270 -90 0 1 {name=l1 sig_type=std_logic lab=vdd} +C {iopin.sym} 300 -90 0 0 {name=p1 lab=vdd} +C {iopin.sym} 190 0 0 0 {name=p2 lab=vin} +C {iopin.sym} 150 100 0 0 {name=p3 lab=vss}
diff --git a/xschem/src/ESD/ESD.sym b/xschem/src/ESD/ESD.sym new file mode 100644 index 0000000..46bf5eb --- /dev/null +++ b/xschem/src/ESD/ESD.sym
@@ -0,0 +1,22 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -30 -130 30 {} +L 4 30 -30 30 30 {} +L 4 -130 -30 30 -30 {} +L 4 -130 30 30 30 {} +L 7 30 0 50 0 {} +B 5 -52.5 -32.5 -47.5 -27.5 {name=vdd dir=inout } +B 5 47.5 -2.5 52.5 2.5 {name=vin dir=inout } +B 5 -52.5 27.5 -47.5 32.5 {name=vss dir=inout } +T {@symname} -101.5 -6 0 0 0.3 0.3 {} +T {@name} 35 -42 0 0 0.2 0.2 {} +T {vdd} -45 -24 0 1 0.2 0.2 {} +T {vin} 25 -4 0 1 0.2 0.2 {} +T {vss} -45 16 0 1 0.2 0.2 {}
diff --git a/xschem/src/ESD/io_clamp.sch b/xschem/src/ESD/io_clamp.sch new file mode 100644 index 0000000..27a6eb8 --- /dev/null +++ b/xschem/src/ESD/io_clamp.sch
@@ -0,0 +1,29 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -160 -30 -70 -30 { lab=vdd} +N -160 280 -70 280 { lab=vss} +N -160 30 -160 60 { lab=#net1} +N -160 210 -160 220 { lab=#net2} +N -160 120 -160 150 { lab=#net3} +C {iopin.sym} -70 -30 0 0 {name=p1 lab=vdd} +C {iopin.sym} -70 280 0 0 {name=p2 lab=vss} +C {sky130_fd_pr/diode.sym} -160 180 2 0 {name=D4 +model=diode_pd2nw_05v5 +area=22500 +} +C {sky130_fd_pr/diode.sym} -160 90 2 0 {name=D1 +model=diode_pd2nw_05v5 +area=22500 +} +C {sky130_fd_pr/diode.sym} -160 0 2 0 {name=D2 +model=diode_pd2nw_05v5 +area=22500 +} +C {sky130_fd_pr/diode.sym} -160 250 2 0 {name=D3 +model=diode_pd2nw_05v5 +area=22500 +}
diff --git a/xschem/src/ESD/io_clamp.sym b/xschem/src/ESD/io_clamp.sym new file mode 100644 index 0000000..2ffe3c7 --- /dev/null +++ b/xschem/src/ESD/io_clamp.sym
@@ -0,0 +1,17 @@ +v {xschem version=2.9.9 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +T {@symname} -54 -6 0 0 0.3 0.3 {} +T {@name} 135 -32 0 0 0.2 0.2 {} +L 4 -130 -20 130 -20 {} +L 4 -130 20 130 20 {} +L 4 -130 -20 -130 20 {} +L 4 130 -20 130 20 {} +B 5 147.5 -12.5 152.5 -7.5 {name=vdd dir=inout } +L 7 130 -10 150 -10 {} +T {vdd} 125 -14 0 1 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=vss dir=inout } +L 7 130 10 150 10 {} +T {vss} 125 6 0 1 0.2 0.2 {}
diff --git a/xschem/src/OTA/OTA.sch b/xschem/src/OTA/OTA.sch new file mode 100644 index 0000000..02d4fcd --- /dev/null +++ b/xschem/src/OTA/OTA.sch
@@ -0,0 +1,212 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +T {0.386p} 320 60 0 0 0.2 0.2 {} +T {gm/id=11} -160 -20 0 0 0.2 0.2 {} +T {gm/id=11} 20 -20 0 0 0.2 0.2 {} +T {gm/id=11} 360 -20 0 0 0.2 0.2 {} +T {gm/id=15} 10 80 0 0 0.2 0.2 {} +T {gm/id=15} 110 80 0 0 0.2 0.2 {} +T {gm/id=17} 30 220 0 0 0.2 0.2 {} +T {gm/id=17} 90 220 0 0 0.2 0.2 {} +T {gm/id=17} 360 170 0 0 0.2 0.2 {} +T {32k} 220 90 0 0 0.2 0.2 {} +N -320 50 -250 50 { lab=vn} +N -330 90 -250 90 { lab=vbias} +N -330 50 -320 50 { lab=vn} +N -330 10 -310 10 { lab=vp} +N -310 10 -250 10 { lab=vp} +N -320 -20 -250 -20 { lab=vdd} +N -310 120 -250 120 { lab=vss} +N -320 120 -310 120 { lab=vss} +N -170 -20 -170 60 { lab=vbias} +N -170 240 170 240 { lab=vss} +N 0 210 0 240 { lab=vss} +N 170 210 170 240 { lab=vss} +N 0 90 0 180 { lab=vf} +N 170 90 170 180 { lab=v1} +N 0 30 170 30 { lab=vc} +N 90 -20 90 30 { lab=vc} +N 40 210 130 210 { lab=vf} +N 0 160 80 160 { lab=vf} +N 80 160 80 210 { lab=vf} +N -170 10 -100 10 { lab=vbias} +N -100 -50 -100 10 { lab=vbias} +N -130 -50 50 -50 { lab=vbias} +N 420 -20 420 100 { lab=vout} +N 420 -50 430 -50 { lab=vdd} +N 430 -80 430 -50 { lab=vdd} +N 420 160 420 240 { lab=vss} +N 170 240 320 240 { lab=vss} +N 420 130 450 130 { lab=vss} +N 450 130 450 160 { lab=vss} +N 420 160 450 160 { lab=vss} +N -170 -80 330 -80 { lab=vdd} +N 90 -80 90 -50 { lab=vdd} +N -170 -80 -170 -50 { lab=vdd} +N 350 -50 380 -50 { lab=vbias} +N 380 130 380 160 { lab=v1} +N 170 160 280 160 { lab=v1} +N -60 60 -40 60 { lab=vn} +N 210 60 230 60 { lab=vp} +N 380 240 420 240 { lab=vss} +N 350 160 380 160 { lab=v1} +N 330 -80 400 -80 { lab=vdd} +N 320 240 380 240 { lab=vss} +N 400 -80 420 -80 { lab=vdd} +N 420 -80 430 -80 { lab=vdd} +N 240 80 240 90 { lab=#net1} +N 260 80 280 80 { lab=#net1} +N 240 150 240 160 { lab=v1} +N 240 80 260 80 { lab=#net1} +N 280 80 300 80 { lab=#net1} +N 360 80 420 80 { lab=vout} +N 280 160 350 160 { lab=v1} +N 420 50 460 50 { lab=vout} +N 190 120 220 120 { lab=vss} +N 0 30 -0 60 { lab=vc} +N 170 30 170 60 { lab=vc} +C {ipin.sym} -320 10 0 0 {name=p3 lab=vp} +C {ipin.sym} -320 50 0 0 {name=p4 lab=vn} +C {ipin.sym} -320 90 0 0 {name=p6 lab=vbias} +C {lab_wire.sym} -260 90 0 0 {name=l5 sig_type=std_logic lab=vbias} +C {iopin.sym} -320 120 0 1 {name=p2 lab=vss} +C {lab_wire.sym} -270 10 0 0 {name=l3 sig_type=std_logic lab=vp} +C {lab_wire.sym} -280 50 0 1 {name=l7 sig_type=std_logic lab=vn} +C {lab_wire.sym} -260 -20 0 1 {name=l10 sig_type=std_logic lab=vdd} +C {iopin.sym} -320 -20 0 1 {name=p7 lab=vdd} +C {lab_wire.sym} -270 120 0 0 {name=l11 sig_type=std_logic lab=vss} +C {opin.sym} 460 50 0 0 {name=p1 lab=vout} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 190 60 0 1 {name=M1 +L=1 +W=4 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} -20 60 0 0 {name=M2 +L=1 +W=4 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 70 -50 0 0 {name=M3 +L=1 +W=2 +nf=2 +mult=24 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 150 210 0 0 {name=M4 +L=1 +W=1 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 20 210 0 1 {name=M5 +L=1 +W=1 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} -150 -50 0 1 {name=M6 +L=1 +W=2 +nf=2 +mult=24 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 400 -50 0 0 {name=M7 +L=1 +W=2 +nf=2 +mult=48 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 400 130 0 0 {name=M8 +L=1 +W=1 +nf=1 +mult=64 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} -50 -50 0 0 {name=l1 sig_type=std_logic lab=vbias} +C {lab_wire.sym} -60 -80 0 0 {name=l8 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 340 160 0 0 {name=l13 sig_type=std_logic lab=v1} +C {lab_wire.sym} 130 30 0 0 {name=l14 sig_type=std_logic lab=vc} +C {lab_wire.sym} 420 70 0 0 {name=l15 sig_type=std_logic lab=vout} +C {lab_wire.sym} 60 160 0 0 {name=l16 sig_type=std_logic lab=vf} +C {lab_wire.sym} 230 60 0 0 {name=l12 sig_type=std_logic lab=vp} +C {lab_wire.sym} 370 -50 0 0 {name=l4 sig_type=std_logic lab=vbias} +C {lab_wire.sym} -50 60 0 0 {name=l17 sig_type=std_logic lab=vn} +C {lab_wire.sym} -140 240 0 0 {name=l9 sig_type=std_logic lab=vss} +C {lab_wire.sym} 200 120 0 0 {name=l18 sig_type=std_logic lab=vss} +C {sky130_fd_pr/res_xhigh_po.sym} 240 120 0 0 {name=R1 +W=0.35 +L=0.5 +model=res_xhigh_po +spiceprefix=X +mult=1} +C {sky130_fd_pr/cap_mim_m3_1.sym} 330 80 3 0 {name=C2 model=cap_mim_m3_1 W=14 L=14 MF=1 spiceprefix=X}
diff --git a/xschem/src/OTA/OTA.sym b/xschem/src/OTA/OTA.sym new file mode 100644 index 0000000..f3104ef --- /dev/null +++ b/xschem/src/OTA/OTA.sym
@@ -0,0 +1,24 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -90 60 -90 140 {} +L 4 -90 140 20 100 {} +L 4 -90 60 20 100 {} +B 5 -32.5 77.5 -27.5 82.5 {name=vdd dir=inout } +B 5 -92.5 77.5 -87.5 82.5 {name=vp dir=in } +B 5 -92.5 97.5 -87.5 102.5 {name=vn dir=in } +B 5 -92.5 117.5 -87.5 122.5 {name=vbias dir=in } +B 5 -32.5 117.5 -27.5 122.5 {name=vss dir=inout } +B 5 17.5 97.5 22.5 102.5 {name=vout dir=out } +T {@symname} -61.5 94 0 0 0.2 0.2 {} +T {@name} -5 68 0 0 0.2 0.2 {} +T {vdd} -35 86 0 1 0.2 0.2 {} +T {vp} -85 76 0 0 0.2 0.2 {} +T {vn} -85 96 0 0 0.2 0.2 {} +T {vbias} -85 116 0 0 0.2 0.2 {}
diff --git a/xschem/src/OTA/OTA_post.sym b/xschem/src/OTA/OTA_post.sym new file mode 100644 index 0000000..832c212 --- /dev/null +++ b/xschem/src/OTA/OTA_post.sym
@@ -0,0 +1,24 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -70 70 -70 150 {} +L 4 -70 150 40 110 {} +L 4 -70 70 40 110 {} +B 5 -12.5 87.5 -7.5 92.5 {name=vdd dir=inout } +B 5 -72.5 87.5 -67.5 92.5 {name=vp dir=in } +B 5 -72.5 107.5 -67.5 112.5 {name=vn dir=in } +B 5 -72.5 127.5 -67.5 132.5 {name=vbias dir=in } +B 5 -12.5 127.5 -7.5 132.5 {name=vss dir=inout } +B 5 37.5 107.5 42.5 112.5 {name=vout dir=out } +T {@symname} -41.5 104 0 0 0.2 0.2 {} +T {@name} 15 78 0 0 0.2 0.2 {} +T {vdd} -15 96 0 1 0.2 0.2 {} +T {vp} -65 86 0 0 0.2 0.2 {} +T {vn} -65 106 0 0 0.2 0.2 {} +T {vbias} -65 126 0 0 0.2 0.2 {}
diff --git a/xschem/src/OTA/OTA_revised_post.sym b/xschem/src/OTA/OTA_revised_post.sym new file mode 100644 index 0000000..d4a7b37 --- /dev/null +++ b/xschem/src/OTA/OTA_revised_post.sym
@@ -0,0 +1,24 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 50 -30 50 50 {} +L 4 50 50 160 10 {} +L 4 50 -30 160 10 {} +B 5 107.5 -12.5 112.5 -7.5 {name=vdd dir=inout } +B 5 47.5 -12.5 52.5 -7.5 {name=vp dir=in } +B 5 47.5 7.5 52.5 12.5 {name=vn dir=in } +B 5 47.5 27.5 52.5 32.5 {name=vbias dir=in } +B 5 107.5 27.5 112.5 32.5 {name=vss dir=inout } +B 5 157.5 7.5 162.5 12.5 {name=vout dir=out } +T {@symname} 78.5 4 0 0 0.2 0.2 {} +T {@name} 135 -22 0 0 0.2 0.2 {} +T {vdd} 105 -4 0 1 0.2 0.2 {} +T {vp} 55 -14 0 0 0.2 0.2 {} +T {vn} 55 6 0 0 0.2 0.2 {} +T {vbias} 55 26 0 0 0.2 0.2 {}
diff --git a/xschem/src/OTA/OTA_tb.sch b/xschem/src/OTA/OTA_tb.sch new file mode 100644 index 0000000..1e24af9 --- /dev/null +++ b/xschem/src/OTA/OTA_tb.sch
@@ -0,0 +1,251 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -50 -50 -50 -30 { lab=vdd} +N -50 -50 -30 -50 { lab=vdd} +N -120 -60 -120 -30 { lab=vp} +N -50 30 -50 60 { lab=GND} +N -120 30 -120 50 { lab=GND} +N -330 100 -330 180 { lab=#net1} +N -330 130 -260 130 { lab=#net1} +N -330 20 -330 40 { lab=vdd} +N -330 240 -330 250 { lab=GND} +N -330 210 -330 240 { lab=GND} +N -290 210 -250 210 { lab=#net1} +N -260 130 -260 210 { lab=#net1} +N -250 210 -210 210 { lab=#net1} +N -160 250 -160 280 { lab=GND} +N -260 250 -240 250 { lab=vbias1} +N -260 250 -260 330 { lab=vbias1} +N -210 250 -180 250 { lab=GND} +N -180 250 -160 250 { lab=GND} +N 30 140 30 150 { lab=GND} +N 30 50 30 80 { lab=vn} +N 410 290 410 300 { lab=vout2} +N 390 290 410 290 { lab=vout2} +N 340 230 340 270 { lab=vdd} +N 340 310 340 340 { lab=GND} +N 250 270 280 270 { lab=vp} +N 250 290 280 290 { lab=#net2} +N 250 310 280 310 { lab=vbias2} +N 220 290 250 290 { lab=#net2} +N 160 290 220 290 { lab=#net2} +N 410 300 410 390 { lab=vout2} +N 390 390 410 390 { lab=vout2} +N 180 370 180 380 { lab=vp} +N 180 290 180 310 { lab=#net2} +N 70 290 100 290 { lab=vn} +N 410 10 410 20 { lab=vout1} +N 390 10 410 10 { lab=vout1} +N 340 -50 340 -10 { lab=vdd} +N 340 30 340 60 { lab=GND} +N 250 -10 280 -10 { lab=vp} +N 250 10 280 10 { lab=#net3} +N 250 30 280 30 { lab=vbias1} +N 220 10 250 10 { lab=#net3} +N 160 10 220 10 { lab=#net3} +N 410 20 410 110 { lab=vout1} +N 390 110 410 110 { lab=vout1} +N 70 10 100 10 { lab=vn} +N 430 610 430 620 { lab=vout3} +N 410 610 430 610 { lab=vout3} +N 360 550 360 590 { lab=vdd} +N 360 630 360 660 { lab=GND} +N 270 590 300 590 { lab=vp} +N 270 610 300 610 { lab=#net4} +N 270 630 300 630 { lab=vbias3} +N 240 610 270 610 { lab=#net4} +N 180 610 240 610 { lab=#net4} +N 430 620 430 710 { lab=vout3} +N 410 710 430 710 { lab=vout3} +N 200 610 200 630 { lab=#net4} +N 90 610 120 610 { lab=vn} +N 370 710 410 710 { lab=vout3} +N 200 710 310 710 { lab=#net4} +N 200 630 200 710 { lab=#net4} +N -210 210 -30 210 { lab=#net1} +N -160 250 -120 250 { lab=GND} +N -90 250 -90 320 { lab=vbias2} +N -60 250 -60 320 { lab=vbias3} +N -30 250 10 250 { lab=GND} +C {isource.sym} -330 70 0 0 {name=I0 value=15u} +C {vsource.sym} -120 0 0 0 {name=V1 value="dc 0.9"} +C {vsource.sym} -50 0 0 0 {name=V3 value=1.8} +C {lab_wire.sym} -30 -50 0 0 {name=l7 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -120 -50 0 0 {name=l10 sig_type=std_logic lab=vp} +C {code_shown.sym} 810 -200 0 0 {name=s1 only_toplevel=false value=" + +.control + +save all +op +*tran 10n 500u +*plot @m.xm7.msky130_fd_pr__pfet_01v8_lvt[id] +*plot @m.xm8.msky130_fd_pr__nfet_01v8_lvt[id] +*dc V2 0 1.8 0.01 +*print @m.xm2.msky130_fd_pr__pfet_01v8_lvt[gm] +*print @m.xm5.msky130_fd_pr__nfet_01v8_lvt[gm] +*print @m.xm3.msky130_fd_pr__pfet_01v8_lvt[gm] +*print vbias +ac dec 10000 0.1 100G +meas ac GBW when vdb(vout)=0 +meas ac DC_Gain find vdb(vout) at=1000 +meas ac PM find vp(vout2) when vdb(vout2)=0 +print PM*180/PI +plot vdb(vout1)-20*log10(1+vout2) vdb(vout3) +plot vdb(vout2) vp(vout2)*180/pi + + +.endc +"} +C {netlist_not_shown.sym} -180 -210 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {gnd.sym} -120 50 0 0 {name=l9 lab=GND} +C {gnd.sym} -50 60 0 0 {name=l3 lab=GND} +C {lab_wire.sym} -330 20 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} -330 250 0 0 {name=l18 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -310 210 0 1 {name=M9 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -210 230 3 1 {name=M10 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} -160 280 0 0 {name=l54 lab=GND} +C {lab_wire.sym} -260 330 0 0 {name=l19 sig_type=std_logic lab=vbias1} +C {gnd.sym} 30 150 0 0 {name=l20 lab=GND} +C {lab_wire.sym} 30 60 0 0 {name=l22 sig_type=std_logic lab=vn} +C {gnd.sym} 340 340 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 340 250 0 0 {name=l2 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 260 270 0 0 {name=l4 sig_type=std_logic lab=vp} +C {lab_wire.sym} 260 310 0 0 {name=l6 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 410 290 0 1 {name=l8 sig_type=std_logic lab=vout2} +C {res.sym} 180 340 2 0 {name=R1 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 80 290 0 0 {name=l11 sig_type=std_logic lab=vn} +C {capa.sym} 390 420 0 0 {name=C1 +m=1 +value=3.6p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 390 450 0 0 {name=l5 lab=GND} +C {capa.sym} 130 290 1 0 {name=C2 +m=1 +value=3.6p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} 180 380 0 0 {name=l12 sig_type=std_logic lab=vp} +C {vsource.sym} 30 110 0 0 {name=V2 value="dc 0.9 ac 1"} +C {gnd.sym} 340 60 0 0 {name=l14 lab=GND} +C {lab_wire.sym} 340 -30 0 0 {name=l15 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 260 -10 0 0 {name=l16 sig_type=std_logic lab=vp} +C {lab_wire.sym} 260 30 0 0 {name=l17 sig_type=std_logic lab=vbias1} +C {src/OTA_int/OTA_int.sym} 340 30 0 0 {name=x2} +C {lab_wire.sym} 410 10 0 1 {name=l21 sig_type=std_logic lab=vout1} +C {res.sym} 130 10 3 0 {name=R2 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 80 10 0 0 {name=l23 sig_type=std_logic lab=vn} +C {capa.sym} 390 140 0 0 {name=C3 +m=1 +value=10p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 390 170 0 0 {name=l24 lab=GND} +C {capa.sym} 180 -20 2 0 {name=C5 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 180 -50 2 0 {name=l27 lab=GND} +C {gnd.sym} 360 660 0 0 {name=l13 lab=GND} +C {lab_wire.sym} 360 570 0 0 {name=l25 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 280 590 0 0 {name=l26 sig_type=std_logic lab=vp} +C {lab_wire.sym} 280 630 0 0 {name=l28 sig_type=std_logic lab=vbias3} +C {src/OTA_int/OTA_int.sym} 360 630 0 0 {name=x3} +C {lab_wire.sym} 430 610 0 1 {name=l29 sig_type=std_logic lab=vout3} +C {res.sym} 150 610 3 0 {name=R3 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 100 610 0 0 {name=l30 sig_type=std_logic lab=vn} +C {capa.sym} 340 710 1 0 {name=C4 +m=1 +value=10p +footprint=1206 +device="ceramic capacitor"} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -120 230 1 0 {name=M1 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -30 230 3 1 {name=M2 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} -90 320 0 0 {name=l31 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} -60 320 0 1 {name=l32 sig_type=std_logic lab=vbias3} +C {gnd.sym} 10 250 0 0 {name=l33 lab=GND} +C {src/OTA_int/OTA_int_post.sym} 320 300 0 0 {name=x1}
diff --git a/xschem/src/OTA/OTA_tb2.sch b/xschem/src/OTA/OTA_tb2.sch new file mode 100644 index 0000000..fb8e14c --- /dev/null +++ b/xschem/src/OTA/OTA_tb2.sch
@@ -0,0 +1,122 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -140 -100 -140 -80 { lab=vdd} +N -140 -100 -120 -100 { lab=vdd} +N -250 90 -250 120 { lab=vin} +N 220 -50 220 -30 { lab=vdd} +N 220 10 220 40 { lab=GND} +N 270 -10 300 -10 { lab=vout} +N 90 -10 160 -10 { lab=vin} +N 120 10 160 10 { lab=vbias} +N 140 -30 160 -30 { lab=vref} +N 300 -10 330 -10 { lab=vout} +N -150 90 -150 120 { lab=vref} +N -10 110 -10 190 { lab=#net1} +N -10 140 60 140 { lab=#net1} +N -10 30 -10 50 { lab=vdd} +N -10 250 -10 260 { lab=GND} +N -10 220 -10 250 { lab=GND} +N 30 220 70 220 { lab=#net1} +N 60 140 60 220 { lab=#net1} +N 70 220 110 220 { lab=#net1} +N 160 260 160 290 { lab=GND} +N 150 250 160 250 { lab=GND} +N 160 250 160 260 { lab=GND} +N 150 220 160 220 { lab=GND} +N 160 220 160 250 { lab=GND} +N 150 140 150 190 { lab=vbias} +C {vsource.sym} -140 -50 0 0 {name=V3 value=1.8} +C {gnd.sym} -140 -20 0 0 {name=l6 lab=GND} +C {lab_wire.sym} -120 -100 0 0 {name=l7 sig_type=std_logic lab=vdd} +C {netlist_not_shown.sym} -270 -260 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/ss.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_revised_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_tri_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {vsource.sym} -250 150 0 0 {name=V2 value="dc 0.9 ac 1"} +C {gnd.sym} -250 180 0 0 {name=l9 lab=GND} +C {lab_wire.sym} -250 100 0 0 {name=l11 sig_type=std_logic lab=vin} +C {lab_wire.sym} 220 -50 0 0 {name=l1 sig_type=std_logic lab=vdd} +C {gnd.sym} 220 40 0 0 {name=l2 lab=GND} +C {vsource.sym} -150 150 0 0 {name=V1 value=0.9} +C {gnd.sym} -150 180 0 0 {name=l3 lab=GND} +C {lab_wire.sym} 320 -10 0 1 {name=l15 sig_type=std_logic lab=vout} +C {lab_wire.sym} 100 -10 0 0 {name=l8 sig_type=std_logic lab=vin} +C {lab_wire.sym} -150 100 0 0 {name=l5 sig_type=std_logic lab=vref} +C {lab_wire.sym} 150 -30 0 0 {name=l10 sig_type=std_logic lab=vref} +C {lab_wire.sym} 130 10 0 0 {name=l12 sig_type=std_logic lab=vbias} +C {isource.sym} -10 80 0 0 {name=I0 value=15u} +C {lab_wire.sym} -10 30 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} -10 260 0 0 {name=l18 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 10 220 0 1 {name=M9 +L=2 +W=32 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 130 220 0 0 {name=M10 +L=2 +W=32 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} 160 290 0 0 {name=l54 lab=GND} +C {lab_wire.sym} 150 160 0 0 {name=l19 sig_type=std_logic lab=vbias} +C {code_shown.sym} 540 -230 0 0 {name=s2 only_toplevel=false value=" + +.control + +save all +op +*tran 10n 500u +*plot @m.xm7.msky130_fd_pr__pfet_01v8_lvt[id] +*plot @m.xm8.msky130_fd_pr__nfet_01v8_lvt[id] +*dc V2 0 1.8 0.01 +print @m.xm2.msky130_fd_pr__pfet_01v8_lvt[gm] +print @m.xm5.msky130_fd_pr__nfet_01v8_lvt[gm] +print @m.xm3.msky130_fd_pr__pfet_01v8_lvt[gm] +print vbias +ac dec 10000 0.1 100G +meas ac GBW when vdb(vout)=0 +meas ac DC_Gain find vdb(vout) at=1000 +meas ac PM find vp(vout) when vdb(vout)=0 +print PM*180/PI +plot vdb(vout) vp(vout)*180/pi + + +.endc +"} +C {src/OTA/OTA_revised_post.sym} 110 -20 0 0 {name=x1}
diff --git a/xschem/src/OTA_int/OTA_int.sch b/xschem/src/OTA_int/OTA_int.sch new file mode 100644 index 0000000..73ac021 --- /dev/null +++ b/xschem/src/OTA_int/OTA_int.sch
@@ -0,0 +1,217 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +T {1.79p} 470 160 0 0 0.2 0.2 {} +T {gm/id=11} -10 50 0 0 0.2 0.2 {} +T {gm/id=11} 170 50 0 0 0.2 0.2 {} +T {gm/id=11} 510 50 0 0 0.2 0.2 {} +T {gm/id=15} 160 150 0 0 0.2 0.2 {} +T {gm/id=15} 260 150 0 0 0.2 0.2 {} +T {gm/id=17} 180 290 0 0 0.2 0.2 {} +T {gm/id=17} 240 290 0 0 0.2 0.2 {} +T {gm/id=17} 510 240 0 0 0.2 0.2 {} +T {8k} 370 160 0 0 0.2 0.2 {} +N -160 180 -90 180 { lab=vn} +N -170 220 -90 220 { lab=vbias} +N -170 180 -160 180 { lab=vn} +N -170 140 -150 140 { lab=vp} +N -150 140 -90 140 { lab=vp} +N -160 110 -90 110 { lab=vdd} +N -150 250 -90 250 { lab=vss} +N -160 250 -150 250 { lab=vss} +N 600 120 640 120 { lab=vout} +N -20 50 -20 130 { lab=vbias} +N -20 310 320 310 { lab=vss} +N 150 280 150 310 { lab=vss} +N 320 280 320 310 { lab=vss} +N 150 160 150 250 { lab=vf} +N 320 160 320 250 { lab=v1} +N 150 100 320 100 { lab=vc} +N 240 50 240 100 { lab=vc} +N 190 280 280 280 { lab=vf} +N 150 230 230 230 { lab=vf} +N 230 230 230 280 { lab=vf} +N -20 80 50 80 { lab=vbias} +N 50 20 50 80 { lab=vbias} +N 20 20 200 20 { lab=vbias} +N 570 50 570 170 { lab=vout} +N 570 20 580 20 { lab=vdd} +N 580 -10 580 20 { lab=vdd} +N 570 230 570 310 { lab=vss} +N 320 310 470 310 { lab=vss} +N 570 200 600 200 { lab=vss} +N 600 200 600 230 { lab=vss} +N 570 230 600 230 { lab=vss} +N -20 -10 480 -10 { lab=vdd} +N 240 -10 240 20 { lab=vdd} +N -20 -10 -20 20 { lab=vdd} +N 500 20 530 20 { lab=vbias} +N 530 200 530 230 { lab=v1} +N 320 230 430 230 { lab=v1} +N 90 130 110 130 { lab=vn} +N 360 130 380 130 { lab=vp} +N 530 310 570 310 { lab=vss} +N 500 230 530 230 { lab=v1} +N 480 -10 550 -10 { lab=vdd} +N 470 310 530 310 { lab=vss} +N 550 -10 570 -10 { lab=vdd} +N 570 -10 580 -10 { lab=vdd} +N 390 150 390 160 { lab=v2} +N 410 150 430 150 { lab=v2} +N 390 220 390 230 { lab=v1} +N 390 150 410 150 { lab=v2} +N 430 150 450 150 { lab=v2} +N 510 150 570 150 { lab=vout} +N 430 230 500 230 { lab=v1} +N 340 190 370 190 { lab=vss} +N 570 120 600 120 { lab=vout} +N 150 100 150 130 { lab=vc} +N 320 100 320 130 { lab=vc} +N 450 90 450 150 { lab=v2} +N 510 90 510 150 { lab=vout} +C {ipin.sym} -160 140 0 0 {name=p3 lab=vp} +C {ipin.sym} -160 180 0 0 {name=p4 lab=vn} +C {ipin.sym} -160 220 0 0 {name=p6 lab=vbias} +C {lab_wire.sym} -100 220 0 0 {name=l5 sig_type=std_logic lab=vbias} +C {iopin.sym} -160 250 0 1 {name=p2 lab=vss} +C {lab_wire.sym} -110 140 0 0 {name=l7 sig_type=std_logic lab=vp} +C {lab_wire.sym} -120 180 0 1 {name=l9 sig_type=std_logic lab=vn} +C {lab_wire.sym} -100 110 0 1 {name=l10 sig_type=std_logic lab=vdd} +C {iopin.sym} -160 110 0 1 {name=p7 lab=vdd} +C {lab_wire.sym} -110 250 0 0 {name=l18 sig_type=std_logic lab=vss} +C {opin.sym} 640 120 0 0 {name=p1 lab=vout} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 340 130 0 1 {name=M1 +L=1 +W=4 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 130 130 0 0 {name=M2 +L=1 +W=4 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 220 20 0 0 {name=M3 +L=1 +W=2 +nf=2 +mult=24 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 300 280 0 0 {name=M4 +L=1 +W=1 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 170 280 0 1 {name=M5 +L=1 +W=1 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 0 20 0 1 {name=M6 +L=1 +W=2 +nf=2 +mult=24 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 550 20 0 0 {name=M7 +L=1 +W=2 +nf=2 +mult=48 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 550 200 0 0 {name=M8 +L=1 +W=1 +nf=1 +mult=64 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} 100 20 0 0 {name=l1 sig_type=std_logic lab=vbias} +C {lab_wire.sym} 90 -10 0 0 {name=l8 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 490 230 0 0 {name=l13 sig_type=std_logic lab=v1} +C {lab_wire.sym} 280 100 0 0 {name=l14 sig_type=std_logic lab=vc} +C {lab_wire.sym} 570 140 0 0 {name=l15 sig_type=std_logic lab=vout} +C {lab_wire.sym} 210 230 0 0 {name=l16 sig_type=std_logic lab=vf} +C {lab_wire.sym} 380 130 0 0 {name=l12 sig_type=std_logic lab=vp} +C {lab_wire.sym} 520 20 0 0 {name=l4 sig_type=std_logic lab=vbias} +C {lab_wire.sym} 100 130 0 0 {name=l17 sig_type=std_logic lab=vn} +C {lab_wire.sym} 10 310 0 0 {name=l3 sig_type=std_logic lab=vss} +C {lab_wire.sym} 350 190 0 0 {name=l11 sig_type=std_logic lab=vss} +C {sky130_fd_pr/cap_mim_m3_1.sym} 480 150 3 0 {name=C1 model=cap_mim_m3_1 W=14 L=30 MF=1 spiceprefix=X} +C {sky130_fd_pr/res_xhigh_po_0p35.sym} 390 190 0 0 {name=R1 +W=0.35 +L=2.8 +model=res_xhigh_po +spiceprefix=X +mult=1} +C {sky130_fd_pr/cap_mim_m3_1.sym} 480 90 3 0 {name=C2 model=cap_mim_m3_1 W=30 L=14 MF=1 spiceprefix=X} +C {lab_wire.sym} 430 150 0 0 {name=l2 sig_type=std_logic lab=v2}
diff --git a/xschem/src/OTA_int/OTA_int.sym b/xschem/src/OTA_int/OTA_int.sym new file mode 100644 index 0000000..4af3ce5 --- /dev/null +++ b/xschem/src/OTA_int/OTA_int.sym
@@ -0,0 +1,24 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -60 -60 -60 20 {} +L 4 -60 20 50 -20 {} +L 4 -60 -60 50 -20 {} +B 5 -2.5 -42.5 2.5 -37.5 {name=vdd dir=inout } +B 5 -62.5 -42.5 -57.5 -37.5 {name=vp dir=in } +B 5 -62.5 -22.5 -57.5 -17.5 {name=vn dir=in } +B 5 -62.5 -2.5 -57.5 2.5 {name=vbias dir=in } +B 5 -2.5 -2.5 2.5 2.5 {name=vss dir=inout } +B 5 47.5 -22.5 52.5 -17.5 {name=vout dir=out } +T {@symname} -31.5 -26 0 0 0.2 0.2 {} +T {@name} 25 -52 0 0 0.2 0.2 {} +T {vdd} -5 -34 0 1 0.2 0.2 {} +T {vp} -55 -44 0 0 0.2 0.2 {} +T {vn} -55 -24 0 0 0.2 0.2 {} +T {vbias} -55 -4 0 0 0.2 0.2 {}
diff --git a/xschem/src/OTA_int/OTA_int_post.sym b/xschem/src/OTA_int/OTA_int_post.sym new file mode 100644 index 0000000..ddb209b --- /dev/null +++ b/xschem/src/OTA_int/OTA_int_post.sym
@@ -0,0 +1,24 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -40 -50 -40 30 {} +L 4 -40 30 70 -10 {} +L 4 -40 -50 70 -10 {} +B 5 17.5 -32.5 22.5 -27.5 {name=vdd dir=inout } +B 5 -42.5 -32.5 -37.5 -27.5 {name=vp dir=in } +B 5 -42.5 -12.5 -37.5 -7.5 {name=vn dir=in } +B 5 -42.5 7.5 -37.5 12.5 {name=vbias dir=in } +B 5 17.5 7.5 22.5 12.5 {name=vss dir=inout } +B 5 67.5 -12.5 72.5 -7.5 {name=vout dir=out } +T {@symname} -11.5 -16 0 0 0.2 0.2 {} +T {@name} 45 -42 0 0 0.2 0.2 {} +T {vdd} 15 -24 0 1 0.2 0.2 {} +T {vp} -35 -34 0 0 0.2 0.2 {} +T {vn} -35 -14 0 0 0.2 0.2 {} +T {vbias} -35 6 0 0 0.2 0.2 {}
diff --git a/xschem/src/OTA_int/OTA_int_post_tb.sch b/xschem/src/OTA_int/OTA_int_post_tb.sch new file mode 100644 index 0000000..a5d4d2f --- /dev/null +++ b/xschem/src/OTA_int/OTA_int_post_tb.sch
@@ -0,0 +1,258 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 340 -490 340 -470 { lab=vdd} +N 340 -490 360 -490 { lab=vdd} +N 270 -500 270 -470 { lab=vp} +N 340 -410 340 -380 { lab=GND} +N 270 -410 270 -390 { lab=GND} +N -650 -300 -650 -220 { lab=#net1} +N -650 -270 -580 -270 { lab=#net1} +N -650 -380 -650 -360 { lab=vdd} +N -650 -160 -650 -150 { lab=GND} +N -650 -190 -650 -160 { lab=GND} +N -610 -190 -570 -190 { lab=#net1} +N -580 -270 -580 -190 { lab=#net1} +N -570 -190 -530 -190 { lab=#net1} +N -480 -150 -480 -120 { lab=GND} +N -580 -150 -560 -150 { lab=vbias1} +N -580 -150 -580 -70 { lab=vbias1} +N -530 -150 -500 -150 { lab=GND} +N -500 -150 -480 -150 { lab=GND} +N 290 -230 290 -220 { lab=GND} +N 290 -320 290 -290 { lab=vin} +N 90 -50 90 -40 { lab=vout2} +N 70 -50 90 -50 { lab=vout2} +N 20 -110 20 -70 { lab=vdd} +N 20 -30 20 0 { lab=GND} +N -70 -70 -40 -70 { lab=vp} +N -70 -50 -40 -50 { lab=#net2} +N -70 -30 -40 -30 { lab=vbias2} +N -100 -50 -70 -50 { lab=#net2} +N -160 -50 -100 -50 { lab=#net2} +N 90 -40 90 50 { lab=vout2} +N 70 50 90 50 { lab=vout2} +N -140 30 -140 40 { lab=vp} +N -140 -50 -140 -30 { lab=#net2} +N -250 -50 -220 -50 { lab=vin} +N 110 -380 110 -370 { lab=vout1} +N 90 -380 110 -380 { lab=vout1} +N 40 -440 40 -400 { lab=vdd} +N 40 -360 40 -330 { lab=GND} +N -50 -400 -20 -400 { lab=vp} +N -50 -380 -20 -380 { lab=#net3} +N -50 -360 -20 -360 { lab=vbias1} +N -80 -380 -50 -380 { lab=#net3} +N -140 -380 -80 -380 { lab=#net3} +N 110 -370 110 -280 { lab=vout1} +N 90 -280 110 -280 { lab=vout1} +N -230 -380 -200 -380 { lab=vin} +N 110 290 110 300 { lab=vout3} +N 90 290 110 290 { lab=vout3} +N 40 230 40 270 { lab=vdd} +N 40 310 40 340 { lab=GND} +N -50 270 -20 270 { lab=vp} +N -50 290 -20 290 { lab=#net4} +N -50 310 -20 310 { lab=vbias3} +N -80 290 -50 290 { lab=#net4} +N -140 290 -80 290 { lab=#net4} +N 110 300 110 390 { lab=vout3} +N 90 390 110 390 { lab=vout3} +N -120 290 -120 310 { lab=#net4} +N -230 290 -200 290 { lab=vin} +N 50 390 90 390 { lab=vout3} +N -120 390 -10 390 { lab=#net4} +N -120 310 -120 390 { lab=#net4} +N -530 -190 -320 -190 { lab=#net1} +N -480 -150 -450 -150 { lab=GND} +N -450 -150 -420 -150 { lab=GND} +N -350 -150 -350 -90 { lab=GND} +N -390 -150 -380 -150 { lab=vbias2} +N -380 -150 -380 -80 { lab=vbias2} +N -350 -150 -320 -150 { lab=GND} +N -290 -150 -280 -150 { lab=vbias3} +N -280 -150 -280 -110 { lab=vbias3} +C {isource.sym} -650 -330 0 0 {name=I0 value=15u} +C {vsource.sym} 270 -440 0 0 {name=V1 value="dc 0.9"} +C {vsource.sym} 340 -440 0 0 {name=V3 value=1.8} +C {lab_wire.sym} 360 -490 0 0 {name=l7 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 270 -490 0 0 {name=l10 sig_type=std_logic lab=vp} +C {code_shown.sym} 490 -600 0 0 {name=s1 only_toplevel=false value=" + +.control + +save vout2 vout3 vout1 +op +*tran 10n 500u +*plot @m.xm7.msky130_fd_pr__pfet_01v8_lvt[id] +*plot @m.xm8.msky130_fd_pr__nfet_01v8_lvt[id] +*dc V2 0 1.8 0.01 +*print @m.xm2.msky130_fd_pr__pfet_01v8_lvt[gm] +*print @m.xm5.msky130_fd_pr__nfet_01v8_lvt[gm] +*print @m.xm3.msky130_fd_pr__pfet_01v8_lvt[gm] +*print vbias +ac dec 10000 0.1 100G +*meas ac GBW when vdb(vout)=0 +*meas ac DC_Gain find vdb(vout) at=1000 +*meas ac PM find vp(vout2) when vdb(vout2)=0 +*print PM*180/PI +plot vdb(vout1)-20*log10(1+vout2) vdb(vout3) +plot vdb(vout2) vp(vout2)*180/pi + + +.endc +"} +C {netlist_not_shown.sym} -500 -610 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_tri_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_revised_post.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {gnd.sym} 270 -390 0 0 {name=l9 lab=GND} +C {gnd.sym} 340 -380 0 0 {name=l3 lab=GND} +C {lab_wire.sym} -650 -380 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} -650 -150 0 0 {name=l18 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -630 -190 0 1 {name=M9 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -530 -170 3 1 {name=M10 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} -480 -120 0 0 {name=l54 lab=GND} +C {lab_wire.sym} -580 -70 0 0 {name=l19 sig_type=std_logic lab=vbias1} +C {gnd.sym} 290 -220 0 0 {name=l20 lab=GND} +C {lab_wire.sym} 290 -310 0 0 {name=l22 sig_type=std_logic lab=vin} +C {gnd.sym} 20 0 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 20 -90 0 0 {name=l2 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -60 -70 0 0 {name=l4 sig_type=std_logic lab=vp} +C {lab_wire.sym} -60 -30 0 0 {name=l6 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 90 -50 0 1 {name=l8 sig_type=std_logic lab=vout2} +C {res.sym} -140 0 2 0 {name=R1 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} -240 -50 0 0 {name=l11 sig_type=std_logic lab=vin} +C {capa.sym} 70 80 0 0 {name=C1 +m=1 +value=10p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 70 110 0 0 {name=l5 lab=GND} +C {capa.sym} -190 -50 1 0 {name=C2 +m=1 +value=10p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} -140 40 0 0 {name=l12 sig_type=std_logic lab=vp} +C {vsource.sym} 290 -260 0 0 {name=V2 value="dc 0.9 ac 1"} +C {gnd.sym} 40 -330 0 0 {name=l14 lab=GND} +C {lab_wire.sym} 40 -420 0 0 {name=l15 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -40 -400 0 0 {name=l16 sig_type=std_logic lab=vp} +C {lab_wire.sym} -40 -360 0 0 {name=l17 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 110 -380 0 1 {name=l21 sig_type=std_logic lab=vout1} +C {res.sym} -170 -380 3 0 {name=R2 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} -220 -380 0 0 {name=l23 sig_type=std_logic lab=vin} +C {capa.sym} 90 -250 0 0 {name=C3 +m=1 +value=10p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 90 -220 0 0 {name=l24 lab=GND} +C {capa.sym} -120 -410 2 0 {name=C5 +m=1 +value=10p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} -120 -440 2 0 {name=l27 lab=GND} +C {gnd.sym} 40 340 0 0 {name=l13 lab=GND} +C {lab_wire.sym} 40 250 0 0 {name=l25 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -40 270 0 0 {name=l26 sig_type=std_logic lab=vp} +C {lab_wire.sym} -40 310 0 0 {name=l28 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 110 290 0 1 {name=l29 sig_type=std_logic lab=vout3} +C {res.sym} -170 290 3 0 {name=R3 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} -220 290 0 0 {name=l30 sig_type=std_logic lab=vin} +C {capa.sym} 20 390 1 0 {name=C4 +m=1 +value=10p +footprint=1206 +device="ceramic capacitor"} +C {src/OTA_int/OTA_int.sym} 40 -360 0 0 {name=x3} +C {src/OTA_int/OTA_int.sym} 20 -30 0 0 {name=x1} +C {src/OTA_int/OTA_int.sym} 40 310 0 0 {name=x2} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -420 -170 1 0 {name=M1 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -320 -170 1 0 {name=M2 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} -350 -90 0 0 {name=l31 lab=GND} +C {lab_wire.sym} -380 -90 0 0 {name=l32 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} -280 -120 0 1 {name=l33 sig_type=std_logic lab=vbias3}
diff --git a/xschem/src/OTA_int/OTA_int_revised_post.sym b/xschem/src/OTA_int/OTA_int_revised_post.sym new file mode 100644 index 0000000..c1f953d --- /dev/null +++ b/xschem/src/OTA_int/OTA_int_revised_post.sym
@@ -0,0 +1,24 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -40 -30 -40 50 {} +L 4 -40 50 70 10 {} +L 4 -40 -30 70 10 {} +B 5 17.5 -12.5 22.5 -7.5 {name=vdd dir=inout } +B 5 -42.5 -12.5 -37.5 -7.5 {name=vp dir=in } +B 5 -42.5 7.5 -37.5 12.5 {name=vn dir=in } +B 5 -42.5 27.5 -37.5 32.5 {name=vbias dir=in } +B 5 17.5 27.5 22.5 32.5 {name=vss dir=inout } +B 5 67.5 7.5 72.5 12.5 {name=vout dir=out } +T {@symname} -11.5 4 0 0 0.2 0.2 {} +T {@name} 45 -22 0 0 0.2 0.2 {} +T {vdd} 15 -4 0 1 0.2 0.2 {} +T {vp} -35 -14 0 0 0.2 0.2 {} +T {vn} -35 6 0 0 0.2 0.2 {} +T {vbias} -35 26 0 0 0.2 0.2 {}
diff --git a/xschem/src/OTA_tri/OTA_tri.sch b/xschem/src/OTA_tri/OTA_tri.sch new file mode 100644 index 0000000..6bb0913 --- /dev/null +++ b/xschem/src/OTA_tri/OTA_tri.sch
@@ -0,0 +1,211 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +T {gm/id=11} -250 -190 0 0 0.2 0.2 {} +T {gm/id=11} -70 -190 0 0 0.2 0.2 {} +T {gm/id=11} 270 -190 0 0 0.2 0.2 {} +T {gm/id=15} -80 -90 0 0 0.2 0.2 {} +T {gm/id=15} 20 -90 0 0 0.2 0.2 {} +T {gm/id=17} -60 50 0 0 0.2 0.2 {} +T {gm/id=17} 0 50 0 0 0.2 0.2 {} +T {gm/id=17} 270 0 0 0 0.2 0.2 {} +T {32k} 130 -80 0 0 0.2 0.2 {} +N -380 -70 -310 -70 { lab=vn} +N -390 -30 -310 -30 { lab=vbias} +N -390 -70 -380 -70 { lab=vn} +N -390 -110 -370 -110 { lab=vp} +N -370 -110 -310 -110 { lab=vp} +N -380 -140 -310 -140 { lab=vdd} +N -370 0 -310 0 { lab=vss} +N -380 0 -370 0 { lab=vss} +N -260 -190 -260 -110 { lab=vbias} +N -260 70 80 70 { lab=vss} +N -90 40 -90 70 { lab=vss} +N 80 40 80 70 { lab=vss} +N -90 -80 -90 10 { lab=vf} +N 80 -80 80 10 { lab=v1} +N -90 -140 80 -140 { lab=vc} +N 0 -190 0 -140 { lab=vc} +N -50 40 40 40 { lab=vf} +N -90 -10 -10 -10 { lab=vf} +N -10 -10 -10 40 { lab=vf} +N -260 -160 -190 -160 { lab=vbias} +N -190 -220 -190 -160 { lab=vbias} +N -220 -220 -40 -220 { lab=vbias} +N 330 -190 330 -70 { lab=vout} +N 330 -220 340 -220 { lab=vdd} +N 340 -250 340 -220 { lab=vdd} +N 330 -10 330 70 { lab=vss} +N 80 70 230 70 { lab=vss} +N 330 -40 360 -40 { lab=vss} +N 360 -40 360 -10 { lab=vss} +N 330 -10 360 -10 { lab=vss} +N -260 -250 240 -250 { lab=vdd} +N 0 -250 0 -220 { lab=vdd} +N -260 -250 -260 -220 { lab=vdd} +N 260 -220 290 -220 { lab=vbias} +N 290 -40 290 -10 { lab=v1} +N 80 -10 190 -10 { lab=v1} +N -150 -110 -130 -110 { lab=vn} +N 120 -110 140 -110 { lab=vp} +N 290 70 330 70 { lab=vss} +N 260 -10 290 -10 { lab=v1} +N 240 -250 310 -250 { lab=vdd} +N 230 70 290 70 { lab=vss} +N 310 -250 330 -250 { lab=vdd} +N 330 -250 340 -250 { lab=vdd} +N 150 -90 150 -80 { lab=#net1} +N 170 -90 190 -90 { lab=#net1} +N 150 -20 150 -10 { lab=v1} +N 150 -90 170 -90 { lab=#net1} +N 190 -90 210 -90 { lab=#net1} +N 270 -90 330 -90 { lab=vout} +N 190 -10 260 -10 { lab=v1} +N 330 -120 370 -120 { lab=vout} +N 100 -50 130 -50 { lab=vss} +N -90 -140 -90 -110 { lab=vc} +N 80 -140 80 -110 { lab=vc} +C {ipin.sym} -380 -110 0 0 {name=p3 lab=vp} +C {ipin.sym} -380 -70 0 0 {name=p4 lab=vn} +C {ipin.sym} -380 -30 0 0 {name=p6 lab=vbias} +C {lab_wire.sym} -320 -30 0 0 {name=l5 sig_type=std_logic lab=vbias} +C {iopin.sym} -380 0 0 1 {name=p2 lab=vss} +C {lab_wire.sym} -330 -110 0 0 {name=l7 sig_type=std_logic lab=vp} +C {lab_wire.sym} -340 -70 0 1 {name=l9 sig_type=std_logic lab=vn} +C {lab_wire.sym} -320 -140 0 1 {name=l10 sig_type=std_logic lab=vdd} +C {iopin.sym} -380 -140 0 1 {name=p7 lab=vdd} +C {lab_wire.sym} -330 0 0 0 {name=l18 sig_type=std_logic lab=vss} +C {opin.sym} 370 -120 0 0 {name=p1 lab=vout} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 100 -110 0 1 {name=M1 +L=1 +W=4 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} -110 -110 0 0 {name=M2 +L=1 +W=4 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} -20 -220 0 0 {name=M3 +L=1 +W=2 +nf=2 +mult=24 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 60 40 0 0 {name=M4 +L=1 +W=1 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -70 40 0 1 {name=M5 +L=1 +W=1 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} -240 -220 0 1 {name=M6 +L=1 +W=2 +nf=2 +mult=24 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 310 -220 0 0 {name=M7 +L=1 +W=2 +nf=3 +mult=48 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 310 -40 0 0 {name=M8 +L=1 +W=1 +nf=1 +mult=64 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} -140 -220 0 0 {name=l1 sig_type=std_logic lab=vbias} +C {lab_wire.sym} -150 -250 0 0 {name=l8 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 250 -10 0 0 {name=l13 sig_type=std_logic lab=v1} +C {lab_wire.sym} 40 -140 0 0 {name=l14 sig_type=std_logic lab=vc} +C {lab_wire.sym} 330 -100 0 0 {name=l15 sig_type=std_logic lab=vout} +C {lab_wire.sym} -30 -10 0 0 {name=l16 sig_type=std_logic lab=vf} +C {lab_wire.sym} 140 -110 0 0 {name=l12 sig_type=std_logic lab=vp} +C {lab_wire.sym} 280 -220 0 0 {name=l4 sig_type=std_logic lab=vbias} +C {lab_wire.sym} -140 -110 0 0 {name=l17 sig_type=std_logic lab=vn} +C {sky130_fd_pr/cap_mim_m3_1.sym} 240 -90 3 0 {name=C1 model=cap_mim_m3_1 W=27 L=18 MF=1 spiceprefix=X} +C {lab_wire.sym} -230 70 0 0 {name=l3 sig_type=std_logic lab=vss} +C {lab_wire.sym} 110 -50 0 0 {name=l11 sig_type=std_logic lab=vss} +C {sky130_fd_pr/res_xhigh_po.sym} 150 -50 0 0 {name=R1 +W=0.35 +L=1.4 +model=res_xhigh_po +spiceprefix=X +mult=1}
diff --git a/xschem/src/OTA_tri/OTA_tri.sym b/xschem/src/OTA_tri/OTA_tri.sym new file mode 100644 index 0000000..24a9d71 --- /dev/null +++ b/xschem/src/OTA_tri/OTA_tri.sym
@@ -0,0 +1,24 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -80 -70 -80 10 {} +L 4 -80 10 30 -30 {} +L 4 -80 -70 30 -30 {} +B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout } +B 5 -82.5 -52.5 -77.5 -47.5 {name=vp dir=in } +B 5 -82.5 -32.5 -77.5 -27.5 {name=vn dir=in } +B 5 -82.5 -12.5 -77.5 -7.5 {name=vbias dir=in } +B 5 -22.5 -12.5 -17.5 -7.5 {name=vss dir=inout } +B 5 27.5 -32.5 32.5 -27.5 {name=vout dir=out } +T {@symname} -51.5 -36 0 0 0.2 0.2 {} +T {@name} 5 -62 0 0 0.2 0.2 {} +T {vdd} -25 -44 0 1 0.2 0.2 {} +T {vp} -75 -54 0 0 0.2 0.2 {} +T {vn} -75 -34 0 0 0.2 0.2 {} +T {vbias} -75 -14 0 0 0.2 0.2 {}
diff --git a/xschem/src/OTA_tri/OTA_tri_post.sym b/xschem/src/OTA_tri/OTA_tri_post.sym new file mode 100644 index 0000000..215f19a --- /dev/null +++ b/xschem/src/OTA_tri/OTA_tri_post.sym
@@ -0,0 +1,24 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 30 -30 30 50 {} +L 4 30 50 140 10 {} +L 4 30 -30 140 10 {} +B 5 87.5 -12.5 92.5 -7.5 {name=vdd dir=inout } +B 5 27.5 -12.5 32.5 -7.5 {name=vp dir=in } +B 5 27.5 7.5 32.5 12.5 {name=vn dir=in } +B 5 27.5 27.5 32.5 32.5 {name=vbias dir=in } +B 5 87.5 27.5 92.5 32.5 {name=vss dir=inout } +B 5 137.5 7.5 142.5 12.5 {name=vout dir=out } +T {@symname} 58.5 4 0 0 0.2 0.2 {} +T {@name} 115 -22 0 0 0.2 0.2 {} +T {vdd} 85 -4 0 1 0.2 0.2 {} +T {vp} 35 -14 0 0 0.2 0.2 {} +T {vn} 35 6 0 0 0.2 0.2 {} +T {vbias} 35 26 0 0 0.2 0.2 {}
diff --git a/xschem/src/OTA_tri/OTA_tri_revised_post.sym b/xschem/src/OTA_tri/OTA_tri_revised_post.sym new file mode 100644 index 0000000..0e4b1cf --- /dev/null +++ b/xschem/src/OTA_tri/OTA_tri_revised_post.sym
@@ -0,0 +1,24 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 10 -40 10 40 {} +L 4 10 40 120 0 {} +L 4 10 -40 120 0 {} +B 5 67.5 -22.5 72.5 -17.5 {name=vdd dir=inout } +B 5 7.5 -22.5 12.5 -17.5 {name=vp dir=in } +B 5 7.5 -2.5 12.5 2.5 {name=vn dir=in } +B 5 7.5 17.5 12.5 22.5 {name=vbias dir=in } +B 5 67.5 17.5 72.5 22.5 {name=vss dir=inout } +B 5 117.5 -2.5 122.5 2.5 {name=vout dir=out } +T {@symname} 38.5 -6 0 0 0.2 0.2 {} +T {@name} 95 -32 0 0 0.2 0.2 {} +T {vdd} 65 -14 0 1 0.2 0.2 {} +T {vp} 15 -24 0 0 0.2 0.2 {} +T {vn} 15 -4 0 0 0.2 0.2 {} +T {vbias} 15 16 0 0 0.2 0.2 {}
diff --git a/xschem/src/S_to_D/S_to_D.sch b/xschem/src/S_to_D/S_to_D.sch new file mode 100644 index 0000000..86c8129 --- /dev/null +++ b/xschem/src/S_to_D/S_to_D.sch
@@ -0,0 +1,83 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 250 -100 250 -80 { lab=vdd} +N 250 -40 250 -10 { lab=vss} +N 300 -60 330 -60 { lab=vn} +N 330 -160 330 -60 { lab=vn} +N 280 -160 330 -160 { lab=vn} +N 120 -160 220 -160 { lab=v1} +N 120 -160 120 -60 { lab=v1} +N 110 -60 120 -60 { lab=v1} +N 30 -60 50 -60 { lab=vi} +N 120 -60 190 -60 { lab=v1} +N 150 -40 190 -40 { lab=vbias2} +N 170 -80 190 -80 { lab=vref} +N 330 -60 360 -60 { lab=vn} +N 260 -330 260 -300 { lab=vdd} +N 260 -260 260 -240 { lab=vss} +N 310 -280 340 -280 { lab=vp} +N 170 -260 200 -260 { lab=vbias1} +N 340 -280 380 -280 { lab=vp} +N 80 -40 100 -40 { lab=vss} +N 250 -140 270 -140 { lab=vss} +N 30 -230 30 -60 { lab=vi} +N 120 -230 340 -230 { lab=vp} +N 120 -280 120 -230 { lab=vp} +N 340 -280 340 -230 { lab=vp} +N 30 -280 30 -240 { lab=vi} +N 30 -240 30 -230 { lab=vi} +N -110 -200 30 -200 { lab=vi} +N 360 -60 370 -60 { lab=vn} +N -110 -230 -90 -230 { lab=vdd} +N -110 -90 -100 -90 { lab=vss} +N -100 -90 -90 -90 { lab=vss} +N -110 -160 -70 -160 { lab=vref} +N 170 -300 200 -300 { lab=vi} +N -110 -120 -70 -120 { lab=vbias1} +N 120 -280 200 -280 { lab=vp} +N 30 -300 170 -300 { lab=vi} +N 30 -300 30 -280 { lab=vi} +N -110 -60 -70 -60 { lab=vbias2} +C {src/OTA/OTA.sym} 280 -160 0 0 {name=x1} +C {lab_wire.sym} 250 -100 0 0 {name=l1 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 170 -40 0 0 {name=l5 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 180 -80 0 0 {name=l12 sig_type=std_logic lab=vref} +C {lab_wire.sym} 350 -60 0 1 {name=l15 sig_type=std_logic lab=vn} +C {lab_wire.sym} 160 -60 0 0 {name=l16 sig_type=std_logic lab=v1} +C {sky130_fd_pr/res_xhigh_po_0p35.sym} 250 -160 3 0 {name=R2 +W=0.35 +L=10 +model=res_xhigh_po +spiceprefix=X +mult=1} +C {src/OTA/OTA.sym} 290 -380 0 0 {name=x2} +C {lab_wire.sym} 260 -320 0 0 {name=l19 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 190 -260 0 0 {name=l21 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 360 -280 0 1 {name=l22 sig_type=std_logic lab=vp} +C {lab_wire.sym} 250 -20 0 1 {name=l3 sig_type=std_logic lab=vss} +C {lab_wire.sym} 260 -240 0 1 {name=l4 sig_type=std_logic lab=vss} +C {iopin.sym} -110 -230 0 1 {name=p1 lab=vdd} +C {iopin.sym} -110 -90 0 1 {name=p2 lab=vss} +C {ipin.sym} -110 -200 0 0 {name=p3 lab=vi} +C {opin.sym} 380 -280 0 0 {name=p4 lab=vp} +C {opin.sym} 370 -60 0 0 {name=p5 lab=vn} +C {lab_wire.sym} -100 -230 0 1 {name=l7 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -100 -90 0 1 {name=l9 sig_type=std_logic lab=vss} +C {ipin.sym} -110 -160 0 0 {name=p6 lab=vref} +C {lab_wire.sym} -80 -160 0 1 {name=l10 sig_type=std_logic lab=vref} +C {ipin.sym} -110 -120 0 0 {name=p7 lab=vbias1} +C {lab_wire.sym} -80 -120 0 1 {name=l13 sig_type=std_logic lab=vbias1} +C {ipin.sym} -110 -60 0 0 {name=p8 lab=vbias2} +C {lab_wire.sym} -80 -60 0 1 {name=l8 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 90 -40 0 1 {name=l2 sig_type=std_logic lab=vss} +C {lab_wire.sym} 260 -140 0 1 {name=l6 sig_type=std_logic lab=vss} +C {sky130_fd_pr/res_xhigh_po_0p35.sym} 80 -60 3 0 {name=R1 +W=0.35 +L=10 +model=res_xhigh_po +spiceprefix=X +mult=1}
diff --git a/xschem/src/S_to_D/S_to_D.sym b/xschem/src/S_to_D/S_to_D.sym new file mode 100644 index 0000000..c227ea8 --- /dev/null +++ b/xschem/src/S_to_D/S_to_D.sym
@@ -0,0 +1,37 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -40 -130 40 {} +L 4 70 -40 70 40 {} +L 4 70 -10 90 -10 {} +L 4 -150 10 -130 10 {} +L 4 -150 -10 -130 -10 {} +L 4 -150 30 -130 30 {} +L 4 70 10 90 10 {} +L 4 -130 -40 70 -40 {} +L 4 -130 40 70 40 {} +L 4 -150 -30 -130 -30 {} +B 5 -32.5 -42.5 -27.5 -37.5 {name=vdd dir=inout } +B 5 -152.5 -32.5 -147.5 -27.5 {name=vbias1 dir=in } +B 5 -152.5 -12.5 -147.5 -7.5 {name=vbias2 dir=in } +B 5 -152.5 7.5 -147.5 12.5 {name=vi dir=in } +B 5 -152.5 27.5 -147.5 32.5 {name=vref dir=in } +B 5 -32.5 37.5 -27.5 42.5 {name=vss dir=inout } +B 5 87.5 7.5 92.5 12.5 {name=vn dir=out } +B 5 87.5 -12.5 92.5 -7.5 {name=vp dir=out } +T {@symname} -75 -6 0 0 0.3 0.3 {} +T {@name} 75 -52 0 0 0.2 0.2 {} +T {vdd} -25 -34 0 1 0.2 0.2 {} +T {vp} 65 -14 0 1 0.2 0.2 {} +T {vi} -125 6 0 0 0.2 0.2 {} +T {vref} -125 26 0 0 0.2 0.2 {} +T {vbias2} -125 -14 0 0 0.2 0.2 {} +T {vn} 65 6 0 1 0.2 0.2 {} +T {vss} -25 26 0 1 0.2 0.2 {} +T {vbias1} -125 -34 0 0 0.2 0.2 {}
diff --git a/xschem/src/S_to_D/S_to_D_post.sym b/xschem/src/S_to_D/S_to_D_post.sym new file mode 100644 index 0000000..08bb13f --- /dev/null +++ b/xschem/src/S_to_D/S_to_D_post.sym
@@ -0,0 +1,37 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -120 -60 -120 20 {} +L 4 80 -60 80 20 {} +L 4 80 -30 100 -30 {} +L 4 -140 -10 -120 -10 {} +L 4 -140 -30 -120 -30 {} +L 4 -140 10 -120 10 {} +L 4 80 -10 100 -10 {} +L 4 -120 -60 80 -60 {} +L 4 -120 20 80 20 {} +L 4 -140 -50 -120 -50 {} +B 5 -22.5 -62.5 -17.5 -57.5 {name=vdd dir=inout } +B 5 -142.5 -52.5 -137.5 -47.5 {name=vbias1 dir=in } +B 5 -142.5 -32.5 -137.5 -27.5 {name=vbias2 dir=in } +B 5 -142.5 -12.5 -137.5 -7.5 {name=vi dir=in } +B 5 -142.5 7.5 -137.5 12.5 {name=vref dir=in } +B 5 -22.5 17.5 -17.5 22.5 {name=vss dir=inout } +B 5 97.5 -12.5 102.5 -7.5 {name=vn dir=out } +B 5 97.5 -32.5 102.5 -27.5 {name=vp dir=out } +T {@symname} -65 -26 0 0 0.3 0.3 {} +T {@name} 85 -72 0 0 0.2 0.2 {} +T {vdd} -15 -54 0 1 0.2 0.2 {} +T {vp} 75 -34 0 1 0.2 0.2 {} +T {vi} -115 -14 0 0 0.2 0.2 {} +T {vref} -115 6 0 0 0.2 0.2 {} +T {vbias2} -115 -34 0 0 0.2 0.2 {} +T {vn} 75 -14 0 1 0.2 0.2 {} +T {vss} -15 6 0 1 0.2 0.2 {} +T {vbias1} -115 -54 0 0 0.2 0.2 {}
diff --git a/xschem/src/S_to_D/S_to_D_revised_post.sym b/xschem/src/S_to_D/S_to_D_revised_post.sym new file mode 100644 index 0000000..c39a656 --- /dev/null +++ b/xschem/src/S_to_D/S_to_D_revised_post.sym
@@ -0,0 +1,37 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 20 -20 20 60 {} +L 4 220 -20 220 60 {} +L 4 220 10 240 10 {} +L 4 0 30 20 30 {} +L 4 0 10 20 10 {} +L 4 0 50 20 50 {} +L 4 220 30 240 30 {} +L 4 20 -20 220 -20 {} +L 4 20 60 220 60 {} +L 4 0 -10 20 -10 {} +B 5 117.5 -22.5 122.5 -17.5 {name=vdd dir=inout } +B 5 -2.5 -12.5 2.5 -7.5 {name=vbias1 dir=in } +B 5 -2.5 7.5 2.5 12.5 {name=vbias2 dir=in } +B 5 -2.5 27.5 2.5 32.5 {name=vi dir=in } +B 5 -2.5 47.5 2.5 52.5 {name=vref dir=in } +B 5 117.5 57.5 122.5 62.5 {name=vss dir=inout } +B 5 237.5 27.5 242.5 32.5 {name=vn dir=out } +B 5 237.5 7.5 242.5 12.5 {name=vp dir=out } +T {@symname} 75 14 0 0 0.3 0.3 {} +T {@name} 225 -32 0 0 0.2 0.2 {} +T {vdd} 125 -14 0 1 0.2 0.2 {} +T {vp} 215 6 0 1 0.2 0.2 {} +T {vi} 25 26 0 0 0.2 0.2 {} +T {vref} 25 46 0 0 0.2 0.2 {} +T {vbias2} 25 6 0 0 0.2 0.2 {} +T {vn} 215 26 0 1 0.2 0.2 {} +T {vss} 125 46 0 1 0.2 0.2 {} +T {vbias1} 25 -14 0 0 0.2 0.2 {}
diff --git a/xschem/src/S_to_D/S_to_D_tb.sch b/xschem/src/S_to_D/S_to_D_tb.sch new file mode 100644 index 0000000..cbedac6 --- /dev/null +++ b/xschem/src/S_to_D/S_to_D_tb.sch
@@ -0,0 +1,129 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -220 -140 -220 -120 { lab=vdd} +N -220 -140 -200 -140 { lab=vdd} +N -180 80 -180 110 { lab=vin} +N -420 -100 -420 -70 { lab=vref} +N -490 -40 -490 -20 { lab=vdd} +N -490 180 -490 190 { lab=GND} +N -490 150 -490 180 { lab=GND} +N -450 150 -410 150 { lab=#net1} +N -420 70 -420 150 { lab=#net1} +N -410 150 -370 150 { lab=#net1} +N -330 190 -330 220 { lab=GND} +N -420 190 -400 190 { lab=vbias1} +N -420 190 -420 270 { lab=vbias1} +N -370 190 -340 190 { lab=GND} +N -340 190 -330 190 { lab=GND} +N -420 40 -420 70 { lab=#net1} +N -490 40 -420 40 { lab=#net1} +N -490 110 -490 120 { lab=#net2} +N -490 40 -490 50 { lab=#net1} +N -370 150 -280 150 { lab=#net1} +N -330 190 -310 190 { lab=GND} +N -310 190 -280 190 { lab=GND} +N -250 190 -250 270 { lab=vbias2} +N 70 -90 70 -60 { lab=vdd} +N 70 20 70 40 { lab=GND} +N -100 -50 -50 -50 { lab=vbias1} +N -100 -30 -50 -30 { lab=vbias2} +N -100 -10 -50 -10 { lab=vin} +N -100 10 -50 10 { lab=vref} +N 190 -30 240 -30 { lab=vp} +N 190 -10 240 -10 { lab=vn} +C {vsource.sym} -220 -90 0 0 {name=V3 value=1.8} +C {gnd.sym} -220 -60 0 0 {name=l6 lab=GND} +C {lab_wire.sym} -200 -140 0 0 {name=l7 sig_type=std_logic lab=vdd} +C {code_shown.sym} 350 -220 0 0 {name=s1 only_toplevel=false value=" +.nodeset V(v1)=0.9 +.control +save vp vn vin +tran 10n 500u +.endc +"} +C {netlist_not_shown.sym} -300 -280 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/ss.spice +.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_post.spice + +.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_revised_post.spice + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {vsource.sym} -180 140 0 0 {name=V2 value="sin(0.9 0.8 5k)"} +C {gnd.sym} -180 170 0 0 {name=l9 lab=GND} +C {vsource.sym} -420 -40 0 0 {name=V1 value=0.9} +C {gnd.sym} -420 -10 0 0 {name=l3 lab=GND} +C {lab_wire.sym} -180 90 0 0 {name=l11 sig_type=std_logic lab=vin} +C {isource.sym} -490 10 0 0 {name=I0 value=15u} +C {lab_wire.sym} -490 -40 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} -490 190 0 0 {name=l4 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -470 150 0 1 {name=M5 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -370 170 3 1 {name=M6 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} -330 220 0 0 {name=l54 lab=GND} +C {lab_wire.sym} -420 -90 0 0 {name=l10 sig_type=std_logic lab=vref} +C {vsource.sym} -490 80 2 0 {name=V5 value=0} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -280 170 1 0 {name=M1 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} -250 240 2 0 {name=l1 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} -420 240 2 0 {name=l2 sig_type=std_logic lab=vbias1} +C {gnd.sym} 70 40 0 0 {name=l5 lab=GND} +C {lab_wire.sym} 70 -80 0 0 {name=l8 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -70 -50 0 0 {name=l12 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} -80 -30 0 0 {name=l13 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} -70 10 0 0 {name=l14 sig_type=std_logic lab=vref} +C {lab_wire.sym} -80 -10 0 0 {name=l15 sig_type=std_logic lab=vin} +C {lab_wire.sym} 210 -30 0 1 {name=l16 sig_type=std_logic lab=vp} +C {lab_wire.sym} 210 -10 0 1 {name=l17 sig_type=std_logic lab=vn} +C {src/S_to_D/S_to_D.sym} 100 -20 0 0 {name=x1}
diff --git a/xschem/src/basic_test/data_nmos/data_015.raw b/xschem/src/basic_test/data_nmos/data_015.raw new file mode 100644 index 0000000..3255dbe --- /dev/null +++ b/xschem/src/basic_test/data_nmos/data_015.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_nmos +Date: Tue Jun 1 20:07:27 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -3.794663635455580e-16 + 5.922017570577976e-20 + -4.821791968922638e-18 + 1.171284598253324e-13 + 2.426094293472705e-12 + 9.326278971502852e-14 + + 1 1.000000000000000e-02 + -3.775943441400648e-16 + 6.255773436350447e-20 + -5.118011829353092e-18 + 1.511317042577190e-13 + 3.146854257730783e-12 + 1.209714828548612e-13 + + 2 2.000000000000000e-02 + -3.757439778703655e-16 + 6.609766272580900e-20 + -5.436974764221158e-18 + 1.950001781133364e-13 + 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diff --git a/xschem/src/basic_test/data_nmos/data_020.raw b/xschem/src/basic_test/data_nmos/data_020.raw new file mode 100644 index 0000000..5e5c802 --- /dev/null +++ b/xschem/src/basic_test/data_nmos/data_020.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_nmos +Date: Tue Jun 1 20:08:21 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -5.163526292823956e-16 + 2.369765767701746e-20 + -5.070524459472119e-18 + 7.707800483957246e-15 + 2.834572575263908e-13 + 9.337015001545679e-15 + + 1 1.000000000000000e-02 + -5.138904544287486e-16 + 2.520597458004591e-20 + -5.410761614477290e-18 + 1.039981116551126e-14 + 3.839959442972729e-13 + 1.264888765364240e-14 + + 2 2.000000000000000e-02 + -5.114553868287533e-16 + 2.680763072873240e-20 + -5.778782590561715e-18 + 1.403174187072742e-14 + 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diff --git a/xschem/src/basic_test/data_nmos/data_025.raw b/xschem/src/basic_test/data_nmos/data_025.raw new file mode 100644 index 0000000..c487aa9 --- /dev/null +++ b/xschem/src/basic_test/data_nmos/data_025.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_nmos +Date: Tue Jun 1 20:08:56 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -6.530491504143914e-16 + 1.628512568974113e-20 + -9.566290452191098e-18 + 1.261744196027347e-14 + 6.528079681760675e-13 + 2.313364909569108e-14 + + 1 1.000000000000000e-02 + -6.499210219689331e-16 + 1.725615442031527e-20 + -1.021364608056309e-17 + 1.669551665852701e-14 + 8.656274010054692e-13 + 3.067585345682624e-14 + + 2 2.000000000000000e-02 + -6.468207948333442e-16 + 1.828953703369002e-20 + -1.091475124739828e-17 + 2.209145315547113e-14 + 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diff --git a/xschem/src/basic_test/data_nmos/data_030.raw b/xschem/src/basic_test/data_nmos/data_030.raw new file mode 100644 index 0000000..4d539af --- /dev/null +++ b/xschem/src/basic_test/data_nmos/data_030.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_nmos +Date: Tue Jun 1 20:09:29 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -7.359161034432674e-16 + 6.727873019948289e-20 + -1.570227772065605e-17 + 2.177720898487250e-14 + 1.378314109616080e-12 + 5.035898211441353e-14 + + 1 1.000000000000000e-02 + -7.318491248863505e-16 + 7.210870476278097e-20 + -1.679576305478386e-17 + 2.858549870696987e-14 + 1.812180125584095e-12 + 6.621264342287522e-14 + + 2 2.000000000000000e-02 + -7.278195147662337e-16 + 7.733561407702083e-20 + -1.798244993372780e-17 + 3.752186542379264e-14 + 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diff --git a/xschem/src/basic_test/data_nmos/data_035.raw b/xschem/src/basic_test/data_nmos/data_035.raw new file mode 100644 index 0000000..e37ba24 --- /dev/null +++ b/xschem/src/basic_test/data_nmos/data_035.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_nmos +Date: Tue Jun 1 20:10:04 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -8.162638982249190e-16 + 9.869405359794599e-20 + -2.140104270172073e-17 + 2.910341370921940e-14 + 2.050136600901583e-12 + 7.645039879080118e-14 + + 1 1.000000000000000e-02 + -8.112435811686914e-16 + 1.059888878905463e-19 + -2.290791249246154e-17 + 3.801756222348837e-14 + 2.680589958576916e-12 + 9.996335462289931e-14 + + 2 2.000000000000000e-02 + -8.062731028820384e-16 + 1.139100889014408e-19 + -2.454526461531527e-17 + 4.966145804163018e-14 + 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diff --git a/xschem/src/basic_test/data_nmos/data_040.raw b/xschem/src/basic_test/data_nmos/data_040.raw new file mode 100644 index 0000000..2f23a63 --- /dev/null +++ b/xschem/src/basic_test/data_nmos/data_040.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_nmos +Date: Tue Jun 1 20:10:33 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -8.949643023640091e-16 + 1.107816266222269e-19 + -2.642889182271885e-17 + 3.001503435927582e-14 + 2.452113326294682e-12 + 9.281250320020572e-14 + + 1 1.000000000000000e-02 + -8.889843439092126e-16 + 1.190718730752803e-19 + -2.829801826980385e-17 + 3.906953623505257e-14 + 3.193480845651282e-12 + 1.208774953186578e-13 + + 2 2.000000000000000e-02 + -8.830695647524088e-16 + 1.280936285192065e-19 + -3.033148720059787e-17 + 5.085483010460047e-14 + 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diff --git a/xschem/src/basic_test/data_nmos/data_045.raw b/xschem/src/basic_test/data_nmos/data_045.raw new file mode 100644 index 0000000..c4d1962 --- /dev/null +++ b/xschem/src/basic_test/data_nmos/data_045.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_nmos +Date: Tue Jun 1 20:11:05 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -9.725019916408052e-16 + 1.095169022276109e-19 + -3.082008542774421e-17 + 2.672312541729529e-14 + 2.622687323900150e-12 + 1.004074826948645e-13 + + 1 1.000000000000000e-02 + -9.655582033922003e-16 + 1.177657089281175e-19 + -3.300379859209337e-17 + 3.468860927563519e-14 + 3.405398749885613e-12 + 1.303777968701762e-13 + + 2 2.000000000000000e-02 + -9.586973831357841e-16 + 1.267592226130252e-19 + -3.538263971397157e-17 + 4.502781217438745e-14 + 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diff --git a/xschem/src/basic_test/data_nmos/data_050.raw b/xschem/src/basic_test/data_nmos/data_050.raw new file mode 100644 index 0000000..5013f89 --- /dev/null +++ b/xschem/src/basic_test/data_nmos/data_050.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_nmos +Date: Tue Jun 1 20:11:59 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -1.049179199197191e-15 + 1.005342136801270e-19 + -3.467337094982030e-17 + 2.189610941559236e-14 + 2.647527226110249e-12 + 1.022760898016355e-13 + + 1 1.000000000000000e-02 + -1.041267716915927e-15 + 1.081374283235667e-19 + -3.713138312771321e-17 + 2.835993311588538e-14 + 3.429598837625274e-12 + 1.324932679323826e-13 + + 2 2.000000000000000e-02 + -1.033459038334247e-15 + 1.164420730438708e-19 + -3.981285579733803e-17 + 3.673140871234316e-14 + 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diff --git a/xschem/src/basic_test/data_nmos_lvt/data_100.raw b/xschem/src/basic_test/data_nmos_lvt/data_100.raw new file mode 100644 index 0000000..7c9630e --- /dev/null +++ b/xschem/src/basic_test/data_nmos_lvt/data_100.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_nmos +Date: Sat Jun 12 17:26:53 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -8.009646926055015e-15 + -1.218287032801904e-19 + -1.578676334880824e-15 + 7.697485313945830e-13 + 6.833016536843870e-11 + 2.246341882577886e-12 + 4.829638923799480e-01 + + 1 1.000000000000000e-02 + -7.927011269174477e-15 + -1.315773639194775e-19 + -1.701417794212658e-15 + 1.043378299409144e-12 + 9.260834991900495e-11 + 3.044896995263743e-12 + 4.829638923799569e-01 + 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diff --git a/xschem/src/basic_test/data_nmos_lvt/data_15.raw b/xschem/src/basic_test/data_nmos_lvt/data_15.raw new file mode 100644 index 0000000..569b9ae --- /dev/null +++ b/xschem/src/basic_test/data_nmos_lvt/data_15.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_nmos +Date: Sat Jun 12 17:25:08 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -2.089723034809680e-16 + 4.867402892232669e-19 + -2.573550857020925e-17 + 1.564641846748040e-12 + 3.377444808317574e-11 + 1.420671750150482e-12 + 5.831173769968007e-01 + + 1 1.000000000000000e-02 + -2.075907120619596e-16 + 5.172854226328070e-19 + -2.730442803587995e-17 + 1.983896005814130e-12 + 4.283615484914212e-11 + 1.801932231606155e-12 + 5.831173769968283e-01 + + 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diff --git a/xschem/src/basic_test/data_nmos_lvt/data_200.raw b/xschem/src/basic_test/data_nmos_lvt/data_200.raw new file mode 100644 index 0000000..e1a5a6d --- /dev/null +++ b/xschem/src/basic_test/data_nmos_lvt/data_200.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_nmos +Date: Sat Jun 12 17:27:44 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -3.169491559745245e-14 + -5.477357362007135e-19 + -7.030819362904637e-15 + 7.307732420799105e-13 + 8.793015144020105e-11 + 2.762919241928982e-12 + 4.572448933692719e-01 + + 1 1.000000000000000e-02 + -3.135614257952621e-14 + -5.930271205859462e-19 + -7.599792987238073e-15 + 1.004580279118959e-12 + 1.208538770370403e-10 + 3.798135710462082e-12 + 4.572448933692765e-01 + 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diff --git a/xschem/src/basic_test/data_nmos_lvt/data_300.raw b/xschem/src/basic_test/data_nmos_lvt/data_300.raw new file mode 100644 index 0000000..d95c6c5 --- /dev/null +++ b/xschem/src/basic_test/data_nmos_lvt/data_300.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_nmos +Date: Wed Jun 16 15:44:50 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -7.119119204340541e-14 + -1.294201683346586e-18 + -1.633331148219569e-14 + 6.403846456372503e-13 + 9.667726854517827e-11 + 2.961476655562669e-12 + 4.446342125148689e-01 + + 1 1.000000000000000e-02 + -7.043252591983850e-14 + -1.403982946587811e-18 + -1.768601190119191e-14 + 8.875663578779272e-13 + 1.339644621730675e-10 + 4.104577618144324e-12 + 4.446342125148735e-01 + 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diff --git a/xschem/src/basic_test/data_nmos_lvt/data_35.raw b/xschem/src/basic_test/data_nmos_lvt/data_35.raw new file mode 100644 index 0000000..ff811c6 --- /dev/null +++ b/xschem/src/basic_test/data_nmos_lvt/data_35.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_nmos +Date: Sat Jun 12 17:25:41 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -1.074155062170495e-15 + 1.287406474941648e-22 + -1.411979929288208e-16 + 3.475355117697083e-13 + 2.853191830738364e-11 + 1.022659908072617e-12 + 5.471478173513024e-01 + + 1 1.000000000000000e-02 + -1.064908223611911e-15 + -8.209974158427923e-23 + -1.513810179715137e-16 + 4.592884282397611e-13 + 3.771050375803251e-11 + 1.351742231647639e-12 + 5.471478173513125e-01 + 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diff --git a/xschem/src/basic_test/data_nmos_lvt/data_50.raw b/xschem/src/basic_test/data_nmos_lvt/data_50.raw new file mode 100644 index 0000000..a29547e --- /dev/null +++ b/xschem/src/basic_test/data_nmos_lvt/data_50.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_nmos +Date: Sat Jun 12 17:26:15 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__nfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -2.003956520116756e-15 + -1.850087297873522e-20 + -3.595237001248965e-16 + 5.994191181802447e-13 + 5.247102500005964e-11 + 1.882671623108032e-12 + 5.208722804959438e-01 + + 1 1.000000000000000e-02 + -1.983814041279403e-15 + -2.007376629521078e-20 + -3.852224838019868e-16 + 7.920126826764376e-13 + 6.932847415413440e-11 + 2.487762557067537e-12 + 5.208722804959561e-01 + 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diff --git a/xschem/src/basic_test/data_pmos/data_015.raw b/xschem/src/basic_test/data_pmos/data_015.raw new file mode 100644 index 0000000..f2ca1b9 --- /dev/null +++ b/xschem/src/basic_test/data_pmos/data_015.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_pmos +Date: Wed Jun 2 14:54:21 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -5.329500465814102e-16 + 1.537733212950072e-18 + -1.969227254464294e-17 + 9.378420429425086e-11 + 7.555153185627128e-10 + 3.294890226714958e-11 + + 1 1.000000000000000e-02 + -5.312802835336909e-16 + 1.647430280539873e-18 + -2.100680570544607e-17 + 1.157679998816540e-10 + 9.329747889716244e-10 + 4.136360776217401e-11 + + 2 2.000000000000000e-02 + -5.296008106831105e-16 + 1.764775189017479e-18 + -2.241130168144101e-17 + 1.421904785280508e-10 + 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diff --git a/xschem/src/basic_test/data_pmos/data_020.raw b/xschem/src/basic_test/data_pmos/data_020.raw new file mode 100644 index 0000000..33f9f79 --- /dev/null +++ b/xschem/src/basic_test/data_pmos/data_020.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_pmos +Date: Wed Jun 2 14:57:33 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -6.087308210384991e-16 + 8.690298633560459e-20 + -6.970389559765051e-18 + 6.823708262274466e-14 + 2.286711218240453e-12 + 8.040190281642675e-14 + + 1 1.000000000000000e-02 + -6.057251230296432e-16 + 9.347085701180570e-20 + -7.419911273987235e-18 + 9.061875207723422e-14 + 3.035875412231005e-12 + 1.068389949454307e-13 + + 2 2.000000000000000e-02 + -6.027521004534046e-16 + 1.005387162898637e-19 + -7.903435340682562e-18 + 1.202974984531943e-13 + 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diff --git a/xschem/src/basic_test/data_pmos/data_025.raw b/xschem/src/basic_test/data_pmos/data_025.raw new file mode 100644 index 0000000..16c402c --- /dev/null +++ b/xschem/src/basic_test/data_pmos/data_025.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_pmos +Date: Wed Jun 2 14:58:09 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -6.526467467987277e-16 + 5.850564600020555e-21 + -5.107671295933520e-18 + 1.649454440352579e-15 + 7.832475633895286e-14 + 2.642493677621949e-15 + + 1 1.000000000000000e-02 + -6.466402908893156e-16 + 6.304733035335791e-21 + -5.424059456622211e-18 + 2.218494541576908e-15 + 1.053375926139059e-13 + 3.554147983332840e-15 + + 2 2.000000000000000e-02 + -6.407819293644570e-16 + 6.793085521165634e-21 + -5.764649080748838e-18 + 2.983760483020633e-15 + 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diff --git a/xschem/src/basic_test/data_pmos/data_030.raw b/xschem/src/basic_test/data_pmos/data_030.raw new file mode 100644 index 0000000..15878b5 --- /dev/null +++ b/xschem/src/basic_test/data_pmos/data_030.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_pmos +Date: Wed Jun 2 14:58:40 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -7.934780066098964e-16 + 5.715213048532131e-21 + -5.063435279664109e-18 + 1.628566966297598e-16 + 1.279630821805377e-14 + 4.318354292639193e-16 + + 1 1.000000000000000e-02 + -7.853634917440876e-16 + 6.163058595342308e-21 + -5.362402000124792e-18 + 2.190244897543618e-16 + 1.720913169887310e-14 + 5.807748746656020e-16 + + 2 2.000000000000000e-02 + -7.774733452892325e-16 + 6.644266802518487e-21 + -5.684364464092204e-18 + 2.945604632750105e-16 + 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diff --git a/xschem/src/basic_test/data_pmos/data_035.raw b/xschem/src/basic_test/data_pmos/data_035.raw new file mode 100644 index 0000000..27f18f0 --- /dev/null +++ b/xschem/src/basic_test/data_pmos/data_035.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_pmos +Date: Wed Jun 2 14:59:16 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -9.327655451579146e-16 + 6.012631636199412e-21 + -5.298752510150998e-18 + 4.316223196928665e-17 + 4.362951428646841e-15 + 1.472961095291725e-16 + + 1 1.000000000000000e-02 + -9.224730433688005e-16 + 6.487546779490866e-21 + -5.601312579646052e-18 + 5.804168442192043e-17 + 5.866915279479276e-15 + 1.980748179907054e-16 + + 2 2.000000000000000e-02 + -9.124880856706587e-16 + 6.997687042029328e-21 + -5.927356657383117e-18 + 7.805003309110686e-17 + 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diff --git a/xschem/src/basic_test/data_pmos/data_040.raw b/xschem/src/basic_test/data_pmos/data_040.raw new file mode 100644 index 0000000..418aaad --- /dev/null +++ b/xschem/src/basic_test/data_pmos/data_040.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_pmos +Date: Wed Jun 2 14:59:45 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -1.070371216892622e-15 + 6.559935974345097e-21 + -5.671460620577631e-18 + 1.622079268532961e-17 + 2.066299397557738e-15 + 6.978685099497756e-17 + + 1 1.000000000000000e-02 + -1.057876601376023e-15 + 7.081167234788603e-21 + -5.987920283641747e-18 + 2.181014886367414e-17 + 2.778278192914872e-15 + 9.383434256603032e-17 + + 2 2.000000000000000e-02 + -1.045776634322995e-15 + 7.640968856149171e-21 + -6.329151288439024e-18 + 2.932534244672526e-17 + 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diff --git a/xschem/src/basic_test/data_pmos/data_045.raw b/xschem/src/basic_test/data_pmos/data_045.raw new file mode 100644 index 0000000..f9437ec --- /dev/null +++ b/xschem/src/basic_test/data_pmos/data_045.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_pmos +Date: Wed Jun 2 15:00:13 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -1.206431678591055e-15 + 7.285248543520869e-21 + -6.122089582860418e-18 + 7.293112933677385e-18 + 1.191905768252669e-15 + 4.026921654420476e-17 + + 1 1.000000000000000e-02 + -1.191733725256571e-15 + 7.866592972664009e-21 + -6.458334912700919e-18 + 9.805167521227201e-18 + 1.602438491367970e-15 + 5.413983493747868e-17 + + 2 2.000000000000000e-02 + -1.177519581833876e-15 + 8.490886341753249e-21 + -6.821080795435255e-18 + 1.318242956546049e-17 + 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diff --git a/xschem/src/basic_test/data_pmos/data_050.raw b/xschem/src/basic_test/data_pmos/data_050.raw new file mode 100644 index 0000000..b48f53f --- /dev/null +++ b/xschem/src/basic_test/data_pmos/data_050.raw
@@ -0,0 +1,1463 @@ +Title: **.subckt gm_id_pmos +Date: Wed Jun 2 14:53:01 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 7 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8[id]) current +Values: + 0 0.000000000000000e+00 + -1.341194443784225e-15 + 8.155452808259654e-21 + -6.620755018472321e-18 + 3.609238761146369e-18 + 7.815852683917232e-16 + 2.641433496838171e-17 + + 1 1.000000000000000e-02 + -1.324301361880001e-15 + 8.808233613870964e-21 + -6.980447976602825e-18 + 4.851974773953125e-18 + 1.050697456131376e-15 + 3.550949263167130e-17 + + 2 2.000000000000000e-02 + -1.307982265732435e-15 + 9.509176330853769e-21 + -7.368638757825508e-18 + 6.522589571700612e-18 + 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diff --git a/xschem/src/basic_test/data_pmos_lvt/data_100.raw b/xschem/src/basic_test/data_pmos_lvt/data_100.raw new file mode 100644 index 0000000..a51490d --- /dev/null +++ b/xschem/src/basic_test/data_pmos_lvt/data_100.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_pmos +Date: Sat Jun 12 17:33:43 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -1.068972572390222e-14 + -3.875765732142908e-21 + -8.943751304229393e-17 + 8.814467626325418e-12 + 5.486534535915693e-10 + 2.017885394606450e-11 + 4.438652678499522e-01 + + 1 1.000000000000000e-02 + -1.063428606497758e-14 + -4.280366976915889e-21 + -9.661740603767400e-17 + 1.156621599997572e-11 + 7.189140609101973e-10 + 2.647869362087393e-11 + 4.438652678500473e-01 + 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diff --git a/xschem/src/basic_test/data_pmos_lvt/data_200.raw b/xschem/src/basic_test/data_pmos_lvt/data_200.raw new file mode 100644 index 0000000..73a86fd --- /dev/null +++ b/xschem/src/basic_test/data_pmos_lvt/data_200.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_pmos +Date: Sat Jun 12 17:34:24 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -4.282881403569398e-14 + -1.336306025180312e-20 + -2.759196983285481e-16 + 1.771306966473965e-12 + 2.184422910773213e-10 + 8.009713112555415e-12 + 4.708214608504653e-01 + + 1 1.000000000000000e-02 + -4.260338334778518e-14 + -1.477172165520505e-20 + -2.971579525519002e-16 + 2.326347413367116e-12 + 2.866073827499716e-10 + 1.051963752950337e-11 + 4.708214608504847e-01 + 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diff --git a/xschem/src/basic_test/data_pmos_lvt/data_300.raw b/xschem/src/basic_test/data_pmos_lvt/data_300.raw new file mode 100644 index 0000000..1eed038 --- /dev/null +++ b/xschem/src/basic_test/data_pmos_lvt/data_300.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_pmos +Date: Sat Jun 12 17:34:54 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -9.530325458083208e-14 + -3.229344711619415e-20 + -7.058023099113046e-16 + 1.519873148905640e-12 + 2.587581332615295e-10 + 9.501817451002420e-12 + 4.566118671354136e-01 + + 1 1.000000000000000e-02 + -9.480553100624523e-14 + -3.568044534996359e-20 + -7.614939071022604e-16 + 1.995271937955689e-12 + 3.392895397676935e-10 + 1.247401471941258e-11 + 4.566118671354288e-01 + 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diff --git a/xschem/src/basic_test/data_pmos_lvt/data_35.raw b/xschem/src/basic_test/data_pmos_lvt/data_35.raw new file mode 100644 index 0000000..1ac5009 --- /dev/null +++ b/xschem/src/basic_test/data_pmos_lvt/data_35.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_pmos +Date: Sat Jun 12 17:32:09 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -1.266240073651000e-15 + -3.236652670586527e-21 + -5.445403234660047e-17 + 3.546000488828226e-09 + 9.203688884341253e-08 + 3.953141412199626e-09 + 2.897319923240360e-01 + + 1 1.000000000000000e-02 + -1.259569970422486e-15 + -3.530217261925970e-21 + -5.912366409163455e-17 + 4.470507580560958e-09 + 1.151689633545638e-07 + 4.985072824610640e-09 + 2.897319923656396e-01 + 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diff --git a/xschem/src/basic_test/data_pmos_lvt/data_50.raw b/xschem/src/basic_test/data_pmos_lvt/data_50.raw new file mode 100644 index 0000000..faafc8c --- /dev/null +++ b/xschem/src/basic_test/data_pmos_lvt/data_50.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_pmos +Date: Sat Jun 12 17:33:03 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -2.648027086071396e-15 + -4.053283190015982e-21 + -5.978567851978388e-17 + 2.575183844316554e-10 + 8.580444027826376e-09 + 3.662728112167336e-10 + 3.816831461512467e-01 + + 1 1.000000000000000e-02 + -2.634274697081806e-15 + -4.406248137454577e-21 + -6.434249491232138e-17 + 3.253772668123496e-10 + 1.081327567392792e-08 + 4.628188242558892e-10 + 3.816831461542988e-01 + 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diff --git a/xschem/src/basic_test/data_pmos_lvt/data_500.raw b/xschem/src/basic_test/data_pmos_lvt/data_500.raw new file mode 100644 index 0000000..1607b1a --- /dev/null +++ b/xschem/src/basic_test/data_pmos_lvt/data_500.raw
@@ -0,0 +1,1645 @@ +Title: **.subckt gm_id_pmos +Date: Sat Jun 12 17:35:34 2021 +Plotname: DC transfer characteristic +Flags: real +No. Variables: 8 +No. Points: 181 +Variables: + 0 v(v-sweep) voltage + 1 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgb] capacitance + 2 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgd] capacitance + 3 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgs] capacitance + 4 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gds] admittance + 5 @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gm] admittance + 6 i(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[id]) current + 7 v(@m.xm1.msky130_fd_pr__pfet_01v8_lvt[vth]) voltage +Values: + 0 0.000000000000000e+00 + -2.634394260557092e-13 + -8.999308042201614e-20 + -2.026509817691571e-15 + 9.366058150646327e-13 + 2.458220484208681e-10 + 9.030312093517215e-12 + 4.532080111638443e-01 + + 1 1.000000000000000e-02 + -2.620655914976511e-13 + -9.941999299097842e-20 + -2.187424699434899e-15 + 1.229423763644743e-12 + 3.222732347721389e-10 + 1.185367733705245e-11 + 4.532080111638531e-01 + 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diff --git a/xschem/src/basic_test/ft_nmos.sch b/xschem/src/basic_test/ft_nmos.sch new file mode 100644 index 0000000..3dcc421 --- /dev/null +++ b/xschem/src/basic_test/ft_nmos.sch
@@ -0,0 +1,66 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 370 -70 370 -10 { lab=#net1} +N 460 -10 460 80 { lab=GND} +N 370 -10 370 0 { lab=#net1} +N 370 20 400 20 { lab=#net1} +N 400 -30 400 20 { lab=#net1} +N 370 -30 400 -30 { lab=#net1} +N 370 50 370 80 { lab=#net2} +N 370 140 370 170 { lab=GND} +N 370 -70 460 -70 { lab=#net1} +N 280 -70 380 -70 { lab=#net1} +N 280 -10 280 20 { lab=#net3} +N 280 20 330 20 { lab=#net3} +C {code_shown.sym} -170 10 0 0 {name=s1 only_toplevel=false value=" +.control +save all +save @m.xm1.msky130_fd_pr__nfet_01v8[gm] +save @m.xm1.msky130_fd_pr__pfet_01v8[id] +save @m.xm1.msky130_fd_pr__nfet_01v8[cgs] +save @m.xm1.msky130_fd_pr__nfet_01v8[cgd] +save @m.xm1.msky130_fd_pr__nfet_01v8[cgb] + +DC VGS 0 1.8 0.01 +plot @m.xm1.msky130_fd_pr__pfet_01v8[id] +.endc +"} +C {vsource.sym} 460 -40 0 0 {name=VDD value=1.8} +C {gnd.sym} 460 80 0 0 {name=l1 lab=GND} +C {gnd.sym} 370 170 0 0 {name=l2 lab=GND} +C {vsource.sym} 280 -40 0 0 {name=VGS value=0.6} +C {vsource.sym} 370 110 0 0 {name=VDS value=0.9} +C {netlist_not_shown.sym} 70 -100 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/ss.spice + + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {sky130_fd_pr/pfet_01v8.sym} 350 20 0 0 {name=M1 +L=0.15 +W=10 +nf=10 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +}
diff --git a/xschem/src/basic_test/gm_id_nmos.sch b/xschem/src/basic_test/gm_id_nmos.sch new file mode 100644 index 0000000..710d160 --- /dev/null +++ b/xschem/src/basic_test/gm_id_nmos.sch
@@ -0,0 +1,94 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -200 -1590 -140 -1590 { lab=#net1} +N -200 -1530 -100 -1530 { lab=GND} +N -100 -1560 -100 -1530 { lab=GND} +N -100 -1590 -100 -1560 { lab=GND} +N -100 -1680 -100 -1620 { lab=vds} +N -100 -1680 -10 -1680 { lab=vds} +N -10 -1620 -10 -1530 { lab=GND} +N -100 -1530 -10 -1530 { lab=GND} +C {vsource.sym} -10 -1650 0 0 {name=VDS value=0.9} +C {gnd.sym} -130 -1530 0 0 {name=l1 lab=GND} +C {code_shown.sym} -770 -1610 0 0 {name=s1 only_toplevel=false value=" +.param L=3 +.param W=5*L +.op +.control +let run = 300 +save @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gm] +save @m.xm1.msky130_fd_pr__nfet_01v8_lvt[id] +save @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gds] +save @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgs] +save @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgb] +save @m.xm1.msky130_fd_pr__nfet_01v8_lvt[cgd] +save @m.xm1.msky130_fd_pr__nfet_01v8_lvt[vth] +DC VGS 0 1.8 0.01 +plot @m.xm1.msky130_fd_pr__nfet_01v8_lvt[vth] +set filetype=ascii +write /home/eda/xschem/xschem_library/src/basic_test/data_nmos_lvt/data_\{$&run\}.raw + +.endc +"} +C {lab_wire.sym} -50 -1680 0 0 {name=l2 sig_type=std_logic lab=vds} +C {netlist_not_shown.sym} -470 -1710 0 0 {name=TT_MODELS +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" + +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_03v3_nvt/sky130_fd_pr__nfet_03v3_nvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_nfet_01v8/sky130_fd_pr__esd_nfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_pfet_g5v0d10v5/sky130_fd_pr__esd_pfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d16v0/sky130_fd_pr__pfet_g5v0d16v0__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d10v5/sky130_fd_pr__nfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d16v0/sky130_fd_pr__nfet_g5v0d16v0__tt_discrete.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_nfet_g5v0d10v5/sky130_fd_pr__esd_nfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/nonfet.spice +* Mismatch parameters +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d10v5/sky130_fd_pr__nfet_g5v0d10v5__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_03v3_nvt/sky130_fd_pr__nfet_03v3_nvt__mismatch.corner.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice +* All models +.include \\\\$::SKYWATER_MODELS\\\\/models/all.spice +* Corner +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/rf.spice +" +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -120 -1590 0 0 {name=M1 +L=L +W=W +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {vsource.sym} -200 -1560 0 0 {name=VGS value=0.7}
diff --git a/xschem/src/basic_test/gm_id_pmos.sch b/xschem/src/basic_test/gm_id_pmos.sch new file mode 100644 index 0000000..cca58f0 --- /dev/null +++ b/xschem/src/basic_test/gm_id_pmos.sch
@@ -0,0 +1,100 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -60 -1680 -60 -1620 { lab=#net1} +N 30 -1620 30 -1530 { lab=GND} +N -60 -1620 -60 -1610 { lab=#net1} +N -60 -1590 -30 -1590 { lab=#net1} +N -30 -1640 -30 -1590 { lab=#net1} +N -60 -1640 -30 -1640 { lab=#net1} +N -60 -1560 -60 -1530 { lab=#net2} +N -60 -1470 -60 -1440 { lab=GND} +N -60 -1680 30 -1680 { lab=#net1} +N -150 -1680 -50 -1680 { lab=#net1} +N -150 -1620 -150 -1590 { lab=#net3} +N -150 -1590 -100 -1590 { lab=#net3} +C {netlist_not_shown.sym} -470 -1750 0 0 {name=TT_MODELS +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" + +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_03v3_nvt/sky130_fd_pr__nfet_03v3_nvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_nfet_01v8/sky130_fd_pr__esd_nfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_pfet_g5v0d10v5/sky130_fd_pr__esd_pfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d16v0/sky130_fd_pr__pfet_g5v0d16v0__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d10v5/sky130_fd_pr__nfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d16v0/sky130_fd_pr__nfet_g5v0d16v0__tt_discrete.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_nfet_g5v0d10v5/sky130_fd_pr__esd_nfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/nonfet.spice +* Mismatch parameters +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d10v5/sky130_fd_pr__nfet_g5v0d10v5__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_03v3_nvt/sky130_fd_pr__nfet_03v3_nvt__mismatch.corner.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice +* All models +.include \\\\$::SKYWATER_MODELS\\\\/models/all.spice +* Corner +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/rf.spice +" +} +C {vsource.sym} 30 -1650 0 0 {name=VDD value=1.8} +C {gnd.sym} 30 -1530 0 0 {name=l1 lab=GND} +C {code_shown.sym} -730 -1610 0 0 {name=s1 only_toplevel=false value=" +.option SCALE=1e-6 +.param L=5 +.param W=5*L +.control +let run = 500 +save @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gm] +save @m.xm1.msky130_fd_pr__pfet_01v8_lvt[id] +save @m.xm1.msky130_fd_pr__pfet_01v8_lvt[gds] +save @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgs] +save @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgb] +save @m.xm1.msky130_fd_pr__pfet_01v8_lvt[cgd] +save @m.xm1.msky130_fd_pr__pfet_01v8_lvt[vth] +DC VGS 0 1.8 0.01 +*op +plot @m.xm1.msky130_fd_pr__pfet_01v8_lvt[vth] +set filetype=ascii +write /home/eda/xschem/xschem_library/src/basic_test/data_pmos_lvt/data_\{$&run\}.raw + +.endc +"} +C {gnd.sym} -60 -1440 0 0 {name=l2 lab=GND} +C {sky130_fd_pr/pfet_01v8_lvt.sym} -80 -1590 0 0 {name=M1 +L=L +W=W +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {vsource.sym} -150 -1650 0 0 {name=VGS value=0.6} +C {vsource.sym} -60 -1500 0 0 {name=VDS value=0.9}
diff --git a/xschem/src/behavior_mdl/OTA.spice b/xschem/src/behavior_mdl/OTA.spice new file mode 100644 index 0000000..1c94366 --- /dev/null +++ b/xschem/src/behavior_mdl/OTA.spice
@@ -0,0 +1,3 @@ +.subckt OTA inp inn outp outn +Gota outp outn inp inn 0.1 +.ends
diff --git a/xschem/src/behavior_mdl/OTA.sym b/xschem/src/behavior_mdl/OTA.sym new file mode 100644 index 0000000..06d7edb --- /dev/null +++ b/xschem/src/behavior_mdl/OTA.sym
@@ -0,0 +1,26 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 90 -60 90 60 {} +L 4 90 60 170 30 {} +L 4 170 -30 170 30 {} +L 4 90 -60 170 -30 {} +B 5 87.5 -32.5 92.5 -27.5 {name=inp +dir=inout} +B 5 87.5 27.5 92.5 32.5 {name=inn +dir=inout} +B 5 167.5 -22.5 172.5 -17.5 {name=outp +dir=inout} +B 5 167.5 17.5 172.5 22.5 {name=outn +dir=inout} +T {inp} 100 -30 0 0 0.2 0.2 {} +T {inn} 100 20 0 0 0.2 0.2 {} +T {outp} 140 -30 0 0 0.2 0.2 {} +T {outn} 140 10 0 0 0.2 0.2 {} +T {OTA} 110 -10 0 0 0.3 0.3 {}
diff --git a/xschem/src/behavior_mdl/OTA_test.sch b/xschem/src/behavior_mdl/OTA_test.sch new file mode 100644 index 0000000..2e45d19 --- /dev/null +++ b/xschem/src/behavior_mdl/OTA_test.sch
@@ -0,0 +1,104 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -120 410 -120 440 { lab=vdd} +N -350 410 -350 440 { lab=vin} +N 290 270 290 300 { lab=GND} +N 150 270 230 270 { lab=v1} +N -70 270 -40 270 { lab=vin} +N 320 340 380 340 { lab=out} +N -220 270 -180 270 { lab=vin} +N 290 200 290 230 { lab=vdd} +N 220 230 230 230 { lab=vbias} +N 110 190 160 190 { lab=vbias} +N 220 190 220 230 { lab=vbias} +N 40 270 150 270 { lab=v1} +N 20 270 40 270 { lab=v1} +N 110 320 110 340 { lab=v1} +N 110 270 110 320 { lab=v1} +N 380 250 380 260 { lab=out} +N 380 320 380 340 { lab=out} +N 380 260 380 320 { lab=out} +N 210 340 260 340 { lab=v1} +N 150 340 210 340 { lab=v1} +N 110 340 150 340 { lab=v1} +N -120 500 -120 530 { lab=vbias} +N -120 590 -120 630 { lab=GND} +N 340 250 380 250 { lab=out} +N 160 190 220 190 { lab=vbias} +N -120 270 -70 270 { lab=vin} +N -180 270 -120 270 { lab=vin} +C {vsource.sym} -120 470 0 0 {name=V2 value=0.9} +C {gnd.sym} -120 630 0 0 {name=l8 lab=GND} +C {lab_wire.sym} -120 420 0 0 {name=l9 sig_type=std_logic lab=vdd} +C {vsource.sym} -350 470 0 0 {name=V4 value="pulse(0.9 0.95 0 1n 1n 1u 2u 0)"} +C {gnd.sym} -350 500 0 0 {name=l10 lab=GND} +C {lab_wire.sym} -350 420 0 0 {name=l11 sig_type=std_logic lab=vin} +C {netlist_not_shown.sym} -310 -110 0 0 {name=s3 only_toplevel=false value=" +.include /home/eda/xschem/xschem_library/src/behavior_mdl/comparator.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/switch.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/integrator_feedback.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/integrator_input.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/adder.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/triang.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/ideal_amp.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/limiter.spice +"} +C {code_shown.sym} -400 20 0 0 {name=s4 only_toplevel=false value=" +.control +save all +op +*ac dec 10000 1 100G +tran 10n 10m +*linearize V(audio) +*linearize V(out) +*fft V(out) +*fft V(audio) +*plot mag(V(audio)) +*plot mag(V(out)) +*fourier 5k V(out) +*fourier 5k V(audio) +write behavior.raw + +.endc + + +"} +C {lab_wire.sym} -210 270 0 1 {name=l12 sig_type=std_logic lab=vin} +C {res.sym} -10 270 1 0 {name=R5 +value=100k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 290 210 0 0 {name=l19 sig_type=std_logic lab=vdd} +C {gnd.sym} 290 300 0 0 {name=l20 lab=GND} +C {capa.sym} 290 340 1 0 {name=C2 +m=1 +value=10p +footprint=1206 +device="ceramic capacitor"} +C {netlist_not_shown.sym} -160 -100 0 0 {name=TT_MODELS2 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice + + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {lab_wire.sym} 120 190 0 0 {name=l33 sig_type=std_logic lab=vbias} +C {src/behavior_mdl/ideal_amp.sym} 370 400 0 0 {name=x4} +C {vsource.sym} -120 560 0 0 {name=V7 value=0.9} +C {lab_wire.sym} -120 520 0 0 {name=l38 sig_type=std_logic lab=vbias} +C {lab_wire.sym} 380 250 0 0 {name=l1 sig_type=std_logic lab=out} +C {lab_wire.sym} 170 270 0 0 {name=l2 sig_type=std_logic lab=v1}
diff --git a/xschem/src/behavior_mdl/adder.spice b/xschem/src/behavior_mdl/adder.spice new file mode 100644 index 0000000..76ff9df --- /dev/null +++ b/xschem/src/behavior_mdl/adder.spice
@@ -0,0 +1,3 @@ +.subckt adder in1 in2 out gnd +Badd out gnd V=V(in1)-V(in2) +.ends
diff --git a/xschem/src/behavior_mdl/adder.sym b/xschem/src/behavior_mdl/adder.sym new file mode 100644 index 0000000..11233f4 --- /dev/null +++ b/xschem/src/behavior_mdl/adder.sym
@@ -0,0 +1,28 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 80 -30 80 50 {} +L 4 80 50 190 50 {} +L 4 190 -30 190 50 {} +L 4 80 -30 190 -30 {} +L 4 90 -10 110 -10 {} +L 4 100 -20 100 0 {} +L 4 90 30 110 30 {} +L 4 190 10 210 10 {} +L 4 130 50 130 70 {} +L 4 60 -10 80 -10 {} +L 4 60 30 80 30 {} +B 5 57.5 -12.5 62.5 -7.5 {name=in1 +dir=inout} +B 5 57.5 27.5 62.5 32.5 {name=in2 +dir=inout} +B 5 207.5 7.5 212.5 12.5 {name=out +dir=inout} +B 5 127.5 67.5 132.5 72.5 {name=gnd +dir=inout}
diff --git a/xschem/src/behavior_mdl/behavior_mdl.sch b/xschem/src/behavior_mdl/behavior_mdl.sch new file mode 100644 index 0000000..6aa29a1 --- /dev/null +++ b/xschem/src/behavior_mdl/behavior_mdl.sch
@@ -0,0 +1,152 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 290 80 350 80 { lab=error1} +N -150 220 -150 250 { lab=vbias} +N -90 220 -90 250 { lab=vdd} +N 400 40 400 60 { lab=GND} +N 400 160 400 200 { lab=vdd} +N 400 40 420 40 { lab=GND} +N -30 220 -30 250 { lab=vpulse} +N 300 140 350 140 { lab=vtriang} +N -210 220 -210 250 { lab=vin} +N 450 110 470 110 { lab=vcmp} +N 470 110 470 160 { lab=vcmp} +N 470 160 530 160 { lab=vcmp} +N 470 20 470 110 { lab=vcmp} +N 470 20 530 20 { lab=vcmp} +N 540 50 540 130 { lab=out} +N 540 -30 540 -10 { lab=vdd} +N 540 190 540 200 { lab=GND} +N 540 90 580 90 { lab=out} +N 550 20 570 20 { lab=vbias} +N 550 160 570 160 { lab=vbias} +N 580 90 600 90 { lab=out} +N 290 50 290 80 { lab=error1} +N -60 30 -60 50 { lab=input} +N -60 30 -0 30 { lab=input} +N -20 -90 10 -90 { lab=feedback} +N -20 -90 -20 70 { lab=feedback} +N -20 70 0 70 { lab=feedback} +N 150 50 290 50 { lab=error1} +N 230 300 280 300 { lab=vpulse} +N 490 300 550 300 { lab=vtriang} +N 870 90 910 90 { lab=audio} +N 910 90 910 100 { lab=audio} +N 910 90 1000 90 { lab=audio} +N 1000 90 1000 100 { lab=audio} +N 910 160 1000 160 { lab=GND} +N 790 90 810 90 { lab=#net1} +N -370 210 -370 240 { lab=v1} +N -300 210 -300 240 { lab=v2} +N 220 -90 250 -90 { lab=#net2} +N 400 -110 600 -110 { lab=out} +N 330 -30 330 -10 { lab=GND} +N 400 -70 450 -70 { lab=vbias} +N 610 -110 610 90 { lab=out} +N 600 -110 610 -110 { lab=out} +N -510 30 -450 30 { lab=vin} +N -300 50 -270 50 { lab=#net3} +N -490 70 -450 70 { lab=vbias} +N -380 110 -380 130 { lab=GND} +N 610 70 640 70 { lab=out} +N 600 90 610 90 { lab=out} +N 620 110 640 110 { lab=vbias} +N 710 150 710 170 { lab=GND} +C {src/behavior_mdl/comparator.sym} 310 120 2 1 {name=x2} +C {vsource.sym} -150 280 0 0 {name=V2 value=0.9} +C {vsource.sym} -90 280 0 0 {name=V3 value=1.8} +C {vsource.sym} -30 280 0 0 {name=V4 value="pulse(-1.8 1.8 0 0.1n 0.1n 1u 2u 0)"} +C {gnd.sym} -150 310 0 0 {name=l1 lab=GND} +C {gnd.sym} -90 310 0 0 {name=l2 lab=GND} +C {gnd.sym} -30 310 0 0 {name=l3 lab=GND} +C {lab_wire.sym} -150 230 0 0 {name=l4 sig_type=std_logic lab=vbias} +C {lab_wire.sym} -90 230 0 0 {name=l5 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 400 200 0 0 {name=l7 sig_type=std_logic lab=vdd} +C {gnd.sym} 420 40 0 0 {name=l8 lab=GND} +C {lab_wire.sym} -30 230 0 0 {name=l9 sig_type=std_logic lab=vpulse} +C {lab_wire.sym} 300 140 0 0 {name=l10 sig_type=std_logic lab=vtriang} +C {vsource.sym} -210 280 0 0 {name=V1 value="sin(0.9 0.1 5k)"} +C {gnd.sym} -210 310 0 0 {name=l13 lab=GND} +C {lab_wire.sym} -210 230 0 0 {name=l14 sig_type=std_logic lab=vin} +C {netlist_not_shown.sym} -470 -220 0 0 {name=s1 only_toplevel=false value=" +.include /home/eda/xschem/xschem_library/src/behavior_mdl/OTA.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/comparator.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/switch.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/integrator_feedback.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/integrator_input.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/adder.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/triang.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/ideal_amp.spice +"} +C {code_shown.sym} -770 -90 0 0 {name=s2 only_toplevel=false value=" +.control +save all +tran 9n 10m +*linearize V(audio) +*linearize V(out) +*fft V(out) +*fft V(audio) +*plot mag(V(audio)) +*plot mag(V(out)) +fourier 5k V(out) +fourier 5k V(audio) + +.endc + + +"} +C {src/behavior_mdl/switch.sym} 560 190 3 0 {name=x1} +C {src/behavior_mdl/switch.sym} 520 50 1 1 {name=x3} +C {lab_wire.sym} 570 90 0 1 {name=l15 sig_type=std_logic lab=out} +C {lab_wire.sym} 560 20 0 1 {name=l16 sig_type=std_logic lab=vbias} +C {lab_wire.sym} 560 160 0 1 {name=l17 sig_type=std_logic lab=vbias} +C {lab_wire.sym} 470 70 0 1 {name=l18 sig_type=std_logic lab=vcmp} +C {lab_wire.sym} -500 30 0 1 {name=l6 sig_type=std_logic lab=vin} +C {lab_wire.sym} 220 50 0 0 {name=l21 sig_type=std_logic lab=error1} +C {src/behavior_mdl/integrator_feedback.sym} 340 -70 0 1 {name=x4} +C {src/behavior_mdl/integrator_input.sym} -220 50 0 0 {name=x5} +C {src/behavior_mdl/adder.sym} -60 40 0 0 {name=x6} +C {gnd.sym} 70 110 0 0 {name=l19 lab=GND} +C {src/behavior_mdl/triang.sym} 350 280 0 0 {name=x7} +C {lab_wire.sym} 230 300 0 0 {name=l20 sig_type=std_logic lab=vpulse} +C {lab_wire.sym} 540 300 0 0 {name=l22 sig_type=std_logic lab=vtriang} +C {lab_wire.sym} -20 -70 0 0 {name=l23 sig_type=std_logic lab=feedback} +C {lab_wire.sym} -30 30 0 0 {name=l24 sig_type=std_logic lab=input} +C {ind.sym} 840 90 1 0 {name=L1 +m=1 +value=10u +footprint=1206 +device=inductor} +C {capa.sym} 910 130 0 0 {name=C1 +m=1 +value=1.2u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} 1000 130 0 0 {name=R2 +value=4 +footprint=1206 +device=resistor +m=1} +C {gnd.sym} 960 160 0 0 {name=l29 lab=GND} +C {lab_wire.sym} 960 90 0 1 {name=l30 sig_type=std_logic lab=audio} +C {vsource.sym} -370 270 0 0 {name=V5 value=0.9} +C {vsource.sym} -300 270 0 0 {name=V6 value=-0.9} +C {gnd.sym} -370 300 0 0 {name=l25 lab=GND} +C {gnd.sym} -300 300 0 0 {name=l26 lab=GND} +C {lab_wire.sym} -370 220 0 0 {name=l27 sig_type=std_logic lab=v1} +C {lab_wire.sym} -300 220 0 0 {name=l28 sig_type=std_logic lab=v2} +C {src/behavior_mdl/adder.sym} 460 -100 0 1 {name=x8} +C {gnd.sym} 330 -10 0 0 {name=l31 lab=GND} +C {lab_wire.sym} 450 -70 0 0 {name=l32 sig_type=std_logic lab=vbias} +C {lab_wire.sym} 540 -30 0 0 {name=l11 sig_type=std_logic lab=vdd} +C {gnd.sym} 540 200 0 0 {name=l12 lab=GND} +C {src/behavior_mdl/adder.sym} -510 40 0 0 {name=x9} +C {lab_wire.sym} -460 70 0 0 {name=l33 sig_type=std_logic lab=vbias} +C {gnd.sym} -380 130 0 0 {name=l34 lab=GND} +C {src/behavior_mdl/adder.sym} 580 80 0 0 {name=x10} +C {lab_wire.sym} 620 110 0 0 {name=l35 sig_type=std_logic lab=vbias} +C {gnd.sym} 710 170 0 0 {name=l36 lab=GND}
diff --git a/xschem/src/behavior_mdl/behavior_model_fine.sch b/xschem/src/behavior_mdl/behavior_model_fine.sch new file mode 100644 index 0000000..ca28219 --- /dev/null +++ b/xschem/src/behavior_mdl/behavior_model_fine.sch
@@ -0,0 +1,429 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -1410 240 -1310 240 { lab=vpulse_p} +N -1930 390 -1930 420 { lab=vref} +N -1930 480 -1930 520 { lab=GND} +N -1160 50 -1100 50 { lab=vref} +N -1170 90 -1100 90 { lab=feedback_p} +N -1040 20 -1040 50 { lab=vdd} +N -1040 90 -1040 130 { lab=GND} +N -720 100 -690 100 { lab=vcmp_p} +N -40 -20 -40 0 { lab=#net1} +N -40 200 -40 210 { lab=GND} +N -30 100 -20 100 { lab=out_p} +N -1290 -90 -920 -90 { lab=feedback_p} +N -1310 90 -1290 90 { lab=feedback_p} +N -1420 90 -1370 90 { lab=vin_p} +N -770 20 -770 50 { lab=vdd} +N -770 150 -770 180 { lab=GND} +N -1160 450 -1100 450 { lab=vref} +N -860 530 -820 530 { lab=vtriang} +N -1170 490 -1100 490 { lab=feedback_n} +N -990 470 -950 470 { lab=error_n} +N -1040 420 -1040 450 { lab=vdd} +N -1040 490 -1040 530 { lab=GND} +N -950 470 -860 470 { lab=error_n} +N -40 600 -40 610 { lab=GND} +N -1310 490 -1290 490 { lab=feedback_n} +N -1160 590 -1090 590 { lab=feedback_n} +N -1160 490 -1160 590 { lab=feedback_n} +N -1030 590 -960 590 { lab=error_n} +N -960 470 -960 590 { lab=error_n} +N -1420 490 -1370 490 { lab=vin_n} +N -770 420 -770 450 { lab=vdd} +N -770 550 -770 580 { lab=GND} +N 80 100 160 100 { lab=audio_p} +N 100 100 100 110 { lab=audio_p} +N 100 170 100 190 { lab=GND} +N 100 570 100 590 { lab=GND} +N -40 270 -40 290 { lab=GND} +N -40 670 -40 690 { lab=GND} +N -860 470 -820 470 { lab=error_n} +N -1440 490 -1420 490 { lab=vin_n} +N -1440 90 -1420 90 { lab=vin_p} +N -40 100 -30 100 { lab=out_p} +N -110 30 -80 30 { lab=vp_p} +N -110 170 -80 170 { lab=vn_p} +N -720 500 -710 500 { lab=vcmp_n} +N -40 60 -40 140 { lab=out_p} +N -40 170 -20 170 { lab=GND} +N -20 170 -20 210 { lab=GND} +N -40 210 -20 210 { lab=GND} +N -40 30 -20 30 { lab=#net1} +N -20 -10 -20 30 { lab=#net1} +N -40 -10 -20 -10 { lab=#net1} +N -40 460 -40 540 { lab=out_n} +N -40 510 -30 510 { lab=out_n} +N -40 570 -20 570 { lab=GND} +N -20 570 -20 620 { lab=GND} +N -40 620 -20 620 { lab=GND} +N -40 380 -40 400 { lab=#net1} +N -40 430 -20 430 { lab=#net1} +N -20 390 -20 430 { lab=#net1} +N -40 390 -20 390 { lab=#net1} +N -1840 390 -1840 420 { lab=vdd} +N -1840 480 -1840 510 { lab=GND} +N -40 610 -40 620 { lab=GND} +N -140 30 -140 80 { lab=vp_p} +N -140 30 -110 30 { lab=vp_p} +N -140 120 -140 170 { lab=vn_p} +N -140 170 -110 170 { lab=vn_p} +N -20 100 20 100 { lab=out_p} +N -560 40 -560 60 { lab=vdd} +N -560 140 -560 160 { lab=GND} +N -860 -90 10 -90 { lab=out_p} +N 10 -90 10 100 { lab=out_p} +N -440 480 -440 490 { lab=vp_n} +N -440 510 -440 520 { lab=vn_n} +N -140 430 -140 480 { lab=vp_n} +N -140 520 -140 570 { lab=vn_n} +N -560 440 -560 460 { lab=vdd} +N -560 540 -560 560 { lab=GND} +N -710 500 -690 500 { lab=vcmp_n} +N -140 430 -80 430 { lab=vp_n} +N -140 570 -80 570 { lab=vn_n} +N -20 510 10 510 { lab=out_n} +N -30 510 -20 510 { lab=out_n} +N 70 510 100 510 { lab=audio_n} +N 160 100 160 310 { lab=audio_p} +N 160 310 160 320 { lab=audio_p} +N 160 380 160 510 { lab=audio_n} +N 100 510 160 510 { lab=audio_n} +N -990 70 -960 70 { lab=error_p} +N -960 70 -820 70 { lab=error_p} +N -1290 90 -1170 90 { lab=feedback_p} +N -1290 -90 -1290 90 { lab=feedback_p} +N -1160 90 -1160 150 { lab=feedback_p} +N -1100 150 -980 150 { lab=error_p} +N -980 70 -980 150 { lab=error_p} +N -1100 240 -890 240 { lab=vtriang} +N -890 130 -890 240 { lab=vtriang} +N -890 130 -820 130 { lab=vtriang} +N -1290 490 -1170 490 { lab=feedback_n} +N -1450 90 -1440 90 { lab=vin_p} +N -1450 490 -1440 490 { lab=vin_n} +N -1570 230 -1570 250 { lab=vdd} +N -1570 330 -1570 350 { lab=GND} +N -1450 90 -1450 280 { lab=vin_p} +N -1450 300 -1450 490 { lab=vin_n} +N -890 240 -890 520 { lab=vtriang} +N -890 520 -890 530 { lab=vtriang} +N -890 530 -860 530 { lab=vtriang} +N -210 -50 -210 210 { lab=#net1} +N -210 -50 -40 -50 { lab=#net1} +N -40 -50 -40 -20 { lab=#net1} +N -210 190 -140 190 { lab=#net1} +N -140 190 -140 380 { lab=#net1} +N -140 380 -40 380 { lab=#net1} +N -40 620 -40 670 { lab=GND} +N -40 210 -40 270 { lab=GND} +N -1820 300 -1690 300 { lab=#net2} +N -1720 320 -1690 320 { lab=vref} +N -1720 280 -1690 280 { lab=vbias2} +N -1720 260 -1690 260 { lab=vbias1} +N -1760 680 -1760 760 { lab=v1} +N -1760 710 -1690 710 { lab=v1} +N -1760 600 -1760 620 { lab=vdd} +N -1760 820 -1760 830 { lab=GND} +N -1760 790 -1760 820 { lab=GND} +N -1720 790 -1680 790 { lab=v1} +N -1690 710 -1690 790 { lab=v1} +N -1680 790 -1640 790 { lab=v1} +N -1610 830 -1580 830 { lab=GND} +N -1590 830 -1590 860 { lab=GND} +N -1640 830 -1610 830 { lab=GND} +N -1580 830 -1550 830 { lab=GND} +N -1670 830 -1670 880 { lab=vbias1} +N -1520 830 -1520 880 { lab=vbias2} +N -1640 790 -1550 790 { lab=v1} +N 0 510 -0 790 { lab=out_n} +N -830 790 -0 790 { lab=out_n} +N -1250 790 -890 790 { lab=feedback_n} +N -1250 490 -1250 790 { lab=feedback_n} +N -440 480 -140 480 { lab=vp_n} +N -440 520 -140 520 { lab=vn_n} +N -440 90 -140 90 { lab=vp_p} +N -140 80 -140 90 { lab=vp_p} +N -440 110 -140 110 { lab=vn_p} +N -140 110 -140 120 { lab=vn_p} +C {gnd.sym} -1930 520 0 0 {name=l2 lab=GND} +C {vsource.sym} -1820 330 0 0 {name=V1 value="sin(0.9 0.4 1k)"} +C {gnd.sym} -1820 360 0 0 {name=l13 lab=GND} +C {netlist_not_shown.sym} -2260 -290 0 0 {name=s1 only_toplevel=false value=" +.include /home/eda/xschem/xschem_library/src/behavior_mdl/comparator.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/switch.spice +*.include /home/eda/xschem/xschem_library/src/behavior_mdl/integrator_feedback.spice +*.include /home/eda/xschem/xschem_library/src/behavior_mdl/integrator_input.spice +*.include /home/eda/xschem/xschem_library/src/behavior_mdl/adder.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/triang.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/ideal_amp.spice +.include /home/eda/xschem/xschem_library/src/behavior_mdl/limiter.spice +"} +C {code_shown.sym} -2790 -180 0 0 {name=s2 only_toplevel=false value=" +.option VNTOL=1e-6 ABSTOL=5e-9 +.nodeset v(vin_p)=0.9 v(vin_n)=0.9 v(out_p)=0.9 v(out_n)=0.9 v(error_p)=0.9 v(error_n)=0.9 +*set the absolute voltage error tolerance and absolute current error tolerance +.control +save vtriang vin_p vin_n error_n error_p vcmp_n vcmp_p vp_p vn_p vp_n vn_n out_p out_n audio_p audio_n feedback_p feedback_n I(V4) I(V2) @r6[i] @r1[i] +tran 1n 10m 1m +*op +*linearize V(audio) +*linearize V(out) +*fft V(out) +*fft V(audio) +*plot mag(V(audio)) +*plot mag(V(out)) +let pout=@r6[i]*(V(audio_p)-V(audio_n)) +let pin=1.8*I(V2) +meas tran pload avg pout from=1m to=4m +meas tran p_supply avg pin from=1m to=4m +print pload/p_supply +set nfreqs=20 +fourier 1k V(audio_p)-V(audio_n) +write behavior_1k_04.raw + +.endc + + +"} +C {src/behavior_mdl/triang.sym} -1240 220 0 0 {name=x5} +C {gnd.sym} -1410 300 0 0 {name=l3 lab=GND} +C {lab_wire.sym} -1040 240 0 0 {name=l9 sig_type=std_logic lab=vtriang} +C {lab_wire.sym} -1350 240 0 0 {name=l20 sig_type=std_logic lab=vpulse_p} +C {vsource.sym} -1930 450 0 0 {name=V5 value=0.9} +C {lab_wire.sym} -1930 410 0 0 {name=l26 sig_type=std_logic lab=vref} +C {lab_wire.sym} -1420 90 0 1 {name=l1 sig_type=std_logic lab=vin_p} +C {src/behavior_mdl/ideal_amp.sym} -960 220 0 0 {name=x3} +C {lab_wire.sym} -1040 30 0 0 {name=l6 sig_type=std_logic lab=vdd} +C {gnd.sym} -1040 130 0 0 {name=l12 lab=GND} +C {src/behavior_mdl/comparator.sym} -860 90 0 0 {name=x1} +C {lab_wire.sym} -20 100 0 1 {name=l15 sig_type=std_logic lab=out_p} +C {ind.sym} 50 100 1 0 {name=L1 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 100 140 0 0 {name=C1 +m=1 +value=2.2u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} -890 -90 1 0 {name=R1 +value=200k +footprint=1206 +device=resistor +m=1} +C {res.sym} -1340 90 1 0 {name=R3 +value=200k +footprint=1206 +device=resistor +m=1} +C {capa.sym} -1130 150 1 0 {name=C2 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} -1290 0 0 0 {name=l18 sig_type=std_logic lab=feedback_p} +C {lab_wire.sym} -700 100 0 0 {name=l19 sig_type=std_logic lab=vcmp_p} +C {lab_wire.sym} -770 30 0 0 {name=l21 sig_type=std_logic lab=vdd} +C {gnd.sym} -770 180 0 0 {name=l22 lab=GND} +C {lab_wire.sym} -910 70 0 0 {name=l8 sig_type=std_logic lab=error_p} +C {lab_wire.sym} -1420 490 0 1 {name=l23 sig_type=std_logic lab=vin_n} +C {src/behavior_mdl/ideal_amp.sym} -960 620 0 0 {name=x6} +C {lab_wire.sym} -1040 430 0 0 {name=l24 sig_type=std_logic lab=vdd} +C {gnd.sym} -1040 530 0 0 {name=l25 lab=GND} +C {src/behavior_mdl/comparator.sym} -860 490 0 0 {name=x7} +C {res.sym} -860 790 1 0 {name=R4 +value=200k +footprint=1206 +device=resistor +m=1} +C {res.sym} -1340 490 1 0 {name=R5 +value=200k +footprint=1206 +device=resistor +m=1} +C {capa.sym} -1060 590 1 0 {name=C3 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} -770 430 0 0 {name=l38 sig_type=std_logic lab=vdd} +C {gnd.sym} -770 580 0 0 {name=l39 lab=GND} +C {ind.sym} 40 510 3 1 {name=L2 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 100 540 0 1 {name=C4 +m=1 +value=2.2u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} 160 350 2 0 {name=R6 +value=8 +footprint=1206 +device=resistor +m=1} +C {gnd.sym} 100 190 0 1 {name=l41 lab=GND} +C {gnd.sym} 100 590 0 0 {name=l42 lab=GND} +C {lab_wire.sym} -10 510 0 0 {name=l28 sig_type=std_logic lab=out_n} +C {lab_wire.sym} -900 470 0 0 {name=l29 sig_type=std_logic lab=error_n} +C {lab_wire.sym} -1250 680 0 0 {name=l30 sig_type=std_logic lab=feedback_n} +C {lab_wire.sym} -710 500 0 1 {name=l40 sig_type=std_logic lab=vcmp_n} +C {lab_wire.sym} 110 100 0 1 {name=l43 sig_type=std_logic lab=audio_p} +C {lab_wire.sym} 110 510 0 1 {name=l44 sig_type=std_logic lab=audio_n} +C {gnd.sym} -40 290 0 0 {name=l4 lab=GND} +C {vsource.sym} -1410 270 0 0 {name=V11 value="pulse(-1.8 1.8 0 0.1n 0.1n 1u 2u 0)"} +C {gnd.sym} -40 690 0 1 {name=l10 lab=GND} +C {sky130_fd_pr/pfet_01v8.sym} -60 30 0 0 {name=M10 +L=0.15 +W=6000 +nf=200 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} -60 170 0 0 {name=M2 +L=0.15 +W=1200 +nf=100 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} -60 430 0 0 {name=M3 +L=0.15 +W=6000 +nf=200 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} -60 570 0 0 {name=M4 +L=0.15 +W=1200 +nf=100 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {vsource.sym} -1840 450 0 0 {name=V4 value=1.8} +C {lab_wire.sym} -1840 400 0 0 {name=l16 sig_type=std_logic lab=vdd} +C {gnd.sym} -1840 510 0 0 {name=l5 lab=GND} +C {src/dead_time/dead_time.sym} -590 100 0 0 {name=x2} +C {lab_wire.sym} -560 40 0 0 {name=l17 sig_type=std_logic lab=vdd} +C {gnd.sym} -560 160 0 0 {name=l32 lab=GND} +C {src/dead_time/dead_time.sym} -590 500 0 0 {name=x8} +C {lab_wire.sym} -560 440 0 0 {name=l34 sig_type=std_logic lab=vdd} +C {gnd.sym} -560 560 0 0 {name=l37 lab=GND} +C {lab_wire.sym} -120 30 0 0 {name=l49 sig_type=std_logic lab=vp_p} +C {lab_wire.sym} -100 170 0 0 {name=l50 sig_type=std_logic lab=vn_p} +C {lab_wire.sym} -110 430 0 0 {name=l51 sig_type=std_logic lab=vp_n} +C {lab_wire.sym} -100 570 0 0 {name=l52 sig_type=std_logic lab=vn_n} +C {src/S_to_D/S_to_D.sym} -1540 290 0 0 {name=x11} +C {lab_wire.sym} -1570 240 0 0 {name=l57 sig_type=std_logic lab=vdd} +C {gnd.sym} -1570 350 0 0 {name=l58 lab=GND} +C {vsource.sym} -210 240 0 0 {name=V2 value=1.8} +C {gnd.sym} -210 270 0 0 {name=l11 lab=GND} +C {isource.sym} -1760 650 0 0 {name=I0 value=15u} +C {lab_wire.sym} -1760 600 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} -1760 830 0 0 {name=l14 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -1740 790 0 1 {name=M5 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -1640 810 3 1 {name=M6 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} -1710 710 0 1 {name=l62 sig_type=std_logic lab=v1} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -1550 810 1 0 {name=M7 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} -1590 860 0 0 {name=l54 lab=GND} +C {lab_wire.sym} -1670 870 0 0 {name=l36 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} -1520 880 0 0 {name=l66 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} -1710 260 0 0 {name=l45 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} -1710 280 0 0 {name=l46 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} -1710 320 0 0 {name=l47 sig_type=std_logic lab=vref} +C {lab_wire.sym} -1140 450 0 0 {name=l7 sig_type=std_logic lab=vref} +C {lab_wire.sym} -1140 50 0 0 {name=l27 sig_type=std_logic lab=vref} +C {netlist_not_shown.sym} -2060 -280 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice +.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_post.spice +.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_post.spice + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +}
diff --git a/xschem/src/behavior_mdl/comparator.spice b/xschem/src/behavior_mdl/comparator.spice new file mode 100644 index 0000000..5e11fcc --- /dev/null +++ b/xschem/src/behavior_mdl/comparator.spice
@@ -0,0 +1,3 @@ +.subckt comparator inp inn out vdd gnd +Bcmp out gnd V=((V(inp)-V(inn))*700 > 0.9? 1.8 : (V(inp)-V(inn))*700 <-0.9 ? 0 : ((V(inp)-V(inn))*700)+0.9) +.ends
diff --git a/xschem/src/behavior_mdl/comparator.sym b/xschem/src/behavior_mdl/comparator.sym new file mode 100644 index 0000000..a1c5fc5 --- /dev/null +++ b/xschem/src/behavior_mdl/comparator.sym
@@ -0,0 +1,27 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 40 -50 40 70 {} +L 4 40 -50 140 10 {} +L 4 40 70 140 10 {} +L 4 90 -40 90 -20 {} +L 4 90 40 90 60 {} +B 5 37.5 -22.5 42.5 -17.5 {name=inp +dir=inout} +B 5 37.5 37.5 42.5 42.5 {name=inn +dir=inout} +B 5 137.5 7.5 142.5 12.5 {name=out +dir=inout} +B 5 87.5 -42.5 92.5 -37.5 {name=vdd +dir=inout} +B 5 87.5 57.5 92.5 62.5 {name=gnd +dir=inout} +T {inp} 50 -20 0 0 0.2 0.2 {} +T {inn} 50 30 0 0 0.2 0.2 {} +T {CMP} 70 0 0 0 0.3 0.3 {}
diff --git a/xschem/src/behavior_mdl/ideal_amp.spice b/xschem/src/behavior_mdl/ideal_amp.spice new file mode 100644 index 0000000..375acb9 --- /dev/null +++ b/xschem/src/behavior_mdl/ideal_amp.spice
@@ -0,0 +1,26 @@ +.subckt ideal_amp inp inn out vdd gnd +*.model limiter ilimit(in_offset=0 gain=735 r_out_source=1 +*+ r_out_sink=1 i_limit_source=1e-3 +*+ i_limit_sink=10e-3 v_pwr_range=0.2 +*+ i_source_range=1e-6 i_sink_range=1e-6 +*+ r_out_domain=1e-6) +*.model amp gain(gain=735) +*Bsub sub gnd V=V(inp)-V(inn) +*aamp out_amp gnd amp +*alim sub vdd gnd out limiter + +*controlled limiter +.model climiter climit(in_offset=0 gain=700 upper_delta=0 ++ lower_delta=0 limit_range=0.1 fraction=FALSE) +Bsub sub gnd V=V(inp)-V(inn) +*Bvddnodc vpp gnd V=V(vdd)-0.9 +*Bgndnodc vnn gnd V=V(gnd)-0.9 +aamp sub vdd gnd out climiter + + + + +*.param gm=0.02 +*Bi out gnd V=V(sub)*1e3 +*Rout out gnd 1e10 +.ends
diff --git a/xschem/src/behavior_mdl/ideal_amp.sym b/xschem/src/behavior_mdl/ideal_amp.sym new file mode 100644 index 0000000..bd1265b --- /dev/null +++ b/xschem/src/behavior_mdl/ideal_amp.sym
@@ -0,0 +1,22 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -140 -190 -140 -110 {} +L 4 -140 -110 -30 -150 {} +L 4 -140 -190 -30 -150 {} +B 5 -142.5 -172.5 -137.5 -167.5 {name=inp dir=in } +B 5 -142.5 -132.5 -137.5 -127.5 {name=inn dir=in } +B 5 -32.5 -152.5 -27.5 -147.5 {name=out dir=out } +B 5 -82.5 -172.5 -77.5 -167.5 {name=vdd dir=inout } +B 5 -82.5 -132.5 -77.5 -127.5 {name=gnd dir=inout } +T {@symname} -111.5 -156 0 0 0.2 0.2 {} +T {@name} -55 -182 0 0 0.2 0.2 {} +T {vdd} -85 -164 0 1 0.2 0.2 {} +T {vp} -135 -174 0 0 0.2 0.2 {} +T {vn} -135 -134 0 0 0.2 0.2 {}
diff --git a/xschem/src/behavior_mdl/integrator_feedback.spice b/xschem/src/behavior_mdl/integrator_feedback.spice new file mode 100644 index 0000000..ec89942 --- /dev/null +++ b/xschem/src/behavior_mdl/integrator_feedback.spice
@@ -0,0 +1,5 @@ +.subckt integrator_feedback in out +.model int_fb int(in_offset=0 gain=500k out_lower_limit=-100 out_upper_limit=100 limit_range=1e-9 out_ic=0.9) + +aint in out int_fb +.ends
diff --git a/xschem/src/behavior_mdl/integrator_feedback.sym b/xschem/src/behavior_mdl/integrator_feedback.sym new file mode 100644 index 0000000..e0ba69a --- /dev/null +++ b/xschem/src/behavior_mdl/integrator_feedback.sym
@@ -0,0 +1,32 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 220 -60 220 20 {} +L 4 220 -60 300 -20 {} +L 4 220 20 300 -20 {} +L 4 300 -20 330 -20 {} +L 4 210 -20 220 -20 {} +L 4 190 -20 210 -20 {} +L 4 190 -30 190 -10 {} +L 4 150 -10 190 -10 {} +L 4 150 -30 150 -10 {} +L 4 150 -30 190 -30 {} +L 4 200 -80 200 -20 {} +L 4 200 -80 240 -80 {} +L 4 240 -90 240 -70 {} +L 4 250 -90 250 -70 {} +L 4 250 -80 310 -80 {} +L 4 310 -80 310 -20 {} +L 4 120 -20 150 -20 {} +B 5 117.5 -22.5 122.5 -17.5 {name=in +dir=inout} +B 5 327.5 -22.5 332.5 -17.5 {name=out +dir=inout} +T {RF} 160 -10 0 0 0.2 0.2 {} +T {CF} 240 -70 0 0 0.2 0.2 {}
diff --git a/xschem/src/behavior_mdl/integrator_input.sch b/xschem/src/behavior_mdl/integrator_input.sch new file mode 100644 index 0000000..13687e0 --- /dev/null +++ b/xschem/src/behavior_mdl/integrator_input.sch
@@ -0,0 +1,31 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {type=primitive +format="@name @pinlist @symname" +template="name=x1"} +E {} +L 4 50 -30 50 50 {} +L 4 50 -30 130 10 {} +L 4 50 50 130 10 {} +L 4 130 10 160 10 {} +L 4 40 10 50 10 {} +L 4 20 10 40 10 {} +L 4 20 0 20 20 {} +L 4 -20 20 20 20 {} +L 4 -20 0 -20 20 {} +L 4 -20 0 20 0 {} +L 4 30 -50 30 10 {} +L 4 30 -50 70 -50 {} +L 4 70 -60 70 -40 {} +L 4 80 -60 80 -40 {} +L 4 80 -50 140 -50 {} +L 4 140 -50 140 10 {} +L 4 -50 10 -20 10 {} +B 5 -52.5 7.5 -47.5 12.5 {name=in +dir=inout} +B 5 157.5 7.5 162.5 12.5 {name=out +dir=inout} +T {R1} -10 20 0 0 0.2 0.2 {} +T {CF} 70 -40 0 0 0.2 0.2 {}
diff --git a/xschem/src/behavior_mdl/integrator_input.spice b/xschem/src/behavior_mdl/integrator_input.spice new file mode 100644 index 0000000..707b91f --- /dev/null +++ b/xschem/src/behavior_mdl/integrator_input.spice
@@ -0,0 +1,6 @@ +.subckt integrator_input in out +.param R1=10k CF=20p +.model int_fb int(in_offset=0 gain=2e6 out_lower_limit=-100 out_upper_limit=100 limit_range=1e-9 out_ic=0.9) + +aint in out int_fb +.ends
diff --git a/xschem/src/behavior_mdl/integrator_input.sym b/xschem/src/behavior_mdl/integrator_input.sym new file mode 100644 index 0000000..8ff0feb --- /dev/null +++ b/xschem/src/behavior_mdl/integrator_input.sym
@@ -0,0 +1,32 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 50 -40 50 40 {} +L 4 50 -40 130 0 {} +L 4 50 40 130 0 {} +L 4 130 0 160 0 {} +L 4 40 0 50 0 {} +L 4 20 0 40 0 {} +L 4 20 -10 20 10 {} +L 4 -20 10 20 10 {} +L 4 -20 -10 -20 10 {} +L 4 -20 -10 20 -10 {} +L 4 30 -60 30 0 {} +L 4 30 -60 70 -60 {} +L 4 70 -70 70 -50 {} +L 4 80 -70 80 -50 {} +L 4 80 -60 140 -60 {} +L 4 140 -60 140 0 {} +L 4 -50 0 -20 0 {} +B 5 -52.5 -2.5 -47.5 2.5 {name=in +dir=inout} +B 5 157.5 -2.5 162.5 2.5 {name=out +dir=inout} +T {R1} -10 10 0 0 0.2 0.2 {} +T {CF} 70 -50 0 0 0.2 0.2 {}
diff --git a/xschem/src/behavior_mdl/limiter.spice b/xschem/src/behavior_mdl/limiter.spice new file mode 100644 index 0000000..48f9b9b --- /dev/null +++ b/xschem/src/behavior_mdl/limiter.spice
@@ -0,0 +1,3 @@ +.subckt limiter in out vdd gnd +Blim out gnd V=V(in)>V(vdd)?V(vdd):(V(in)<V(gnd)?V(gnd):V(in)) +.ends
diff --git a/xschem/src/behavior_mdl/limiter.sym b/xschem/src/behavior_mdl/limiter.sym new file mode 100644 index 0000000..c71e0be --- /dev/null +++ b/xschem/src/behavior_mdl/limiter.sym
@@ -0,0 +1,27 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 180 100 180 140 {} +L 4 180 140 220 140 {} +L 4 220 100 220 140 {} +L 4 180 100 220 100 {} +L 4 200 80 200 100 {} +L 4 160 120 180 120 {} +L 4 220 120 240 120 {} +L 4 200 140 200 160 {} +B 5 157.5 117.5 162.5 122.5 {name=in +dir=in} +B 5 237.5 117.5 242.5 122.5 {name=out +dir=out} +B 5 197.5 77.5 202.5 82.5 {name=vdd +dir=inout} +B 5 197.5 157.5 202.5 162.5 {name=gnd +dir=inout} +T {vdd} 190 100 0 0 0.2 0.2 {} +T {vin} 180 110 0 0 0.2 0.2 {}
diff --git a/xschem/src/behavior_mdl/switch.spice b/xschem/src/behavior_mdl/switch.spice new file mode 100644 index 0000000..30758ad --- /dev/null +++ b/xschem/src/behavior_mdl/switch.spice
@@ -0,0 +1,6 @@ +.subckt switch n1 n2 vcp vcn +.model switch1 sw vt=0 vh=0.1 ron=0.1 roff=10MEG +*threshold=0.9V, hysteresis=0.1V, ron=0.1ohm, roff=10meg +s1 n1 n2 vcp vcn switch1 OFF +*the switch is off during the period of hysteresis +.ends
diff --git a/xschem/src/behavior_mdl/switch.sym b/xschem/src/behavior_mdl/switch.sym new file mode 100644 index 0000000..1d16402 --- /dev/null +++ b/xschem/src/behavior_mdl/switch.sym
@@ -0,0 +1,21 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 0 -20 20 -20 {} +L 4 20 -20 40 -30 {} +L 4 40 -20 60 -20 {} +B 5 -2.5 -22.5 2.5 -17.5 {name=n1 +dir=inout} +B 5 57.5 -22.5 62.5 -17.5 {name=n2 +dir=inout} +B 5 27.5 -32.5 32.5 -27.5 {name=vcp +dir=inout} +B 5 27.5 -12.5 32.5 -7.5 {name=vcn +dir=inout} +T {0.9V} 40 -10 0 0 0.2 0.2 {}
diff --git a/xschem/src/behavior_mdl/triang.spice b/xschem/src/behavior_mdl/triang.spice new file mode 100644 index 0000000..fde1313 --- /dev/null +++ b/xschem/src/behavior_mdl/triang.spice
@@ -0,0 +1,4 @@ +.subckt triang in out +.model int_fb int(in_offset=0 gain=1e6 out_lower_limit=0 out_upper_limit=1.8 limit_range=1e-9 out_ic=0) +aint in out int_fb +.ends
diff --git a/xschem/src/behavior_mdl/triang.sym b/xschem/src/behavior_mdl/triang.sym new file mode 100644 index 0000000..911134a --- /dev/null +++ b/xschem/src/behavior_mdl/triang.sym
@@ -0,0 +1,30 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 30 -20 30 60 {} +L 4 30 -20 110 20 {} +L 4 30 60 110 20 {} +L 4 110 20 140 20 {} +L 4 20 20 30 20 {} +L 4 0 20 20 20 {} +L 4 0 10 0 30 {} +L 4 -40 30 0 30 {} +L 4 -40 10 -40 30 {} +L 4 -40 10 0 10 {} +L 4 10 -40 10 20 {} +L 4 10 -40 50 -40 {} +L 4 50 -50 50 -30 {} +L 4 60 -50 60 -30 {} +L 4 60 -40 120 -40 {} +L 4 120 -40 120 20 {} +L 4 -70 20 -40 20 {} +B 5 -72.5 17.5 -67.5 22.5 {name=in +dir=inout} +B 5 137.5 17.5 142.5 22.5 {name=out +dir=inout}
diff --git a/xschem/src/biasing_network/biasing_network.sch b/xschem/src/biasing_network/biasing_network.sch new file mode 100644 index 0000000..67c00ad --- /dev/null +++ b/xschem/src/biasing_network/biasing_network.sch
@@ -0,0 +1,185 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 160 280 160 360 { lab=iin_15u} +N 160 310 230 310 { lab=iin_15u} +N 160 420 160 430 { lab=vss} +N 160 390 160 420 { lab=vss} +N 200 390 240 390 { lab=iin_15u} +N 230 310 230 390 { lab=iin_15u} +N 240 390 280 390 { lab=iin_15u} +N 280 390 720 390 { lab=iin_15u} +N 310 430 340 430 { lab=vss} +N 490 430 520 430 { lab=vss} +N 660 430 690 430 { lab=vss} +N 330 430 330 460 { lab=vss} +N 510 430 510 460 { lab=vss} +N 670 430 670 460 { lab=vss} +N 280 430 310 430 { lab=vss} +N 340 430 370 430 { lab=vss} +N 460 430 490 430 { lab=vss} +N 520 430 550 430 { lab=vss} +N 630 430 660 430 { lab=vss} +N 690 430 720 430 { lab=vss} +N 720 390 880 390 { lab=iin_15u} +N 830 430 850 430 { lab=vss} +N 840 430 840 460 { lab=vss} +N 850 430 880 430 { lab=vss} +N 800 430 830 430 { lab=vss} +N 250 430 250 480 { lab=ibias1_15u} +N 400 430 400 480 { lab=ibias2_15u} +N 430 430 430 480 { lab=ibias3_15u} +N 580 430 580 480 { lab=ibias4_15u} +N 600 430 600 480 { lab=ibias5_15u} +N 750 430 750 480 { lab=ibias6_15u} +N 770 430 770 480 { lab=ibias7_15u} +N 910 430 910 480 { lab=ibias8_15u} +N 160 430 160 470 { lab=vss} +N 100 510 160 510 { lab=vss} +N 100 280 160 280 { lab=iin_15u} +N 80 280 100 280 { lab=iin_15u} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 180 390 0 1 {name=M5 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 280 410 3 1 {name=M6 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 370 410 1 0 {name=M7 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 460 410 3 1 {name=M8 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 550 410 1 0 {name=M9 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 630 410 3 1 {name=M10 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 720 410 1 0 {name=M11 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 800 410 1 0 {name=M12 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 880 410 1 0 {name=M13 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} 160 460 0 1 {name=l1 sig_type=std_logic lab=vss} +C {lab_wire.sym} 330 460 0 1 {name=l2 sig_type=std_logic lab=vss} +C {lab_wire.sym} 510 460 0 1 {name=l3 sig_type=std_logic lab=vss} +C {lab_wire.sym} 670 460 0 1 {name=l4 sig_type=std_logic lab=vss} +C {lab_wire.sym} 840 460 0 1 {name=l5 sig_type=std_logic lab=vss} +C {iopin.sym} 80 280 0 0 {name=p1 lab=iin_15u} +C {iopin.sym} 90 510 0 0 {name=p2 lab=vss} +C {lab_wire.sym} 150 510 0 1 {name=l6 sig_type=std_logic lab=vss} +C {opin.sym} 250 480 1 0 {name=p3 lab=ibias1_15u} +C {opin.sym} 400 480 1 0 {name=p4 lab=ibias2_15u} +C {opin.sym} 430 480 1 0 {name=p5 lab=ibias3_15u} +C {opin.sym} 580 480 1 0 {name=p6 lab=ibias4_15u} +C {opin.sym} 600 480 1 0 {name=p7 lab=ibias5_15u} +C {opin.sym} 750 480 1 0 {name=p8 lab=ibias6_15u} +C {opin.sym} 770 480 1 0 {name=p9 lab=ibias7_15u} +C {opin.sym} 910 480 1 0 {name=p10 lab=ibias8_15u}
diff --git a/xschem/src/biasing_network/biasing_network.sym b/xschem/src/biasing_network/biasing_network.sym new file mode 100644 index 0000000..06b90d4 --- /dev/null +++ b/xschem/src/biasing_network/biasing_network.sym
@@ -0,0 +1,43 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -20 -100 -20 100 {} +L 4 130 -100 130 100 {} +L 4 130 -70 150 -70 {} +L 4 130 30 150 30 {} +L 4 130 -30 150 -30 {} +L 4 130 -10 150 -10 {} +L 4 130 10 150 10 {} +L 4 130 -50 150 -50 {} +L 4 130 50 150 50 {} +L 4 130 70 150 70 {} +L 4 -20 -100 130 -100 {} +L 4 -20 100 130 100 {} +B 5 47.5 -102.5 52.5 -97.5 {name=iin_15u dir=inout } +B 5 147.5 -72.5 152.5 -67.5 {name=ibias1_15u dir=out } +B 5 147.5 -52.5 152.5 -47.5 {name=ibias2_15u dir=out } +B 5 147.5 -32.5 152.5 -27.5 {name=ibias3_15u dir=out } +B 5 147.5 -12.5 152.5 -7.5 {name=ibias4_15u dir=out } +B 5 147.5 7.5 152.5 12.5 {name=ibias5_15u dir=out } +B 5 147.5 27.5 152.5 32.5 {name=ibias6_15u dir=out } +B 5 147.5 47.5 152.5 52.5 {name=ibias7_15u dir=out } +B 5 147.5 67.5 152.5 72.5 {name=ibias8_15u dir=out } +B 5 47.5 97.5 52.5 102.5 {name=vss dir=inout } +T {@symname} -15.5 -26 0 0 0.3 0.3 {} +T {@name} 135 -112 0 0 0.2 0.2 {} +T {iin_15u} 55 -94 0 1 0.2 0.2 {} +T {ibias1_15u} 125 -74 0 1 0.2 0.2 {} +T {ibias6_15u} 125 26 0 1 0.2 0.2 {} +T {ibias3_15u} 125 -34 0 1 0.2 0.2 {} +T {ibias4_15u} 125 -14 0 1 0.2 0.2 {} +T {ibias5_15u} 125 6 0 1 0.2 0.2 {} +T {ibias2_15u} 125 -54 0 1 0.2 0.2 {} +T {ibias7_15u} 125 46 0 1 0.2 0.2 {} +T {ibias8_15u} 125 66 0 1 0.2 0.2 {} +T {vss} 55 86 0 1 0.2 0.2 {}
diff --git a/xschem/src/biasing_network/biasing_network_tb.sch b/xschem/src/biasing_network/biasing_network_tb.sch new file mode 100644 index 0000000..bf82f82 --- /dev/null +++ b/xschem/src/biasing_network/biasing_network_tb.sch
@@ -0,0 +1,53 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -220 -380 -220 -350 { lab=vdd} +N -220 -290 -220 -260 { lab=GND} +N -0 -270 -0 -230 { lab=#net1} +N 0 -30 -0 0 { lab=GND} +N -0 -360 0 -330 { lab=vdd} +N -50 -360 0 -360 { lab=vdd} +C {netlist_not_shown.sym} -20 -510 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice +.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_post.spice +.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_post.spice +.include /home/eda/magic/class_d_audio_amplifier/comparator/comparator_post.spice +.include /home/eda/magic/class_d_audio_amplifier/dead_time/dead_time_post.spice +.include /home/eda/magic/class_d_audio_amplifier/output_driver/output_driver_post.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {vsource.sym} -220 -320 0 0 {name=V4 value=1.8} +C {lab_wire.sym} -220 -370 0 0 {name=l16 sig_type=std_logic lab=vdd} +C {gnd.sym} -220 -260 0 0 {name=l63 lab=GND} +C {src/biasing_network/biasing_network.sym} -50 -130 0 0 {name=x1} +C {gnd.sym} 0 0 0 0 {name=l1 lab=GND} +C {res.sym} 0 -300 0 0 {name=R1 +value=83k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} -30 -360 0 0 {name=l2 sig_type=std_logic lab=vdd} +C {code_shown.sym} 170 -520 0 0 {name=s2 only_toplevel=false value=" +.control +save all +op +tran 10n 1u +.endc + + +"}
diff --git a/xschem/src/buffer/buffer.sch b/xschem/src/buffer/buffer.sch new file mode 100644 index 0000000..1c03efa --- /dev/null +++ b/xschem/src/buffer/buffer.sch
@@ -0,0 +1,323 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 770 380 770 390 { lab=vss} +N 770 350 800 350 { lab=vss} +N 800 350 800 380 { lab=vss} +N 770 210 770 230 { lab=vdd} +N 770 380 800 380 { lab=vss} +N 770 260 790 260 { lab=vdd} +N 790 230 790 260 { lab=vdd} +N 770 230 790 230 { lab=vdd} +N 770 290 770 310 { lab=#net1} +N 770 310 770 320 { lab=#net1} +N 730 260 730 310 { lab=vip} +N 730 320 730 350 { lab=vip} +N 730 310 730 320 { lab=vip} +N 770 310 840 310 { lab=#net1} +N 880 380 880 390 { lab=vss} +N 880 350 910 350 { lab=vss} +N 910 350 910 380 { lab=vss} +N 880 210 880 230 { lab=vdd} +N 880 380 910 380 { lab=vss} +N 880 260 900 260 { lab=vdd} +N 900 230 900 260 { lab=vdd} +N 880 230 900 230 { lab=vdd} +N 880 290 880 310 { lab=#net2} +N 880 310 880 320 { lab=#net2} +N 840 260 840 310 { lab=#net1} +N 840 320 840 350 { lab=#net1} +N 840 310 840 320 { lab=#net1} +N 990 380 990 390 { lab=vss} +N 990 350 1020 350 { lab=vss} +N 1020 350 1020 380 { lab=vss} +N 990 210 990 230 { lab=vdd} +N 990 380 1020 380 { lab=vss} +N 990 260 1010 260 { lab=vdd} +N 1010 230 1010 260 { lab=vdd} +N 990 230 1010 230 { lab=vdd} +N 990 290 990 310 { lab=#net3} +N 990 310 990 320 { lab=#net3} +N 950 260 950 310 { lab=#net2} +N 950 320 950 350 { lab=#net2} +N 950 310 950 320 { lab=#net2} +N 1090 380 1090 390 { lab=vss} +N 1090 350 1120 350 { lab=vss} +N 1120 350 1120 380 { lab=vss} +N 1090 210 1090 230 { lab=vdd} +N 1090 380 1120 380 { lab=vss} +N 1090 260 1110 260 { lab=vdd} +N 1110 230 1110 260 { lab=vdd} +N 1090 230 1110 230 { lab=vdd} +N 1090 290 1090 310 { lab=vop} +N 1090 310 1090 320 { lab=vop} +N 1050 260 1050 310 { lab=#net3} +N 1050 320 1050 350 { lab=#net3} +N 1050 310 1050 320 { lab=#net3} +N 880 310 950 310 { lab=#net2} +N 990 310 1050 310 { lab=#net3} +N 770 610 770 620 { lab=gnd} +N 770 580 800 580 { lab=gnd} +N 800 580 800 610 { lab=gnd} +N 770 440 770 460 { lab=vdd} +N 770 610 800 610 { lab=gnd} +N 770 420 770 440 { lab=vdd} +N 770 490 790 490 { lab=vdd} +N 790 460 790 490 { lab=vdd} +N 770 460 790 460 { lab=vdd} +N 770 520 770 540 { lab=#net4} +N 770 540 770 550 { lab=#net4} +N 730 490 730 540 { lab=vin} +N 730 550 730 580 { lab=vin} +N 730 540 730 550 { lab=vin} +N 880 610 880 620 { lab=gnd} +N 880 580 910 580 { lab=gnd} +N 910 580 910 610 { lab=gnd} +N 880 440 880 460 { lab=vdd} +N 880 610 910 610 { lab=gnd} +N 880 420 880 440 { lab=vdd} +N 880 490 900 490 { lab=vdd} +N 900 460 900 490 { lab=vdd} +N 880 460 900 460 { lab=vdd} +N 880 520 880 540 { lab=#net5} +N 880 540 880 550 { lab=#net5} +N 840 490 840 540 { lab=#net4} +N 840 550 840 580 { lab=#net4} +N 840 540 840 550 { lab=#net4} +N 990 610 990 620 { lab=gnd} +N 990 580 1020 580 { lab=gnd} +N 1020 580 1020 610 { lab=gnd} +N 990 440 990 460 { lab=vdd} +N 990 610 1020 610 { lab=gnd} +N 990 420 990 440 { lab=vdd} +N 990 490 1010 490 { lab=vdd} +N 1010 460 1010 490 { lab=vdd} +N 990 460 1010 460 { lab=vdd} +N 990 520 990 540 { lab=von} +N 990 540 990 550 { lab=von} +N 950 490 950 540 { lab=#net5} +N 950 550 950 580 { lab=#net5} +N 950 540 950 550 { lab=#net5} +N 770 530 840 530 { lab=#net4} +N 880 530 950 530 { lab=#net5} +N 640 300 730 300 { lab=vip} +N 630 520 730 520 { lab=vin} +N 990 540 1200 540 { lab=von} +N 1090 310 1200 310 { lab=vop} +N 750 390 1090 390 { lab=vss} +N 770 210 1090 210 { lab=vdd} +N 770 420 990 420 { lab=vdd} +N 770 620 990 620 { lab=gnd} +N 630 390 660 390 { lab=vdd} +N 630 450 660 450 { lab=vss} +C {sky130_fd_pr/nfet_01v8.sym} 750 350 0 0 {name=M3 +L=0.15 +W=5 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 750 260 0 0 {name=M1 +L=0.15 +W=10 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 860 350 0 0 {name=M2 +L=0.15 +W=20 +nf=8 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 860 260 0 0 {name=M4 +L=0.15 +W=40 +nf=8 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 970 350 0 0 {name=M5 +L=0.15 +W=90 +nf=36 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 970 260 0 0 {name=M6 +L=0.15 +W=180 +nf=36 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 1070 350 0 0 {name=M7 +L=0.15 +W=202.5 +nf=81 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 1070 260 0 0 {name=M8 +L=0.15 +W=405 +nf=81 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 750 580 0 0 {name=M9 +L=0.15 +W=5 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 750 490 0 0 {name=M10 +L=0.15 +W=10 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 860 580 0 0 {name=M11 +L=0.15 +W=20 +nf=8 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 860 490 0 0 {name=M12 +L=0.15 +W=40 +nf=8 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 970 580 0 0 {name=M13 +L=0.15 +W=90 +nf=36 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 970 490 0 0 {name=M14 +L=0.15 +W=180 +nf=36 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {iopin.sym} 630 390 0 1 {name=p1 lab=vdd} +C {iopin.sym} 630 450 0 1 {name=p2 lab=vss} +C {ipin.sym} 640 300 0 0 {name=p3 lab=vip} +C {ipin.sym} 630 520 0 0 {name=p4 lab=vin} +C {opin.sym} 1200 310 0 0 {name=p5 lab=vop} +C {opin.sym} 1200 540 0 0 {name=p6 lab=von} +C {lab_wire.sym} 810 420 0 0 {name=l1 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 840 210 0 0 {name=l2 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 840 390 0 0 {name=l3 sig_type=std_logic lab=vss} +C {lab_wire.sym} 850 620 0 0 {name=l4 sig_type=std_logic lab=vss} +C {lab_wire.sym} 660 390 0 0 {name=l5 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 660 450 0 0 {name=l6 sig_type=std_logic lab=vss}
diff --git a/xschem/src/buffer/buffer.sym b/xschem/src/buffer/buffer.sym new file mode 100644 index 0000000..d1ef462 --- /dev/null +++ b/xschem/src/buffer/buffer.sym
@@ -0,0 +1,31 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -40 130 -40 {} +L 4 -130 40 130 40 {} +L 4 -130 -40 -130 40 {} +L 4 130 -40 130 40 {} +L 4 -150 -20 -130 -20 {} +L 4 130 -20 150 -20 {} +L 4 -150 20 -130 20 {} +L 4 130 20 150 20 {} +B 5 -2.5 -42.5 2.5 -37.5 {name=vdd dir=inout } +B 5 -152.5 -22.5 -147.5 -17.5 {name=vip dir=in } +B 5 147.5 -22.5 152.5 -17.5 {name=vop dir=out } +B 5 -152.5 17.5 -147.5 22.5 {name=vin dir=in } +B 5 147.5 17.5 152.5 22.5 {name=von dir=out } +B 5 -2.5 37.5 2.5 42.5 {name=vss dir=inout } +T {@symname} -45 -6 0 0 0.3 0.3 {} +T {@name} 135 -52 0 0 0.2 0.2 {} +T {vdd} 5 -34 0 1 0.2 0.2 {} +T {vip} -125 -24 0 0 0.2 0.2 {} +T {vop} 125 -24 0 1 0.2 0.2 {} +T {vin} -125 16 0 0 0.2 0.2 {} +T {von} 125 16 0 1 0.2 0.2 {} +T {vss} 5 26 0 1 0.2 0.2 {}
diff --git a/xschem/src/common_source/common_source.sch b/xschem/src/common_source/common_source.sch new file mode 100644 index 0000000..9feb21b --- /dev/null +++ b/xschem/src/common_source/common_source.sch
@@ -0,0 +1,88 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -30 70 90 70 { lab=vin} +N -30 130 130 130 { lab=GND} +N 130 100 130 130 { lab=GND} +N 130 -10 130 40 { lab=out} +N 130 -110 130 -70 { lab=#net1} +N 130 -110 240 -110 { lab=#net1} +N 240 -50 240 130 { lab=GND} +N 130 130 240 130 { lab=GND} +N 130 70 160 70 { lab=GND} +N 160 70 160 130 { lab=GND} +C {sky130_fd_pr/nfet_01v8.sym} 110 70 0 0 {name=M1 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {vsource.sym} 240 -80 0 0 {name=V1 value=1.8} +C {vsource.sym} -30 100 0 0 {name=V2 value=0.9} +C {gnd.sym} 40 130 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 130 20 0 0 {name=l2 sig_type=std_logic lab=out} +C {lab_wire.sym} 50 70 0 0 {name=l3 sig_type=std_logic lab=vin} +C {netlist_not_shown.sym} -190 -110 0 0 {name=TT_MODELS +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_03v3_nvt/sky130_fd_pr__nfet_03v3_nvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_nfet_01v8/sky130_fd_pr__esd_nfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_pfet_g5v0d10v5/sky130_fd_pr__esd_pfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d16v0/sky130_fd_pr__pfet_g5v0d16v0__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d10v5/sky130_fd_pr__nfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d16v0/sky130_fd_pr__nfet_g5v0d16v0__tt_discrete.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_nfet_g5v0d10v5/sky130_fd_pr__esd_nfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/nonfet.spice +* Mismatch parameters +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d10v5/sky130_fd_pr__nfet_g5v0d10v5__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_03v3_nvt/sky130_fd_pr__nfet_03v3_nvt__mismatch.corner.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice +* All models +.include \\\\$::SKYWATER_MODELS\\\\/models/all.spice +* Corner +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/rf.spice +" +} +C {code_shown.sym} -310 50 0 0 {name=s1 only_toplevel=false value=" +.control +dc V2 0 1.8 0.01 +save all +write common_source.raw +.endc +"} +C {res.sym} 130 -40 0 0 {name=R1 +value=1k +footprint=1206 +device=resistor +m=1}
diff --git a/xschem/src/comparator/comparator.sch b/xschem/src/comparator/comparator.sch new file mode 100644 index 0000000..5d00204 --- /dev/null +++ b/xschem/src/comparator/comparator.sch
@@ -0,0 +1,195 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +T {gm/id=11} -210 -160 0 0 0.2 0.2 {} +T {gm/id=11} -30 -160 0 0 0.2 0.2 {} +T {gm/id=11} 310 -160 0 0 0.2 0.2 {} +T {gm/id=15} -40 -60 0 0 0.2 0.2 {} +T {gm/id=15} 60 -60 0 0 0.2 0.2 {} +T {gm/id=17} -20 80 0 0 0.2 0.2 {} +T {gm/id=17} 40 80 0 0 0.2 0.2 {} +T {gm/id=17} 310 30 0 0 0.2 0.2 {} +N -370 -90 -300 -90 { lab=vn} +N -380 -50 -300 -50 { lab=vbias} +N -380 -90 -370 -90 { lab=vn} +N -380 -130 -360 -130 { lab=vp} +N -360 -130 -300 -130 { lab=vp} +N -370 -160 -300 -160 { lab=vdd} +N -360 -20 -300 -20 { lab=vss} +N -370 -20 -360 -20 { lab=vss} +N -220 -160 -220 -80 { lab=vbias} +N -220 100 120 100 { lab=vss} +N -50 70 -50 100 { lab=vss} +N 120 70 120 100 { lab=vss} +N -50 -50 -50 40 { lab=vf} +N 120 -50 120 40 { lab=v1} +N -50 -110 120 -110 { lab=vc} +N 40 -160 40 -110 { lab=vc} +N -10 70 80 70 { lab=vf} +N -50 20 30 20 { lab=vf} +N 30 20 30 70 { lab=vf} +N -220 -130 -150 -130 { lab=vbias} +N -150 -190 -150 -130 { lab=vbias} +N -180 -190 0 -190 { lab=vbias} +N 370 -160 370 -40 { lab=vout} +N 370 -190 380 -190 { lab=vdd} +N 380 -220 380 -190 { lab=vdd} +N 370 20 370 100 { lab=vss} +N 120 100 270 100 { lab=vss} +N 370 -10 400 -10 { lab=vss} +N 400 -10 400 20 { lab=vss} +N 370 20 400 20 { lab=vss} +N -220 -220 280 -220 { lab=vdd} +N 40 -220 40 -190 { lab=vdd} +N -220 -220 -220 -190 { lab=vdd} +N 300 -190 330 -190 { lab=vbias} +N 330 -10 330 20 { lab=v1} +N 120 20 230 20 { lab=v1} +N -110 -80 -90 -80 { lab=vn} +N 160 -80 180 -80 { lab=vp} +N 330 100 370 100 { lab=vss} +N 300 20 330 20 { lab=v1} +N 280 -220 350 -220 { lab=vdd} +N 270 100 330 100 { lab=vss} +N 350 -220 370 -220 { lab=vdd} +N 370 -220 380 -220 { lab=vdd} +N 230 20 300 20 { lab=v1} +N 370 -90 410 -90 { lab=vout} +N -50 -110 -50 -80 { lab=vc} +N 120 -110 120 -80 { lab=vc} +C {ipin.sym} -370 -130 0 0 {name=p3 lab=vp} +C {ipin.sym} -370 -90 0 0 {name=p4 lab=vn} +C {ipin.sym} -370 -50 0 0 {name=p6 lab=vbias} +C {lab_wire.sym} -310 -50 0 0 {name=l5 sig_type=std_logic lab=vbias} +C {iopin.sym} -370 -20 0 1 {name=p2 lab=vss} +C {lab_wire.sym} -320 -130 0 0 {name=l3 sig_type=std_logic lab=vp} +C {lab_wire.sym} -330 -90 0 1 {name=l7 sig_type=std_logic lab=vn} +C {lab_wire.sym} -310 -160 0 1 {name=l10 sig_type=std_logic lab=vdd} +C {iopin.sym} -370 -160 0 1 {name=p7 lab=vdd} +C {lab_wire.sym} -320 -20 0 0 {name=l11 sig_type=std_logic lab=vss} +C {opin.sym} 410 -90 0 0 {name=p1 lab=vout} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 140 -80 0 1 {name=M1 +L=1 +W=4 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} -70 -80 0 0 {name=M2 +L=1 +W=4 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 20 -190 0 0 {name=M3 +L=1 +W=2 +nf=2 +mult=24 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 100 70 0 0 {name=M4 +L=1 +W=1 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -30 70 0 1 {name=M5 +L=1 +W=1 +nf=1 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} -200 -190 0 1 {name=M6 +L=1 +W=2 +nf=2 +mult=24 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 350 -190 0 0 {name=M7 +L=1 +W=2 +nf=2 +mult=48 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 350 -10 0 0 {name=M8 +L=1 +W=1 +nf=1 +mult=64 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} -100 -190 0 0 {name=l1 sig_type=std_logic lab=vbias} +C {lab_wire.sym} -110 -220 0 0 {name=l8 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 290 20 0 0 {name=l13 sig_type=std_logic lab=v1} +C {lab_wire.sym} 80 -110 0 0 {name=l14 sig_type=std_logic lab=vc} +C {lab_wire.sym} 370 -70 0 0 {name=l15 sig_type=std_logic lab=vout} +C {lab_wire.sym} 10 20 0 0 {name=l16 sig_type=std_logic lab=vf} +C {lab_wire.sym} 180 -80 0 0 {name=l12 sig_type=std_logic lab=vp} +C {lab_wire.sym} 320 -190 0 0 {name=l4 sig_type=std_logic lab=vbias} +C {lab_wire.sym} -100 -80 0 0 {name=l17 sig_type=std_logic lab=vn} +C {lab_wire.sym} -190 100 0 0 {name=l9 sig_type=std_logic lab=vss}
diff --git a/xschem/src/comparator/comparator.sym b/xschem/src/comparator/comparator.sym new file mode 100644 index 0000000..72b618a --- /dev/null +++ b/xschem/src/comparator/comparator.sym
@@ -0,0 +1,24 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -90 -80 -90 0 {} +L 4 -90 0 20 -40 {} +L 4 -90 -80 20 -40 {} +B 5 -32.5 -62.5 -27.5 -57.5 {name=vdd dir=inout } +B 5 -92.5 -62.5 -87.5 -57.5 {name=vp dir=in } +B 5 -92.5 -42.5 -87.5 -37.5 {name=vn dir=in } +B 5 -92.5 -22.5 -87.5 -17.5 {name=vbias dir=in } +B 5 -32.5 -22.5 -27.5 -17.5 {name=vss dir=inout } +B 5 17.5 -42.5 22.5 -37.5 {name=vout dir=out } +T {@symname} -61.5 -46 0 0 0.2 0.2 {} +T {@name} -5 -72 0 0 0.2 0.2 {} +T {vdd} -35 -54 0 1 0.2 0.2 {} +T {vp} -85 -64 0 0 0.2 0.2 {} +T {vn} -85 -44 0 0 0.2 0.2 {} +T {vbias} -85 -24 0 0 0.2 0.2 {}
diff --git a/xschem/src/comparator/comparator_post.sym b/xschem/src/comparator/comparator_post.sym new file mode 100644 index 0000000..8f1a3bb --- /dev/null +++ b/xschem/src/comparator/comparator_post.sym
@@ -0,0 +1,23 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1"} +V {} +S {} +E {} +L 4 -10 -20 -10 60 {} +L 4 -10 60 100 20 {} +L 4 -10 -20 100 20 {} +B 5 47.5 -2.5 52.5 2.5 {name=vdd dir=inout } +B 5 -12.5 -2.5 -7.5 2.5 {name=vp dir=in } +B 5 -12.5 17.5 -7.5 22.5 {name=vn dir=in } +B 5 -12.5 37.5 -7.5 42.5 {name=vbias dir=in } +B 5 47.5 37.5 52.5 42.5 {name=vss dir=inout } +B 5 97.5 17.5 102.5 22.5 {name=vout dir=out } +T {@symname} 18.5 14 0 0 0.2 0.2 {} +T {@name} 75 -12 0 0 0.2 0.2 {} +T {vdd} 45 6 0 1 0.2 0.2 {} +T {vp} -5 -4 0 0 0.2 0.2 {} +T {vn} -5 16 0 0 0.2 0.2 {} +T {vbias} -5 36 0 0 0.2 0.2 {}
diff --git a/xschem/src/comparator/comparator_revised_post.sym b/xschem/src/comparator/comparator_revised_post.sym new file mode 100644 index 0000000..dda860c --- /dev/null +++ b/xschem/src/comparator/comparator_revised_post.sym
@@ -0,0 +1,23 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1"} +V {} +S {} +E {} +L 4 -30 -40 -30 40 {} +L 4 -30 40 80 0 {} +L 4 -30 -40 80 0 {} +B 5 27.5 -22.5 32.5 -17.5 {name=vdd dir=inout } +B 5 -32.5 -22.5 -27.5 -17.5 {name=vp dir=in } +B 5 -32.5 -2.5 -27.5 2.5 {name=vn dir=in } +B 5 -32.5 17.5 -27.5 22.5 {name=vbias dir=in } +B 5 27.5 17.5 32.5 22.5 {name=vss dir=inout } +B 5 77.5 -2.5 82.5 2.5 {name=vout dir=out } +T {@symname} -1.5 -6 0 0 0.2 0.2 {} +T {@name} 55 -32 0 0 0.2 0.2 {} +T {vdd} 25 -14 0 1 0.2 0.2 {} +T {vp} -25 -24 0 0 0.2 0.2 {} +T {vn} -25 -4 0 0 0.2 0.2 {} +T {vbias} -25 16 0 0 0.2 0.2 {}
diff --git a/xschem/src/comparator/comparator_tb.sch b/xschem/src/comparator/comparator_tb.sch new file mode 100644 index 0000000..43ed0b8 --- /dev/null +++ b/xschem/src/comparator/comparator_tb.sch
@@ -0,0 +1,154 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -20 -140 -20 -120 { lab=vdd} +N -20 -140 0 -140 { lab=vdd} +N -30 20 -30 40 { lab=vref} +N 350 -110 390 -110 { lab=#net1} +N 350 -90 390 -90 { lab=vref} +N 350 -70 390 -70 { lab=vbias3} +N 450 -140 450 -110 { lab=vdd} +N 450 -70 450 -20 { lab=GND} +N 500 -90 540 -90 { lab=vout} +N 90 70 90 150 { lab=v1} +N 90 100 160 100 { lab=v1} +N 90 -10 90 10 { lab=vdd} +N 90 210 90 220 { lab=GND} +N 90 180 90 210 { lab=GND} +N 130 180 170 180 { lab=v1} +N 160 100 160 180 { lab=v1} +N 170 180 210 180 { lab=v1} +N 240 220 270 220 { lab=GND} +N 260 220 260 250 { lab=GND} +N 440 220 440 250 { lab=GND} +N 210 220 240 220 { lab=GND} +N 270 220 300 220 { lab=GND} +N 390 220 420 220 { lab=GND} +N 180 220 180 270 { lab=vbias1} +N 330 220 330 270 { lab=vbias2} +N 360 220 360 270 { lab=vbias3} +N 420 220 440 220 { lab=GND} +N 210 180 390 180 { lab=v1} +N 200 -110 200 -90 { lab=#net1} +N 200 -110 350 -110 { lab=#net1} +C {vsource.sym} -20 -90 0 0 {name=V3 value=1.8} +C {gnd.sym} -20 -60 0 0 {name=l6 lab=GND} +C {lab_wire.sym} 0 -140 0 0 {name=l7 sig_type=std_logic lab=vdd} +C {code_shown.sym} 840 -290 0 0 {name=s1 only_toplevel=false value=" +.nodeset V(vt)=0.9 +.control +save @m.xm3.msky130_fd_pr__pfet_01v8_lvt[id] +save @m.xm7.msky130_fd_pr__pfet_01v8_lvt[id] +save @m.xm8.msky130_fd_pr__nfet_01v8_lvt[id] +save all +op +*tran 4n 500u +*5n +*plot @m.xm7.msky130_fd_pr__pfet_01v8_lvt[id] +*plot @m.xm8.msky130_fd_pr__nfet_01v8_lvt[id] +*dc V2 0 1.8 0.01 +ac dec 10000 100 100G +meas ac GBW when vdb(vout)=0 +meas ac DC_Gain find vdb(vout) at=1000 +meas ac PM find vp(vout) when vdb(vout)=0 +print PM*180/PI +plot vdb(vout) (vp(vout))*180/PI + +.endc +"} +C {netlist_not_shown.sym} -150 -300 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/comparator/comparator_post.spice + +.include /home/eda/magic/class_d_audio_amplifier/comparator/comparator_revised_post.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {vsource.sym} -30 70 0 0 {name=V1 value=0.9} +C {gnd.sym} -30 100 0 0 {name=l10 lab=GND} +C {lab_wire.sym} -30 30 0 0 {name=l11 sig_type=std_logic lab=vref} +C {lab_wire.sym} 360 -90 0 0 {name=l1 sig_type=std_logic lab=vref} +C {lab_wire.sym} 450 -130 0 0 {name=l2 sig_type=std_logic lab=vdd} +C {gnd.sym} 450 -20 0 0 {name=l3 lab=GND} +C {isource.sym} 90 40 0 0 {name=I0 value=15u} +C {lab_wire.sym} 90 -10 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} 90 220 0 0 {name=l9 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 110 180 0 1 {name=M5 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 210 200 3 1 {name=M6 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} 140 100 0 1 {name=l62 sig_type=std_logic lab=v1} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 300 200 1 0 {name=M7 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 390 200 3 1 {name=M8 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} 260 250 0 0 {name=l54 lab=GND} +C {gnd.sym} 440 250 0 0 {name=l59 lab=GND} +C {lab_wire.sym} 180 260 0 0 {name=l39 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 330 270 0 0 {name=l66 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 360 270 0 1 {name=l67 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 360 -70 0 0 {name=l14 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 530 -90 0 1 {name=l15 sig_type=std_logic lab=vout} +C {src/comparator/comparator_revised_post.sym} 420 -90 0 0 {name=x1} +C {vsource.sym} 200 -60 0 0 {name=V2 value="dc 0.9 ac 1"} +C {gnd.sym} 200 -30 0 0 {name=l4 lab=GND}
diff --git a/xschem/src/current_source/current_source_tb.sch b/xschem/src/current_source/current_source_tb.sch new file mode 100644 index 0000000..d91ca61 --- /dev/null +++ b/xschem/src/current_source/current_source_tb.sch
@@ -0,0 +1,103 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 20 200 20 280 { lab=v1} +N 20 230 90 230 { lab=v1} +N 20 120 20 140 { lab=vdd} +N 20 340 20 350 { lab=GND} +N 20 310 20 340 { lab=GND} +N 60 310 100 310 { lab=v1} +N 90 230 90 310 { lab=v1} +N 100 310 140 310 { lab=v1} +N 180 340 180 350 { lab=GND} +N 180 310 180 340 { lab=GND} +N 180 100 180 150 { lab=vbias} +N 180 120 230 120 { lab=vbias} +N 230 70 230 120 { lab=vbias} +N 220 70 230 70 { lab=vbias} +N 230 70 280 70 { lab=vbias} +N 180 40 180 70 { lab=vdd} +N 180 20 180 40 { lab=vdd} +N -110 230 -110 260 { lab=GND} +N -110 140 -110 170 { lab=vdd} +N 180 250 180 280 { lab=#net1} +N 180 150 180 190 { lab=vbias} +C {netlist_not_shown.sym} -60 -90 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {code_shown.sym} 350 80 0 0 {name=s1 only_toplevel=false value=" +.option savecurrents +.control +save all +tran 1n 1u +.endc + + +"} +C {isource.sym} 20 170 0 0 {name=I0 value=150u} +C {lab_wire.sym} 20 120 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} 20 350 0 0 {name=l10 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 40 310 0 1 {name=M5 +L=2 +W=4 +nf=2 +mult=80 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 160 310 0 0 {name=M6 +L=2 +W=4 +nf=2 +mult=80 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} 180 350 0 0 {name=l54 lab=GND} +C {lab_wire.sym} 180 160 0 0 {name=l59 sig_type=std_logic lab=vbias} +C {sky130_fd_pr/pfet_01v8_lvt.sym} 200 70 0 1 {name=M1 +L=1 +W=4 +nf=2 +mult=40 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} 180 20 0 0 {name=l1 sig_type=std_logic lab=vdd} +C {vsource.sym} -110 200 0 0 {name=V1 value=1.8} +C {gnd.sym} -110 260 0 0 {name=l2 lab=GND} +C {lab_wire.sym} -110 160 0 0 {name=l3 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 70 230 0 1 {name=l4 sig_type=std_logic lab=v1} +C {vsource.sym} 180 220 0 0 {name=V2 value=0}
diff --git a/xschem/src/dead_time/dead_time.sch b/xschem/src/dead_time/dead_time.sch new file mode 100644 index 0000000..b161d97 --- /dev/null +++ b/xschem/src/dead_time/dead_time.sch
@@ -0,0 +1,372 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 150 -50 200 -50 { lab=#net1} +N 150 70 200 70 { lab=#net2} +N 50 60 80 60 { lab=#net3} +N 50 30 50 60 { lab=#net3} +N 50 -40 50 -10 { lab=#net4} +N 50 -40 80 -40 { lab=#net4} +N -10 80 80 80 { lab=vinn} +N -150 -60 80 -60 { lab=vin} +N -110 80 -90 80 { lab=vin} +N -110 -60 -110 80 { lab=vin} +N 200 -50 230 -50 { lab=#net1} +N 200 70 220 70 { lab=#net2} +N 230 -50 270 -50 { lab=#net1} +N 220 70 270 70 { lab=#net2} +N -60 40 -60 60 { lab=vdd} +N -60 100 -60 120 { lab=vss} +N 100 100 100 120 { lab=vss} +N 100 30 100 40 { lab=vdd} +N 100 -90 100 -80 { lab=vdd} +N 270 -50 320 -50 { lab=#net1} +N 270 70 290 70 { lab=#net2} +N 290 70 320 70 { lab=#net2} +N 790 -90 810 -90 { lab=vp} +N 790 130 810 130 { lab=vn} +N -220 -50 -190 -50 { lab=vin} +N -220 -90 -180 -90 { lab=vdd} +N 100 -20 100 -10 { lab=vss} +N -220 0 -190 0 { lab=vss} +N 810 -90 830 -90 { lab=vp} +N 810 130 830 130 { lab=vn} +N 270 -140 270 -110 { lab=vss} +N 270 130 270 160 { lab=vss} +N 430 -20 430 -10 { lab=vss} +N 430 -50 460 -50 { lab=vss} +N 460 -50 460 -20 { lab=vss} +N 430 -190 430 -170 { lab=vdd} +N 430 -20 460 -20 { lab=vss} +N 430 -140 450 -140 { lab=vdd} +N 450 -170 450 -140 { lab=vdd} +N 430 -170 450 -170 { lab=vdd} +N 430 -110 430 -90 { lab=#net5} +N 430 -90 430 -80 { lab=#net5} +N 390 -140 390 -90 { lab=#net1} +N 390 -80 390 -50 { lab=#net1} +N 390 -90 390 -80 { lab=#net1} +N 430 -90 500 -90 { lab=#net5} +N 540 -20 540 -10 { lab=vss} +N 540 -50 570 -50 { lab=vss} +N 570 -50 570 -20 { lab=vss} +N 540 -190 540 -170 { lab=vdd} +N 540 -20 570 -20 { lab=vss} +N 540 -140 560 -140 { lab=vdd} +N 560 -170 560 -140 { lab=vdd} +N 540 -170 560 -170 { lab=vdd} +N 540 -110 540 -90 { lab=#net3} +N 540 -90 540 -80 { lab=#net3} +N 500 -140 500 -90 { lab=#net5} +N 500 -80 500 -50 { lab=#net5} +N 500 -90 500 -80 { lab=#net5} +N 650 -20 650 -10 { lab=vss} +N 650 -50 680 -50 { lab=vss} +N 680 -50 680 -20 { lab=vss} +N 650 -190 650 -170 { lab=vdd} +N 650 -20 680 -20 { lab=vss} +N 650 -140 670 -140 { lab=vdd} +N 670 -170 670 -140 { lab=vdd} +N 650 -170 670 -170 { lab=vdd} +N 650 -110 650 -90 { lab=#net6} +N 650 -90 650 -80 { lab=#net6} +N 610 -140 610 -90 { lab=#net3} +N 610 -80 610 -50 { lab=#net3} +N 610 -90 610 -80 { lab=#net3} +N 750 -20 750 -10 { lab=vss} +N 750 -50 780 -50 { lab=vss} +N 780 -50 780 -20 { lab=vss} +N 750 -190 750 -170 { lab=vdd} +N 750 -20 780 -20 { lab=vss} +N 750 -140 770 -140 { lab=vdd} +N 770 -170 770 -140 { lab=vdd} +N 750 -170 770 -170 { lab=vdd} +N 750 -110 750 -90 { lab=vp} +N 750 -90 750 -80 { lab=vp} +N 710 -140 710 -90 { lab=#net6} +N 710 -80 710 -50 { lab=#net6} +N 710 -90 710 -80 { lab=#net6} +N 540 -90 610 -90 { lab=#net3} +N 650 -90 710 -90 { lab=#net6} +N 430 210 430 220 { lab=vss} +N 430 180 460 180 { lab=vss} +N 460 180 460 210 { lab=vss} +N 430 40 430 60 { lab=vdd} +N 430 210 460 210 { lab=vss} +N 430 20 430 40 { lab=vdd} +N 430 90 450 90 { lab=vdd} +N 450 60 450 90 { lab=vdd} +N 430 60 450 60 { lab=vdd} +N 430 120 430 140 { lab=#net7} +N 430 140 430 150 { lab=#net7} +N 390 90 390 140 { lab=#net2} +N 390 150 390 180 { lab=#net2} +N 390 140 390 150 { lab=#net2} +N 540 210 540 220 { lab=vss} +N 540 180 570 180 { lab=vss} +N 570 180 570 210 { lab=vss} +N 540 40 540 60 { lab=vdd} +N 540 210 570 210 { lab=vss} +N 540 20 540 40 { lab=vdd} +N 540 90 560 90 { lab=vdd} +N 560 60 560 90 { lab=vdd} +N 540 60 560 60 { lab=vdd} +N 540 120 540 140 { lab=#net4} +N 540 140 540 150 { lab=#net4} +N 500 90 500 140 { lab=#net7} +N 500 150 500 180 { lab=#net7} +N 500 140 500 150 { lab=#net7} +N 650 210 650 220 { lab=vss} +N 650 180 680 180 { lab=vss} +N 680 180 680 210 { lab=vss} +N 650 40 650 60 { lab=vdd} +N 650 210 680 210 { lab=vss} +N 650 20 650 40 { lab=vdd} +N 650 90 670 90 { lab=vdd} +N 670 60 670 90 { lab=vdd} +N 650 60 670 60 { lab=vdd} +N 650 120 650 140 { lab=vn} +N 650 140 650 150 { lab=vn} +N 610 90 610 140 { lab=#net4} +N 610 150 610 180 { lab=#net4} +N 610 140 610 150 { lab=#net4} +N 430 130 500 130 { lab=#net7} +N 540 130 610 130 { lab=#net4} +N 410 -10 750 -10 { lab=vss} +N 430 -190 750 -190 { lab=vdd} +N 430 20 650 20 { lab=vdd} +N 430 220 650 220 { lab=vss} +N 320 -50 390 -50 { lab=#net1} +N 320 70 370 70 { lab=#net2} +N 370 70 370 110 { lab=#net2} +N 370 110 390 110 { lab=#net2} +N 750 -90 790 -90 { lab=vp} +N 650 130 790 130 { lab=vn} +N 50 -10 580 130 { lab=#net4} +N 50 30 580 -90 { lab=#net3} +C {src/inverter/inverter.sym} -40 80 0 0 {name=x1} +C {src/nand/nand.sym} 140 -50 0 0 {name=x2} +C {src/nand/nand.sym} 140 70 0 0 {name=x3} +C {lab_wire.sym} -130 -60 0 0 {name=l7 sig_type=std_logic lab=vin} +C {lab_wire.sym} -60 50 0 0 {name=l10 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 100 30 0 0 {name=l11 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 100 -90 0 0 {name=l13 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 30 80 0 0 {name=l16 sig_type=std_logic lab=vinn} +C {sky130_fd_pr/cap_mim_m3_1.sym} 270 -80 2 0 {name=C1 model=cap_mim_m3_1 W=17.75 L=17.75 MF=16 spiceprefix=X} +C {ipin.sym} -220 -50 0 0 {name=p1 lab=vin} +C {iopin.sym} -220 -90 0 1 {name=p2 lab=vdd} +C {opin.sym} 830 -90 0 0 {name=p3 lab=vp} +C {iopin.sym} -220 0 0 1 {name=p4 lab=vss} +C {lab_wire.sym} -190 -50 0 0 {name=l1 sig_type=std_logic lab=vin} +C {lab_wire.sym} -190 -90 0 0 {name=l2 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -190 0 0 0 {name=l3 sig_type=std_logic lab=vss} +C {lab_wire.sym} 100 120 0 0 {name=l5 sig_type=std_logic lab=vss} +C {lab_wire.sym} 100 -10 0 1 {name=l6 sig_type=std_logic lab=vss} +C {opin.sym} 830 130 0 0 {name=p5 lab=vn} +C {lab_wire.sym} 270 150 0 1 {name=l12 sig_type=std_logic lab=vss} +C {lab_wire.sym} 270 -130 0 1 {name=l19 sig_type=std_logic lab=vss} +C {sky130_fd_pr/nfet_01v8.sym} 410 -50 0 0 {name=M3 +L=0.15 +W=5 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 410 -140 0 0 {name=M1 +L=0.15 +W=10 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 520 -50 0 0 {name=M2 +L=0.15 +W=20 +nf=8 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 520 -140 0 0 {name=M4 +L=0.15 +W=40 +nf=8 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 630 -50 0 0 {name=M5 +L=0.15 +W=90 +nf=36 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 630 -140 0 0 {name=M6 +L=0.15 +W=180 +nf=36 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 730 -50 0 0 {name=M7 +L=0.15 +W=200 +nf=81 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 730 -140 0 0 {name=M8 +L=0.15 +W=400 +nf=81 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 410 180 0 0 {name=M9 +L=0.15 +W=5 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 410 90 0 0 {name=M10 +L=0.15 +W=10 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 520 180 0 0 {name=M11 +L=0.15 +W=20 +nf=8 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 520 90 0 0 {name=M12 +L=0.15 +W=40 +nf=8 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 630 180 0 0 {name=M13 +L=0.15 +W=90 +nf=36 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 630 90 0 0 {name=M14 +L=0.15 +W=180 +nf=36 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {lab_wire.sym} 470 20 0 0 {name=l8 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 500 -190 0 0 {name=l9 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 500 -10 0 0 {name=l17 sig_type=std_logic lab=vss} +C {lab_wire.sym} 510 220 0 0 {name=l18 sig_type=std_logic lab=vss} +C {lab_wire.sym} -60 120 0 0 {name=l4 sig_type=std_logic lab=vss} +C {sky130_fd_pr/cap_mim_m3_1.sym} 270 100 0 0 {name=C2 model=cap_mim_m3_1 W=17.75 L=17.75 MF=16 spiceprefix=X}
diff --git a/xschem/src/dead_time/dead_time.sym b/xschem/src/dead_time/dead_time.sym new file mode 100644 index 0000000..b44dd73 --- /dev/null +++ b/xschem/src/dead_time/dead_time.sym
@@ -0,0 +1,28 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -80 -40 -80 40 {} +L 4 130 -40 130 40 {} +L 4 -100 0 -80 0 {} +L 4 130 -10 150 -10 {} +L 4 130 10 150 10 {} +L 4 -80 -40 130 -40 {} +L 4 -80 40 130 40 {} +B 5 27.5 -42.5 32.5 -37.5 {name=vdd dir=inout } +B 5 -102.5 -2.5 -97.5 2.5 {name=vin dir=in } +B 5 147.5 -12.5 152.5 -7.5 {name=vp dir=out } +B 5 147.5 7.5 152.5 12.5 {name=vn dir=out } +B 5 27.5 37.5 32.5 42.5 {name=vss dir=inout } +T {@symname} -28.5 -6 0 0 0.3 0.3 {} +T {@name} 85 -62 0 0 0.2 0.2 {} +T {vdd} 35 -34 0 1 0.2 0.2 {} +T {vin} -75 -4 0 0 0.2 0.2 {} +T {vp} 125 -14 0 1 0.2 0.2 {} +T {vn} 125 6 0 1 0.2 0.2 {} +T {vss} 35 26 0 1 0.2 0.2 {}
diff --git a/xschem/src/dead_time/dead_time_post.sym b/xschem/src/dead_time/dead_time_post.sym new file mode 100644 index 0000000..6e0246d --- /dev/null +++ b/xschem/src/dead_time/dead_time_post.sym
@@ -0,0 +1,28 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -40 -20 -40 60 {} +L 4 170 -20 170 60 {} +L 4 -60 20 -40 20 {} +L 4 170 10 190 10 {} +L 4 170 30 190 30 {} +L 4 -40 -20 170 -20 {} +L 4 -40 60 170 60 {} +B 5 67.5 -22.5 72.5 -17.5 {name=vdd dir=inout } +B 5 -62.5 17.5 -57.5 22.5 {name=vin dir=in } +B 5 187.5 7.5 192.5 12.5 {name=vp dir=out } +B 5 187.5 27.5 192.5 32.5 {name=vn dir=out } +B 5 67.5 57.5 72.5 62.5 {name=vss dir=inout } +T {@symname} 11.5 14 0 0 0.3 0.3 {} +T {@name} 125 -42 0 0 0.2 0.2 {} +T {vdd} 75 -14 0 1 0.2 0.2 {} +T {vin} -35 16 0 0 0.2 0.2 {} +T {vp} 165 6 0 1 0.2 0.2 {} +T {vn} 165 26 0 1 0.2 0.2 {} +T {vss} 75 46 0 1 0.2 0.2 {}
diff --git a/xschem/src/dead_time/dead_time_tb.sch b/xschem/src/dead_time/dead_time_tb.sch new file mode 100644 index 0000000..32073a5 --- /dev/null +++ b/xschem/src/dead_time/dead_time_tb.sch
@@ -0,0 +1,63 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -170 150 -170 180 { lab=vin} +N 120 -150 120 -120 { lab=vdd} +N 280 30 280 80 { lab=vdd} +N 10 120 150 120 { lab=vin} +N 280 160 280 210 { lab=GND} +N 400 110 460 110 { lab=vp} +N 400 130 460 130 { lab=vn} +N 530 110 550 110 { lab=#net1} +N 550 100 550 110 { lab=#net1} +N 530 130 550 130 { lab=#net2} +N 550 130 550 140 { lab=#net2} +N 700 60 700 90 { lab=vdd} +N 700 150 700 180 { lab=GND} +N 850 120 890 120 { lab=#net3} +N 520 110 530 110 { lab=#net1} +N 520 130 530 130 { lab=#net2} +C {vsource.sym} -170 210 0 0 {name=V1 value="pulse(0 1.8 0 1n 1n 1u 2u)"} +C {gnd.sym} -170 240 0 0 {name=l5 lab=GND} +C {lab_wire.sym} -170 150 0 0 {name=l6 sig_type=std_logic lab=vin} +C {lab_wire.sym} 70 120 0 0 {name=l7 sig_type=std_logic lab=vin} +C {netlist_not_shown.sym} -160 -30 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/dead_time/dead_time_post.spice + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {code_shown.sym} 1110 -200 0 0 {name=s1 only_toplevel=false value=" +.control +save all +tran 1n 50u +plot vp vn +.endc + +"} +C {vsource.sym} 120 -90 0 0 {name=V3 value=1.8} +C {gnd.sym} 120 -60 0 0 {name=l4 lab=GND} +C {lab_wire.sym} 120 -140 0 0 {name=l23 sig_type=std_logic lab=vdd} +C {src/dead_time/dead_time_post.sym} 210 100 0 0 {name=x4} +C {lab_wire.sym} 280 50 0 0 {name=l29 sig_type=std_logic lab=vdd} +C {gnd.sym} 280 210 0 0 {name=l31 lab=GND} +C {src/output_driver/half_driver.sym} 700 120 0 0 {name=x5} +C {lab_wire.sym} 700 80 0 0 {name=l33 sig_type=std_logic lab=vdd} +C {gnd.sym} 700 180 0 0 {name=l36 lab=GND} +C {lab_wire.sym} 450 110 0 0 {name=l1 sig_type=std_logic lab=vp} +C {lab_wire.sym} 450 130 0 0 {name=l2 sig_type=std_logic lab=vn} +C {vsource.sym} 490 110 1 0 {name=V2 value=0} +C {vsource.sym} 490 130 1 0 {name=V4 value=0}
diff --git a/xschem/src/diode.sch b/xschem/src/diode.sch new file mode 100644 index 0000000..6ea0c24 --- /dev/null +++ b/xschem/src/diode.sch
@@ -0,0 +1,75 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -130 140 -130 170 { lab=vdd} +N -20 220 0 220 { lab=vin} +N -0 220 50 220 { lab=vin} +N -130 230 -130 400 { lab=GND} +N -130 400 -130 460 { lab=GND} +N 50 220 130 220 { lab=vin} +N 230 80 300 80 { lab=vdd} +N 300 80 300 120 { lab=vdd} +N -240 210 -240 240 { lab=#net1} +N -240 390 -240 400 { lab=#net2} +N -240 300 -240 330 { lab=#net3} +N -240 150 -130 150 { lab=vdd} +N -240 460 -130 460 { lab=GND} +C {code_shown.sym} -620 0 0 0 {name=s2 only_toplevel=false value=" + +*.nodeset all=0.9 +*.option VNTOL=1e-6 ABSTOL=50e-9 +*.option savecurrents +*set the absolute voltage error tolerance and absolute current error tolerance +.control +save all +*dc v8 0 5 0.01 +tran 1n 10u +.endc + + +"} +C {netlist_not_shown.sym} -230 -200 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/cells/diode_pd2nw_05v5/sky130_fd_pr__diode_pd2nw_05v5.model.spice +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/cells/diode_pw2nd_05v5/sky130_fd_pr__diode_pw2nd_05v5.model.spice +*.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice + + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {vsource.sym} -130 200 0 0 {name=V3 value=1.8} +C {lab_wire.sym} -130 150 0 0 {name=l5 sig_type=std_logic lab=vdd} +C {gnd.sym} -20 280 0 0 {name=l12 lab=GND} +C {lab_wire.sym} 0 220 0 1 {name=l6 sig_type=std_logic lab=vin} +C {gnd.sym} 130 320 0 0 {name=l2 lab=GND} +C {gnd.sym} -130 460 0 0 {name=l4 lab=GND} +C {lab_wire.sym} 300 110 0 0 {name=l1 sig_type=std_logic lab=vdd} +C {isource.sym} -20 250 2 0 {name=I0 value=10} +C {sky130_fd_pr/diode.sym} -240 360 2 0 {name=D4 +model=diode_pd2nw_05v5 +area=22500 +} +C {sky130_fd_pr/diode.sym} -240 270 2 0 {name=D1 +model=diode_pd2nw_05v5 +area=22500 +} +C {sky130_fd_pr/diode.sym} -240 180 2 0 {name=D2 +model=diode_pd2nw_05v5 +area=22500 +} +C {sky130_fd_pr/diode.sym} -240 430 2 0 {name=D3 +model=diode_pd2nw_05v5 +area=22500 +}
diff --git a/xschem/src/integrator/integrator.sch b/xschem/src/integrator/integrator.sch new file mode 100644 index 0000000..c53f5e3 --- /dev/null +++ b/xschem/src/integrator/integrator.sch
@@ -0,0 +1,48 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 0 -140 30 -140 { lab=vout} +N -40 -50 30 -50 { lab=vout} +N 30 -140 30 -50 { lab=vout} +N -160 -50 -100 -50 { lab=vi} +N -50 -190 -50 -160 { lab=vdd} +N -50 -120 -50 -100 { lab=vss} +N -130 -160 -110 -160 { lab=vref} +N -140 -160 -130 -160 { lab=vref} +N -180 -120 -110 -120 { lab=vbias} +N 30 -140 70 -140 { lab=vout} +N -300 -50 -160 -50 { lab=vi} +N -300 -140 -300 -50 { lab=vi} +N -170 -140 -110 -140 { lab=vi} +N -300 -140 -170 -140 { lab=vi} +N -450 -140 -380 -140 { lab=vi} +N -460 -110 -380 -110 { lab=vbias} +N -460 -140 -450 -140 { lab=vi} +N -450 -180 -380 -180 { lab=vdd} +N -440 -80 -380 -80 { lab=vss} +N -450 -80 -440 -80 { lab=vss} +N 70 -140 90 -140 { lab=vout} +N -380 -140 -300 -140 { lab=vi} +N -450 -50 -380 -50 { lab=vref} +C {lab_wire.sym} -50 -190 2 1 {name=l2 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -120 -120 2 1 {name=l15 sig_type=std_logic lab=vbias} +C {lab_wire.sym} -130 -160 0 0 {name=l17 sig_type=std_logic lab=vref} +C {lab_wire.sym} 70 -140 2 0 {name=l10 sig_type=std_logic lab=vout} +C {src/OTA_int/OTA_int.sym} -50 -120 0 0 {name=x1} +C {lab_wire.sym} -300 -80 2 0 {name=l1 sig_type=std_logic lab=vi} +C {sky130_fd_pr/cap_mim_m3_1.sym} -70 -50 3 0 {name=C1 model=cap_mim_m3_1 W=17.5 L=17.5 MF=16 spiceprefix=X} +C {lab_wire.sym} -50 -100 2 1 {name=l3 sig_type=std_logic lab=vss} +C {ipin.sym} -450 -140 0 0 {name=p4 lab=vi} +C {ipin.sym} -450 -110 0 0 {name=p6 lab=vbias} +C {lab_wire.sym} -390 -110 0 0 {name=l5 sig_type=std_logic lab=vbias} +C {iopin.sym} -450 -80 0 1 {name=p2 lab=vss} +C {lab_wire.sym} -410 -140 0 1 {name=l9 sig_type=std_logic lab=vi} +C {lab_wire.sym} -390 -180 0 1 {name=l4 sig_type=std_logic lab=vdd} +C {iopin.sym} -450 -180 0 1 {name=p7 lab=vdd} +C {lab_wire.sym} -400 -80 0 0 {name=l18 sig_type=std_logic lab=vss} +C {opin.sym} 90 -140 0 0 {name=p1 lab=vout} +C {ipin.sym} -450 -50 0 0 {name=p3 lab=vref} +C {lab_wire.sym} -410 -50 0 0 {name=l6 sig_type=std_logic lab=vref}
diff --git a/xschem/src/integrator/integrator.sym b/xschem/src/integrator/integrator.sym new file mode 100644 index 0000000..902f24f --- /dev/null +++ b/xschem/src/integrator/integrator.sym
@@ -0,0 +1,31 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -30 130 -30 {} +L 4 -130 30 130 30 {} +L 4 -130 -30 -130 30 {} +L 4 130 -30 130 30 {} +L 4 130 0 150 0 {} +L 4 -150 -20 -130 -20 {} +L 4 -150 0 -130 0 {} +L 4 -150 20 -130 20 {} +B 5 -2.5 -32.5 2.5 -27.5 {name=vdd dir=inout } +B 5 -152.5 -22.5 -147.5 -17.5 {name=vi dir=in } +B 5 -152.5 -2.5 -147.5 2.5 {name=vbias dir=in } +B 5 -152.5 17.5 -147.5 22.5 {name=vref dir=in } +B 5 -2.5 27.5 2.5 32.5 {name=vss dir=inout } +B 5 147.5 -2.5 152.5 2.5 {name=vout dir=out } +T {@symname} -63 -6 0 0 0.3 0.3 {} +T {@name} 135 -42 0 0 0.2 0.2 {} +T {vdd} 5 -24 0 1 0.2 0.2 {} +T {vout} 125 -4 0 1 0.2 0.2 {} +T {vi} -125 -24 0 0 0.2 0.2 {} +T {vbias} -125 -4 0 0 0.2 0.2 {} +T {vss} 5 16 0 1 0.2 0.2 {} +T {vref} -125 16 0 0 0.2 0.2 {}
diff --git a/xschem/src/integrator/integrator_post.sym b/xschem/src/integrator/integrator_post.sym new file mode 100644 index 0000000..d400f0a --- /dev/null +++ b/xschem/src/integrator/integrator_post.sym
@@ -0,0 +1,31 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -10 -30 250 -30 {} +L 4 -10 30 250 30 {} +L 4 -10 -30 -10 30 {} +L 4 250 -30 250 30 {} +L 4 250 0 270 0 {} +L 4 -30 -20 -10 -20 {} +L 4 -30 0 -10 0 {} +L 4 -30 20 -10 20 {} +B 5 117.5 -32.5 122.5 -27.5 {name=vdd dir=inout } +B 5 -32.5 -22.5 -27.5 -17.5 {name=vi dir=in } +B 5 -32.5 -2.5 -27.5 2.5 {name=vbias dir=in } +B 5 -32.5 17.5 -27.5 22.5 {name=vref dir=in } +B 5 117.5 27.5 122.5 32.5 {name=vss dir=inout } +B 5 267.5 -2.5 272.5 2.5 {name=vout dir=out } +T {@symname} 57 -6 0 0 0.3 0.3 {} +T {@name} 255 -42 0 0 0.2 0.2 {} +T {vdd} 125 -24 0 1 0.2 0.2 {} +T {vout} 245 -4 0 1 0.2 0.2 {} +T {vi} -5 -24 0 0 0.2 0.2 {} +T {vbias} -5 -4 0 0 0.2 0.2 {} +T {vss} 125 16 0 1 0.2 0.2 {} +T {vref} -5 16 0 0 0.2 0.2 {}
diff --git a/xschem/src/integrator/integrator_tb.sch b/xschem/src/integrator/integrator_tb.sch new file mode 100644 index 0000000..6143a50 --- /dev/null +++ b/xschem/src/integrator/integrator_tb.sch
@@ -0,0 +1,132 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -300 -270 -300 -250 { lab=vdd} +N -300 -270 -280 -270 { lab=vdd} +N -370 -280 -370 -250 { lab=vp} +N -300 -190 -300 -160 { lab=GND} +N -370 -190 -370 -170 { lab=GND} +N -580 -120 -580 -40 { lab=#net1} +N -580 -90 -510 -90 { lab=#net1} +N -580 -200 -580 -180 { lab=vdd} +N -580 20 -580 30 { lab=GND} +N -580 -10 -580 20 { lab=GND} +N -540 -10 -500 -10 { lab=#net1} +N -510 -90 -510 -10 { lab=#net1} +N -500 -10 -460 -10 { lab=#net1} +N -410 30 -410 60 { lab=GND} +N -510 30 -490 30 { lab=vbias} +N -510 30 -510 110 { lab=vbias} +N -460 30 -430 30 { lab=GND} +N -430 30 -410 30 { lab=GND} +N -350 -10 -350 0 { lab=GND} +N -350 -100 -350 -70 { lab=vin} +N 50 -150 50 -120 { lab=vdd} +N 50 -60 50 -20 { lab=GND} +N -140 -110 -100 -110 { lab=v1} +N -140 -90 -100 -90 { lab=vbias} +N -140 -70 -100 -70 { lab=vp} +N 200 -90 240 -90 { lab=vout} +N -320 -110 -200 -110 { lab=vin} +C {isource.sym} -580 -150 0 0 {name=I0 value=15u} +C {vsource.sym} -370 -220 0 0 {name=V1 value=0.9} +C {vsource.sym} -300 -220 0 0 {name=V3 value=1.8} +C {lab_wire.sym} -280 -270 0 0 {name=l7 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -370 -270 0 0 {name=l10 sig_type=std_logic lab=vp} +C {code_shown.sym} 330 -420 0 0 {name=s1 only_toplevel=false value=" +.nodeset v(v1)=0.9 v(vout)=0.9 +.control + +save vout +op +*tran 10n 500u +*plot @m.xm7.msky130_fd_pr__pfet_01v8_lvt[id] +*plot @m.xm8.msky130_fd_pr__nfet_01v8_lvt[id] +*dc V2 0 1.8 0.01 +*print @m.xm2.msky130_fd_pr__pfet_01v8_lvt[gm] +*print @m.xm5.msky130_fd_pr__nfet_01v8_lvt[gm] +*print @m.xm3.msky130_fd_pr__pfet_01v8_lvt[gm] +*print vbias +ac dec 10000 0.1 100G +*meas ac GBW when vdb(vout)=0 +*meas ac DC_Gain find vdb(vout) at=1000 +*meas ac PM find vp(vout2) when vdb(vout2)=0 +*print PM*180/PI +*plot vdb(vout1)-20*log10(1+vout2) vdb(vout3) +plot vdb(vout) vp(vout)*180/pi + + +.endc +"} +C {netlist_not_shown.sym} -320 -430 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_tri_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_revised_post.spice +.include /home/eda/magic/class_d_audio_amplifier/integrator/integrator_post.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {gnd.sym} -370 -170 0 0 {name=l9 lab=GND} +C {gnd.sym} -300 -160 0 0 {name=l3 lab=GND} +C {lab_wire.sym} -580 -200 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} -580 30 0 0 {name=l18 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -560 -10 0 1 {name=M9 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -460 10 3 1 {name=M10 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} -410 60 0 0 {name=l54 lab=GND} +C {lab_wire.sym} -510 110 0 0 {name=l19 sig_type=std_logic lab=vbias} +C {gnd.sym} -350 0 0 0 {name=l20 lab=GND} +C {lab_wire.sym} -350 -90 0 0 {name=l22 sig_type=std_logic lab=vin} +C {vsource.sym} -350 -40 0 0 {name=V2 value="dc 0.9 ac 1"} +C {src/integrator/integrator_post.sym} -70 -90 0 0 {name=x1} +C {lab_wire.sym} 50 -140 0 0 {name=l1 sig_type=std_logic lab=vdd} +C {gnd.sym} 50 -20 0 0 {name=l2 lab=GND} +C {lab_wire.sym} -310 -110 0 0 {name=l4 sig_type=std_logic lab=vin} +C {lab_wire.sym} -130 -90 0 0 {name=l5 sig_type=std_logic lab=vbias} +C {lab_wire.sym} -130 -70 0 0 {name=l6 sig_type=std_logic lab=vp} +C {lab_wire.sym} 240 -90 0 0 {name=l8 sig_type=std_logic lab=vout} +C {res.sym} -170 -110 1 0 {name=R1 +value=200k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} -110 -110 0 0 {name=l11 sig_type=std_logic lab=v1}
diff --git a/xschem/src/inverter/inverter.sch b/xschem/src/inverter/inverter.sch new file mode 100644 index 0000000..53e2e01 --- /dev/null +++ b/xschem/src/inverter/inverter.sch
@@ -0,0 +1,52 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -20 -1600 -20 -1550 { lab=B} +N -60 -1630 -60 -1520 { lab=A} +N -20 -1490 -20 -1480 { lab=gnd} +N -20 -1520 10 -1520 { lab=gnd} +N 10 -1520 10 -1490 { lab=gnd} +N -20 -1680 -20 -1660 { lab=vdd} +N -20 -1490 10 -1490 { lab=gnd} +N -20 -1580 80 -1580 { lab=B} +N -110 -1580 -60 -1580 { lab=A} +N -20 -1700 -20 -1680 { lab=vdd} +N -20 -1480 -20 -1460 { lab=gnd} +N -20 -1630 -0 -1630 { lab=vdd} +N -0 -1660 -0 -1630 { lab=vdd} +N -20 -1660 0 -1660 { lab=vdd} +C {sky130_fd_pr/nfet_01v8.sym} -40 -1520 0 0 {name=M3 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} -40 -1630 0 0 {name=M1 +L=0.15 +W=2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {iopin.sym} -20 -1700 0 0 {name=p1 lab=vdd} +C {iopin.sym} -20 -1460 0 0 {name=p2 lab=vss} +C {ipin.sym} -110 -1580 0 0 {name=p3 lab=A} +C {opin.sym} 80 -1580 0 0 {name=p4 lab=B}
diff --git a/xschem/src/inverter/inverter.sym b/xschem/src/inverter/inverter.sym new file mode 100644 index 0000000..b0be24d --- /dev/null +++ b/xschem/src/inverter/inverter.sym
@@ -0,0 +1,20 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -40 -30 -40 30 {} +L 4 -40 30 0 0 {} +L 4 -40 -30 0 0 {} +L 4 -50 -0 -40 -0 {} +L 4 20 -0 30 -0 {} +B 5 -22.5 -22.5 -17.5 -17.5 {name=vdd dir=inout } +B 5 -52.5 -2.5 -47.5 2.5 {name=A dir=in } +B 5 27.5 -2.5 32.5 2.5 {name=B dir=out } +B 5 -22.5 17.5 -17.5 22.5 {name=vss dir=inout } +A 4 10 -0 10 180 360 {} +T {vdd} -30 -10 0 0 0.1 0.1 {}
diff --git a/xschem/src/inverter/inverter_tb.sch b/xschem/src/inverter/inverter_tb.sch new file mode 100644 index 0000000..c27bc97 --- /dev/null +++ b/xschem/src/inverter/inverter_tb.sch
@@ -0,0 +1,87 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 430 -1650 430 -1630 { lab=vdd} +N 530 -1510 550 -1510 { lab=out} +N 310 -1510 340 -1510 { lab=in} +N -220 -1660 -220 -1610 { lab=vdd} +N -220 -1550 -220 -1510 { lab=GND} +N 280 -1510 310 -1510 { lab=in} +N 550 -1510 580 -1510 { lab=out} +N 430 -1530 430 -1480 { lab=out} +N 390 -1560 390 -1450 { lab=in} +N 430 -1420 430 -1410 { lab=GND} +N 430 -1450 460 -1450 { lab=GND} +N 460 -1450 460 -1420 { lab=GND} +N 430 -1610 430 -1590 { lab=vdd} +N 430 -1420 460 -1420 { lab=GND} +N 430 -1510 530 -1510 { lab=out} +N 340 -1510 390 -1510 { lab=in} +N 430 -1630 430 -1610 { lab=vdd} +N 430 -1410 430 -1390 { lab=GND} +N 430 -1560 450 -1560 { lab=vdd} +N 450 -1590 450 -1560 { lab=vdd} +N 430 -1590 450 -1590 { lab=vdd} +C {netlist_not_shown.sym} -70 -1840 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice + + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {vsource.sym} -220 -1580 0 0 {name=V1 value=1.8} +C {gnd.sym} -220 -1510 0 0 {name=l1 lab=GND} +C {lab_wire.sym} -220 -1650 0 0 {name=l2 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 430 -1650 0 0 {name=l3 sig_type=std_logic lab=vdd} +C {vsource.sym} 280 -1480 0 0 {name=V2 value="pulse(0 1.8 0 1n 1n 1u 2u 0)"} +C {gnd.sym} 280 -1450 0 0 {name=l5 lab=GND} +C {code_shown.sym} 230 -1700 0 0 {name=s1 only_toplevel=false value=" +.control +save all +tran 10n 10u +.endc + +"} +C {lab_wire.sym} 570 -1510 0 0 {name=l6 sig_type=std_logic lab=out} +C {lab_wire.sym} 310 -1510 0 0 {name=l7 sig_type=std_logic lab=in} +C {sky130_fd_pr/nfet_01v8.sym} 410 -1450 0 0 {name=M3 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 410 -1560 0 0 {name=M1 +L=0.15 +W=2 +nf=2 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {gnd.sym} 430 -1390 0 0 {name=l8 lab=GND}
diff --git a/xschem/src/nand/nand.sch b/xschem/src/nand/nand.sch new file mode 100644 index 0000000..98396b0 --- /dev/null +++ b/xschem/src/nand/nand.sch
@@ -0,0 +1,88 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 20 -140 180 -140 { lab=vdd} +N 20 -140 20 -110 { lab=vdd} +N 180 -140 180 -110 { lab=vdd} +N 20 -80 180 -80 { lab=out} +N 90 -80 90 -0 { lab=out} +N 90 60 90 90 { lab=#net1} +N 90 120 90 150 { lab=vss} +N -80 30 50 30 { lab=A} +N -50 -110 -50 30 { lab=A} +N -50 -110 -20 -110 { lab=A} +N -80 120 50 120 { lab=B} +N 30 -110 30 120 { lab=B} +N 30 -110 140 -110 { lab=B} +N 20 -210 90 -210 { lab=vdd} +N 90 -210 90 -140 { lab=vdd} +N 90 150 90 190 { lab=vss} +N 40 190 90 190 { lab=vss} +N 90 -20 180 -20 { lab=out} +N 90 30 110 30 { lab=vss} +N 110 30 110 190 { lab=vss} +N 90 190 110 190 { lab=vss} +C {sky130_fd_pr/nfet_01v8.sym} 70 30 0 0 {name=M1 +L=0.15 +W=2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 0 -110 0 0 {name=M2 +L=0.15 +W=2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 70 120 0 0 {name=M3 +L=0.15 +W=2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 160 -110 0 0 {name=M4 +L=0.15 +W=2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {ipin.sym} -70 30 0 0 {name=p3 lab=A} +C {ipin.sym} -70 120 0 0 {name=p4 lab=B} +C {opin.sym} 180 -20 0 0 {name=p5 lab=out} +C {iopin.sym} 20 -210 0 1 {name=p1 lab=vdd} +C {iopin.sym} 40 190 0 1 {name=p2 lab=vss}
diff --git a/xschem/src/nand/nand.sym b/xschem/src/nand/nand.sym new file mode 100644 index 0000000..fa83394 --- /dev/null +++ b/xschem/src/nand/nand.sym
@@ -0,0 +1,20 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -60 -30 -20 -30 {} +L 4 -60 30 -20 30 {} +L 4 -60 -30 -60 30 {} +B 5 -42.5 -32.5 -37.5 -27.5 {name=vdd dir=inout } +B 5 7.5 -2.5 12.5 2.5 {name=out dir=out } +B 5 -62.5 -12.5 -57.5 -7.5 {name=A dir=in } +B 5 -62.5 7.5 -57.5 12.5 {name=B dir=in } +B 5 -42.5 27.5 -37.5 32.5 {name=vss dir=inout } +A 4 -30 0 31.62277660168379 288.434948822922 143.130102354156 {} +A 4 10 -0 10 90 360 {} +T {vdd} -50 -20 0 0 0.2 0.2 {}
diff --git a/xschem/src/openloop/openloop.sch b/xschem/src/openloop/openloop.sch new file mode 100644 index 0000000..470e705 --- /dev/null +++ b/xschem/src/openloop/openloop.sch
@@ -0,0 +1,109 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -190 140 -190 160 { lab=vdd} +N -120 140 -120 160 { lab=vbias} +N 220 60 250 60 { lab=vt} +N 240 -70 290 -70 { lab=vt} +N 50 60 90 60 { lab=vbias} +N 350 -90 350 -70 { lab=vdd} +N 150 -0 150 30 { lab=vdd} +N 150 110 150 130 { lab=GND} +N 350 -30 350 -10 { lab=GND} +N 400 -50 440 -50 { lab=vpwm} +N -130 -100 -130 -20 { lab=vref} +N -130 -70 -60 -70 { lab=vref} +N -130 -160 -130 -130 { lab=vdd} +N -130 -180 -130 -160 { lab=vdd} +N -90 -130 -90 -70 { lab=vref} +N -130 40 -130 50 { lab=GND} +N 40 90 90 90 { lab=vref} +N 240 -30 290 -30 { lab=vref} +N -300 140 -300 160 { lab=vin} +N 240 -50 290 -50 { lab=vin} +N 470 -100 470 -70 { lab=vdd} +N 470 -30 470 -10 { lab=GND} +N 520 -50 550 -50 { lab=vout} +C {src/triangle/triangle.sym} 150 70 0 0 {name=x1} +C {src/OTA/OTA.sym} 380 -150 0 0 {name=x2} +C {vsource.sym} -120 190 0 0 {name=V1 value=0.9} +C {vsource.sym} -190 190 0 0 {name=V2 value=1.8} +C {gnd.sym} -190 220 0 0 {name=l1 lab=GND} +C {gnd.sym} -120 220 0 0 {name=l2 lab=GND} +C {lab_wire.sym} -190 140 0 0 {name=l3 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 240 60 0 1 {name=l4 sig_type=std_logic lab=vt} +C {lab_wire.sym} 250 -70 0 1 {name=l5 sig_type=std_logic lab=vt} +C {lab_wire.sym} -120 140 0 0 {name=l6 sig_type=std_logic lab=vbias} +C {lab_wire.sym} 70 60 0 0 {name=l7 sig_type=std_logic lab=vbias} +C {lab_wire.sym} 350 -90 0 0 {name=l8 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 150 10 0 0 {name=l9 sig_type=std_logic lab=vdd} +C {gnd.sym} 150 130 0 0 {name=l10 lab=GND} +C {gnd.sym} 350 -10 0 0 {name=l11 lab=GND} +C {sky130_fd_pr/pfet_01v8_lvt.sym} -110 -130 0 1 {name=M6 +L=1 +W=4 +nf=2 +mult=40 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_lvt +spiceprefix=X +} +C {isource.sym} -130 10 0 0 {name=I0 value=150u} +C {lab_wire.sym} -130 -180 0 0 {name=l13 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -60 -70 0 0 {name=l14 sig_type=std_logic lab=vref} +C {gnd.sym} -130 50 0 0 {name=l15 lab=GND} +C {lab_wire.sym} 50 90 0 0 {name=l16 sig_type=std_logic lab=vref} +C {lab_wire.sym} 270 -30 0 0 {name=l17 sig_type=std_logic lab=vref} +C {netlist_not_shown.sym} 20 -180 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice + + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {vsource.sym} -300 190 0 0 {name=V3 value="sin(0.915 0.35 5k)"} +C {gnd.sym} -300 220 0 0 {name=l18 lab=GND} +C {lab_wire.sym} -300 140 0 0 {name=l19 sig_type=std_logic lab=vin} +C {lab_wire.sym} 270 -50 0 0 {name=l20 sig_type=std_logic lab=vin} +C {src/inverter/inverter.sym} 490 -50 0 0 {name=x3} +C {lab_wire.sym} 470 -90 0 0 {name=l21 sig_type=std_logic lab=vdd} +C {gnd.sym} 470 -10 0 0 {name=l22 lab=GND} +C {capa.sym} 550 -20 0 0 {name=C1 +m=1 +value=1f +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 550 10 0 0 {name=l23 lab=GND} +C {code_shown.sym} 490 110 0 0 {name=s1 only_toplevel=false value=" +.control +save all +tran 1n 1m +*fourier 5k V(vpwm) +*fourier 5k V(vout) +*setplot tran1 +*linearize V(vout) +*fft V(vout) +*plot mag(V(vout)) +*setplot previous +write openloop.raw +.endc +"} +C {lab_wire.sym} 430 -50 0 0 {name=l24 sig_type=std_logic lab=vpwm} +C {lab_wire.sym} 540 -50 0 0 {name=l25 sig_type=std_logic lab=vout}
diff --git a/xschem/src/output_driver/half_driver.sch b/xschem/src/output_driver/half_driver.sch new file mode 100644 index 0000000..2eedc76 --- /dev/null +++ b/xschem/src/output_driver/half_driver.sch
@@ -0,0 +1,74 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -10 -120 -10 -100 { lab=vdd} +N -10 180 -10 190 { lab=vss} +N 0 40 10 40 { lab=out_p} +N -10 250 -10 270 { lab=vss} +N -10 40 0 40 { lab=out_p} +N -80 -30 -50 -30 { lab=vp_p} +N -80 110 -50 110 { lab=vp_n} +N -10 150 10 150 { lab=vss} +N 10 150 10 190 { lab=vss} +N -10 190 10 190 { lab=vss} +N -10 -70 10 -70 { lab=vdd} +N 10 -110 10 -70 { lab=vdd} +N -10 -110 10 -110 { lab=vdd} +N 10 40 50 40 { lab=out_p} +N -10 190 -10 250 { lab=vss} +N -10 110 -10 120 { lab=out_p} +N -10 30 -10 50 { lab=out_p} +N -10 -40 -10 -30 { lab=out_p} +N -50 110 -50 150 { lab=vp_n} +N -50 -70 -50 -30 { lab=vp_p} +N -10 -30 -10 110 { lab=out_p} +N -100 -30 -80 -30 { lab=vp_p} +N -210 110 -80 110 { lab=vp_n} +N -200 -30 -100 -30 { lab=vp_p} +N 50 40 70 40 { lab=out_p} +N -370 -120 -310 -120 { lab=vdd} +N -370 -60 -310 -60 { lab=vss} +C {lab_wire.sym} 10 40 0 1 {name=l15 sig_type=std_logic lab=out_p} +C {sky130_fd_pr/pfet_01v8.sym} -30 -70 0 0 {name=M1 +L=0.15 +W=12000 +nf=200 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} -30 150 0 0 {name=M2 +L=0.15 +W=2400 +nf=100 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {lab_wire.sym} -90 -30 0 0 {name=l49 sig_type=std_logic lab=vp_p} +C {lab_wire.sym} -70 110 0 0 {name=l50 sig_type=std_logic lab=vp_n} +C {lab_wire.sym} -10 -120 0 0 {name=l31 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -10 260 0 0 {name=l1 sig_type=std_logic lab=vss} +C {ipin.sym} -190 -30 0 0 {name=p1 lab=vp_p} +C {ipin.sym} -200 110 0 0 {name=p2 lab=vp_n +} +C {opin.sym} 70 40 0 0 {name=p5 lab=out_p} +C {iopin.sym} -380 -120 0 0 {name=p3 lab=vdd} +C {iopin.sym} -380 -60 0 0 {name=p4 lab=vss} +C {lab_wire.sym} -320 -120 0 1 {name=l2 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -320 -60 0 1 {name=l3 sig_type=std_logic lab=vss}
diff --git a/xschem/src/output_driver/half_driver.sym b/xschem/src/output_driver/half_driver.sym new file mode 100644 index 0000000..fc29c20 --- /dev/null +++ b/xschem/src/output_driver/half_driver.sym
@@ -0,0 +1,28 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -30 130 -30 {} +L 4 -130 30 130 30 {} +L 4 -130 -30 -130 30 {} +L 4 130 -30 130 30 {} +L 4 -150 -20 -130 -20 {} +L 4 130 0 150 0 {} +L 4 -150 20 -130 20 {} +B 5 -2.5 -32.5 2.5 -27.5 {name=vdd dir=inout } +B 5 -2.5 27.5 2.5 32.5 {name=vss dir=inout } +B 5 -152.5 -22.5 -147.5 -17.5 {name=vp_p dir=in } +B 5 147.5 -2.5 152.5 2.5 {name=out_p dir=out } +B 5 -152.5 17.5 -147.5 22.5 {name=vp_n dir=in } +T {@symname} -67.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -42 0 0 0.2 0.2 {} +T {vdd} 5 -24 0 1 0.2 0.2 {} +T {vss} 5 16 0 1 0.2 0.2 {} +T {vp_p} -125 -24 0 0 0.2 0.2 {} +T {out_p} 125 -4 0 1 0.2 0.2 {} +T {vp_n} -125 16 0 0 0.2 0.2 {}
diff --git a/xschem/src/output_driver/half_driver_post.sym b/xschem/src/output_driver/half_driver_post.sym new file mode 100644 index 0000000..53e3897 --- /dev/null +++ b/xschem/src/output_driver/half_driver_post.sym
@@ -0,0 +1,28 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -30 -30 230 -30 {} +L 4 -30 30 230 30 {} +L 4 -30 -30 -30 30 {} +L 4 230 -30 230 30 {} +L 4 -50 -20 -30 -20 {} +L 4 230 0 250 0 {} +L 4 -50 20 -30 20 {} +B 5 97.5 -32.5 102.5 -27.5 {name=vdd dir=inout } +B 5 97.5 27.5 102.5 32.5 {name=vss dir=inout } +B 5 -52.5 -22.5 -47.5 -17.5 {name=vp_p dir=in } +B 5 247.5 -2.5 252.5 2.5 {name=out_p dir=out } +B 5 -52.5 17.5 -47.5 22.5 {name=vp_n dir=in } +T {@symname} 32.5 -6 0 0 0.3 0.3 {} +T {@name} 235 -42 0 0 0.2 0.2 {} +T {vdd} 105 -24 0 1 0.2 0.2 {} +T {vss} 105 16 0 1 0.2 0.2 {} +T {vp_p} -25 -24 0 0 0.2 0.2 {} +T {out_p} 225 -4 0 1 0.2 0.2 {} +T {vp_n} -25 16 0 0 0.2 0.2 {}
diff --git a/xschem/src/output_driver/output_driver.sch b/xschem/src/output_driver/output_driver.sch new file mode 100644 index 0000000..703fc1f --- /dev/null +++ b/xschem/src/output_driver/output_driver.sch
@@ -0,0 +1,40 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 770 -250 770 -230 { lab=dvdd1} +N 770 -110 770 -90 { lab=vss} +N 920 -200 960 -200 { lab=out_p} +N 770 -170 770 -110 { lab=vss} +N 960 -200 980 -200 { lab=out_p} +N 360 -250 420 -250 { lab=dvdd1} +N 360 -190 420 -190 { lab=vss} +N 600 -220 620 -220 { lab=vp_p} +N 600 -180 620 -180 { lab=vp_n} +N 600 -0 620 -0 { lab=vn_p} +N 600 40 620 40 { lab=vn_n} +N 920 20 990 20 { lab=out_n} +N 770 -40 770 -10 { lab=dvdd2} +N 770 50 770 80 { lab=vss} +N 360 -130 420 -130 { lab=dvdd2} +C {lab_wire.sym} 770 -250 0 0 {name=l31 sig_type=std_logic lab=dvdd1} +C {lab_wire.sym} 770 -100 0 0 {name=l1 sig_type=std_logic lab=vss} +C {ipin.sym} 610 -220 0 0 {name=p1 lab=vp_p} +C {ipin.sym} 610 -180 0 0 {name=p2 lab=vp_n +} +C {ipin.sym} 610 0 0 0 {name=p3 lab=vn_p} +C {ipin.sym} 610 40 0 0 {name=p4 lab=vn_n} +C {opin.sym} 980 -200 0 0 {name=p5 lab=out_p} +C {opin.sym} 980 20 0 0 {name=p6 lab=out_n} +C {iopin.sym} 350 -250 0 0 {name=p7 lab=dvdd1} +C {iopin.sym} 350 -190 0 0 {name=p8 lab=vss} +C {lab_wire.sym} 420 -190 0 1 {name=l3 sig_type=std_logic lab=vss} +C {lab_wire.sym} 410 -250 0 1 {name=l4 sig_type=std_logic lab=dvdd1} +C {lab_wire.sym} 770 -30 0 0 {name=l2 sig_type=std_logic lab=dvdd2} +C {lab_wire.sym} 770 80 0 0 {name=l5 sig_type=std_logic lab=vss} +C {iopin.sym} 350 -130 0 0 {name=p9 lab=dvdd2} +C {lab_wire.sym} 410 -130 0 1 {name=l6 sig_type=std_logic lab=dvdd2} +C {src/output_driver/half_driver.sym} 770 -200 0 0 {name=x1} +C {src/output_driver/half_driver.sym} 770 20 0 0 {name=x2}
diff --git a/xschem/src/output_driver/output_driver.sym b/xschem/src/output_driver/output_driver.sym new file mode 100644 index 0000000..a814148 --- /dev/null +++ b/xschem/src/output_driver/output_driver.sym
@@ -0,0 +1,39 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -50 130 -50 {} +L 4 -130 50 130 50 {} +L 4 -130 -50 -130 50 {} +L 4 130 -50 130 50 {} +L 4 -150 -30 -130 -30 {} +L 4 130 -10 150 -10 {} +L 4 -150 -10 -130 -10 {} +L 4 -150 10 -130 10 {} +L 4 130 10 150 10 {} +L 4 -150 30 -130 30 {} +B 5 -22.5 -52.5 -17.5 -47.5 {name=dvdd1 dir=inout } +B 5 -152.5 -32.5 -147.5 -27.5 {name=vp_p dir=in } +B 5 147.5 -12.5 152.5 -7.5 {name=out_p dir=out } +B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout } +B 5 -152.5 -12.5 -147.5 -7.5 {name=vp_n dir=in } +B 5 7.5 -52.5 12.5 -47.5 {name=dvdd2 dir=inout } +B 5 -152.5 7.5 -147.5 12.5 {name=vn_p dir=in } +B 5 147.5 7.5 152.5 12.5 {name=out_n dir=out } +B 5 -152.5 27.5 -147.5 32.5 {name=vn_n dir=in } +T {@symname} -76.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -62 0 0 0.2 0.2 {} +T {dvdd1} -15 -44 0 1 0.2 0.2 {} +T {vp_p} -125 -34 0 0 0.2 0.2 {} +T {out_p} 125 -14 0 1 0.2 0.2 {} +T {vss} 5 36 0 1 0.2 0.2 {} +T {vp_n} -125 -14 0 0 0.2 0.2 {} +T {dvdd2} 25 -44 0 1 0.2 0.2 {} +T {vn_p} -125 6 0 0 0.2 0.2 {} +T {out_n} 125 6 0 1 0.2 0.2 {} +T {vn_n} -125 26 0 0 0.2 0.2 {}
diff --git a/xschem/src/output_driver/output_driver_post.sym b/xschem/src/output_driver/output_driver_post.sym new file mode 100644 index 0000000..db69186 --- /dev/null +++ b/xschem/src/output_driver/output_driver_post.sym
@@ -0,0 +1,39 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -150 -50 110 -50 {} +L 4 -150 30 110 30 {} +L 4 -150 -50 -150 30 {} +L 4 110 -50 110 30 {} +L 4 -170 -40 -150 -40 {} +L 4 110 -20 130 -20 {} +L 4 -170 -20 -150 -20 {} +L 4 -170 0 -150 0 {} +L 4 110 0 130 0 {} +L 4 -170 20 -150 20 {} +B 5 -22.5 -52.5 -17.5 -47.5 {name=dvdd1 dir=inout } +B 5 -172.5 -42.5 -167.5 -37.5 {name=vp_p dir=in } +B 5 127.5 -22.5 132.5 -17.5 {name=out_p dir=out } +B 5 -22.5 27.5 -17.5 32.5 {name=vss dir=inout } +B 5 -172.5 -22.5 -167.5 -17.5 {name=vp_n dir=in } +B 5 -172.5 -2.5 -167.5 2.5 {name=vn_p dir=in } +B 5 127.5 -2.5 132.5 2.5 {name=out_n dir=out } +B 5 -172.5 17.5 -167.5 22.5 {name=vn_n dir=in } +B 5 -52.5 -52.5 -47.5 -47.5 {name=dvdd2 dir=inout } +T {@symname} -96.5 -16 0 0 0.3 0.3 {} +T {@name} 115 -62 0 0 0.2 0.2 {} +T {vdd1} -15 -44 0 1 0.2 0.2 {} +T {vp_p} -145 -44 0 0 0.2 0.2 {} +T {out_p} 105 -24 0 1 0.2 0.2 {} +T {vss} -15 16 0 1 0.2 0.2 {} +T {vp_n} -145 -24 0 0 0.2 0.2 {} +T {vn_p} -145 -4 0 0 0.2 0.2 {} +T {out_n} 105 -4 0 1 0.2 0.2 {} +T {vn_n} -145 16 0 0 0.2 0.2 {} +T {vdd2} -45 -44 0 1 0.2 0.2 {}
diff --git a/xschem/src/output_driver/output_driver_tb.sch b/xschem/src/output_driver/output_driver_tb.sch new file mode 100644 index 0000000..75363ff --- /dev/null +++ b/xschem/src/output_driver/output_driver_tb.sch
@@ -0,0 +1,135 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -180 40 -180 80 { lab=vdd1} +N 450 30 450 70 { lab=vdd2} +N 210 210 210 310 { lab=in_n} +N 160 90 160 230 { lab=in_p} +N 160 90 280 90 { lab=in_p} +N 160 110 280 110 { lab=in_p} +N 440 180 440 190 { lab=GND} +N 440 170 440 180 { lab=GND} +N 600 130 600 340 { lab=out_n} +N 590 130 600 130 { lab=out_n} +N 590 -100 590 110 { lab=out_p} +N 280 90 290 90 { lab=in_p} +N 280 110 290 110 { lab=in_p} +N 210 130 210 210 { lab=in_n} +N 210 130 290 130 { lab=in_n} +N 210 150 290 150 { lab=in_n} +N 420 40 420 70 { lab=vdd1} +N 780 -90 860 -90 { lab=audio_p} +N 800 -90 800 -80 { lab=audio_p} +N 800 380 800 400 { lab=GND} +N 770 320 800 320 { lab=audio_n} +N 800 320 860 320 { lab=audio_n} +N 700 320 710 320 { lab=#net1} +N 700 320 700 340 { lab=#net1} +N 700 -90 720 -90 { lab=#net2} +N 700 -100 700 -90 { lab=#net2} +N 860 -30 860 -0 { lab=audio_n} +N 590 -100 630 -100 { lab=out_p} +N 690 -100 700 -100 { lab=#net2} +N 600 340 640 340 { lab=out_n} +N -90 40 -90 80 { lab=vdd2} +N 860 -0 860 10 { lab=audio_n} +N 800 -20 800 10 { lab=GND} +N 860 10 860 320 { lab=audio_n} +C {vsource.sym} -180 110 0 0 {name=V2 value=1.8} +C {gnd.sym} -180 140 0 0 {name=l1 lab=GND} +C {lab_wire.sym} -180 50 0 0 {name=l4 sig_type=std_logic lab=vdd1} +C {code_shown.sym} 1100 -280 0 0 {name=s1 only_toplevel=false value=" +.nodeset v(audio_p)=0 +.option rshunt=1e20 +.control +save in_p in_n out_p out_n audio_p audio_n i(v2) +*save all +tran 10n 1000u +*ac dec 1000 1 100 +*op +*plot (v(vpwm_p)-v(vdd))/@m.xm1.msky130_fd_pr__pfet_01v8_lvt[id] +*plot vpwm_p +*plot (v(vpwm_p))/@m.xm2.msky130_fd_pr__nfet_01v8_lvt[id] +*plot (vpwm_p1-v(vdd))/@m.xm6.msky130_fd_pr__pfet_01v8[id] +*plot vpwm_p1/@m.xm5.msky130_fd_pr__nfet_01v8[id] +let pout=2*(audio_p)*(audio_p)/4 +plot pout +let pin=1.8*i(v2) +meas tran p avg pin +*plot (V(vout_p)-v(vout_n))/4 + + +.endc + + + +"} +C {vsource.sym} 160 260 0 0 {name=V4 value="pulse(0 1.8 0 10n 10n 1u 2u 0)"} +C {gnd.sym} 160 290 0 0 {name=l17 lab=GND} +C {vsource.sym} 210 340 0 0 {name=V5 value="pulse(0 1.8 0 10n 10n 1u 2u 180)"} +C {gnd.sym} 210 370 0 0 {name=l26 lab=GND} +C {netlist_not_shown.sym} 230 -260 0 0 {name=TT_MODELS2 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice +.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_post.spice +.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_post.spice +.include /home/eda/magic/class_d_audio_amplifier/output_driver/output_driver_post.spice +.include /home/eda/magic/class_d_audio_amplifier/output_driver/half_driver_post.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {lab_wire.sym} 450 40 0 0 {name=l2 sig_type=std_logic lab=vdd2} +C {lab_wire.sym} 590 10 0 0 {name=l5 sig_type=std_logic lab=out_p} +C {lab_wire.sym} 600 290 0 0 {name=l6 sig_type=std_logic lab=out_n} +C {lab_wire.sym} 160 160 0 0 {name=l9 sig_type=std_logic lab=in_p} +C {lab_wire.sym} 210 280 0 0 {name=l10 sig_type=std_logic lab=in_n} +C {gnd.sym} 440 190 0 0 {name=l12 lab=GND} +C {lab_wire.sym} 420 50 0 0 {name=l3 sig_type=std_logic lab=vdd1} +C {ind.sym} 740 320 3 1 {name=L2 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 800 350 0 1 {name=C4 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {lab_wire.sym} 810 320 0 1 {name=l44 sig_type=std_logic lab=audio_n} +C {gnd.sym} 800 400 0 0 {name=l55 lab=GND} +C {res.sym} 860 -60 2 0 {name=R1 +value=8 +footprint=1206 +device=resistor +m=1} +C {vsource.sym} -90 110 0 0 {name=V1 value=1.8} +C {gnd.sym} -90 140 0 0 {name=l11 lab=GND} +C {lab_wire.sym} -90 60 0 0 {name=l13 sig_type=std_logic lab=vdd2} +C {vsource.sym} 670 340 1 0 {name=V3 value=0} +C {ind.sym} 750 -90 3 1 {name=L1 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 800 -50 0 1 {name=C1 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 800 10 0 0 {name=l14 lab=GND} +C {vsource.sym} 660 -100 1 0 {name=V6 value=0} +C {lab_wire.sym} 830 -90 0 1 {name=l7 sig_type=std_logic lab=audio_p} +C {src/output_driver/output_driver.sym} 440 120 0 0 {name=x1}
diff --git a/xschem/src/output_select/out_select.sch b/xschem/src/output_select/out_select.sch new file mode 100644 index 0000000..07d8579 --- /dev/null +++ b/xschem/src/output_select/out_select.sch
@@ -0,0 +1,218 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -570 -70 -500 -70 { lab=s0} +N -570 80 -500 80 { lab=s1} +N -420 -70 -270 -70 { lab=#net1} +N -520 20 -310 20 { lab=s1} +N -310 -50 -310 -20 { lab=s1} +N -310 -50 -270 -50 { lab=s1} +N -510 -70 -510 -30 { lab=s0} +N -510 -30 -380 -30 { lab=s0} +N -380 -30 -380 50 { lab=s0} +N -380 50 -270 50 { lab=s0} +N -420 80 -290 80 { lab=#net2} +N -290 70 -270 70 { lab=#net2} +N -290 70 -290 80 { lab=#net2} +N -310 -20 -310 20 { lab=s1} +N -520 30 -520 80 { lab=s1} +N -520 20 -520 30 { lab=s1} +N -380 50 -380 170 { lab=s0} +N -380 170 -270 170 { lab=s0} +N -400 20 -400 190 { lab=s1} +N -400 190 -270 190 { lab=s1} +N -200 -60 -40 -60 { lab=sel0} +N -200 60 -40 60 { lab=sel1} +N -200 180 -40 180 { lab=sel2} +N 140 410 140 450 { lab=#net3} +N 20 -140 60 -140 { lab=sel0} +N 30 170 60 170 { lab=sel1} +N 20 450 60 450 { lab=sel2} +N 20 170 30 170 { lab=sel1} +N -470 -130 -470 -90 { lab=vdd} +N -470 -50 -470 -40 { lab=vss} +N -470 40 -470 60 { lab=vdd} +N -470 100 -470 120 { lab=vss} +N -250 -120 -250 -90 { lab=vdd} +N -250 -30 -250 -10 { lab=vss} +N -250 10 -250 30 { lab=vdd} +N -250 90 -250 110 { lab=#net4} +N -250 130 -250 150 { lab=vdd} +N -250 210 -250 230 { lab=vss} +N 90 -180 90 -160 { lab=vdd} +N 90 -120 90 -100 { lab=vss} +N 90 120 90 150 { lab=vdd} +N 90 190 90 210 { lab=#net5} +N 90 410 90 430 { lab=vdd} +N 90 470 90 500 { lab=vss} +N 90 -320 110 -320 { lab=vin0} +N 90 -320 90 -210 { lab=vin0} +N 90 -210 110 -210 { lab=vin0} +N 170 -320 190 -320 { lab=vout0} +N 190 -320 190 -210 { lab=vout0} +N 170 -210 190 -210 { lab=vout0} +N 30 -260 90 -260 { lab=vin0} +N 190 -250 270 -250 { lab=vout0} +N 140 -390 140 -360 { lab=sel0} +N 140 -320 170 -320 { lab=vout0} +N 140 -210 170 -210 { lab=vout0} +N 90 -30 110 -30 { lab=vin1} +N 90 -30 90 80 { lab=vin1} +N 90 80 110 80 { lab=vin1} +N 170 -30 190 -30 { lab=vout1} +N 190 -30 190 80 { lab=vout1} +N 170 80 190 80 { lab=vout1} +N 30 30 90 30 { lab=vin1} +N 190 40 270 40 { lab=vout1} +N 140 -100 140 -70 { lab=sel1} +N 140 -30 170 -30 { lab=vout1} +N 140 80 170 80 { lab=vout1} +N 90 260 110 260 { lab=vin2} +N 90 260 90 370 { lab=vin2} +N 90 370 110 370 { lab=vin2} +N 170 260 190 260 { lab=vout2} +N 190 260 190 370 { lab=vout2} +N 170 370 190 370 { lab=vout2} +N 30 320 90 320 { lab=vin2} +N 190 330 270 330 { lab=vout2} +N 140 190 140 220 { lab=sel2} +N 140 410 140 450 { lab=#net3} +N 140 260 170 260 { lab=vout2} +N 140 370 170 370 { lab=vout2} +N 140 -160 140 -140 { lab=#net6} +N 140 -170 140 -160 { lab=#net6} +N 140 120 140 170 { lab=#net7} +N -370 -280 -290 -280 { lab=vdd} +N -370 -200 -290 -200 { lab=vss} +C {src/nand/nand.sym} -210 -60 0 0 {name=x4} +C {src/nand/nand.sym} -210 60 0 0 {name=x5} +C {src/nand/nand.sym} -210 180 0 0 {name=x6} +C {src/inverter/inverter.sym} -450 80 0 0 {name=x8} +C {src/inverter/inverter.sym} -450 -70 0 0 {name=x9} +C {lab_wire.sym} -540 -70 0 0 {name=l1 sig_type=std_logic lab=s0} +C {lab_wire.sym} -540 80 0 0 {name=l2 sig_type=std_logic lab=s1} +C {lab_wire.sym} -90 -60 0 0 {name=l3 sig_type=std_logic lab=sel0} +C {lab_wire.sym} -90 60 0 0 {name=l4 sig_type=std_logic lab=sel1} +C {lab_wire.sym} -90 180 0 0 {name=l5 sig_type=std_logic lab=sel2} +C {lab_wire.sym} 140 -380 0 0 {name=l6 sig_type=std_logic lab=sel0} +C {lab_wire.sym} 140 -90 0 0 {name=l7 sig_type=std_logic lab=sel1} +C {lab_wire.sym} 140 210 0 0 {name=l8 sig_type=std_logic lab=sel2} +C {src/inverter/inverter.sym} 110 450 0 0 {name=x7} +C {src/inverter/inverter.sym} 110 170 0 0 {name=x10} +C {src/inverter/inverter.sym} 110 -140 0 0 {name=x11} +C {lab_wire.sym} 50 -140 0 0 {name=l9 sig_type=std_logic lab=sel0} +C {lab_wire.sym} 40 170 0 0 {name=l10 sig_type=std_logic lab=sel1} +C {lab_wire.sym} 40 450 0 0 {name=l11 sig_type=std_logic lab=sel2} +C {lab_wire.sym} -470 -110 0 0 {name=l12 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -250 -100 0 0 {name=l13 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -470 50 0 0 {name=l14 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -250 20 0 0 {name=l15 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -250 140 0 0 {name=l16 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 90 -170 0 0 {name=l17 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 90 140 0 0 {name=l18 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 90 420 0 0 {name=l19 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -250 -10 0 0 {name=l20 sig_type=std_logic lab=vss} +C {lab_wire.sym} -470 -40 0 1 {name=l21 sig_type=std_logic lab=vss} +C {lab_wire.sym} -470 120 0 1 {name=l22 sig_type=std_logic lab=vss} +C {lab_wire.sym} -250 230 0 1 {name=l23 sig_type=std_logic lab=vss} +C {lab_wire.sym} 90 -110 0 1 {name=l24 sig_type=std_logic lab=vss} +C {lab_wire.sym} 90 490 0 1 {name=l26 sig_type=std_logic lab=vss} +C {sky130_fd_pr/nfet_01v8.sym} 140 -190 3 0 {name=M1 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 140 -340 1 0 {name=M2 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {ipin.sym} 30 -260 0 0 {name=p1 lab=vin0} +C {opin.sym} 270 -250 0 0 {name=p2 lab=vout0} +C {sky130_fd_pr/nfet_01v8.sym} 140 100 3 0 {name=M3 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 140 -50 1 0 {name=M4 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {ipin.sym} 30 30 0 0 {name=p3 lab=vin1} +C {opin.sym} 270 40 0 0 {name=p4 lab=vout1} +C {sky130_fd_pr/nfet_01v8.sym} 140 390 3 0 {name=M5 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 140 240 1 0 {name=M6 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {ipin.sym} 30 320 0 0 {name=p5 lab=vin2} +C {opin.sym} 270 330 0 0 {name=p6 lab=vout2} +C {iopin.sym} -380 -280 0 0 {name=p7 lab=vdd} +C {iopin.sym} -380 -200 0 0 {name=p8 lab=vss} +C {lab_wire.sym} -300 -280 0 0 {name=l25 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -300 -200 0 0 {name=l27 sig_type=std_logic lab=vss} +C {ipin.sym} -570 -70 0 0 {name=p9 lab=s0} +C {ipin.sym} -570 80 0 0 {name=p10 lab=s1}
diff --git a/xschem/src/output_select/out_select.sym b/xschem/src/output_select/out_select.sym new file mode 100644 index 0000000..9d7da7d --- /dev/null +++ b/xschem/src/output_select/out_select.sym
@@ -0,0 +1,43 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -50 130 -50 {} +L 4 -130 50 130 50 {} +L 4 -130 -50 -130 50 {} +L 4 130 -50 130 50 {} +L 4 -150 0 -130 0 {} +L 4 130 -20 150 -20 {} +L 4 -150 -40 -130 -40 {} +L 4 -150 20 -130 20 {} +L 4 130 0 150 0 {} +L 4 -150 -20 -130 -20 {} +L 4 -150 40 -130 40 {} +L 4 130 20 150 20 {} +B 5 -2.5 -52.5 2.5 -47.5 {name=vdd dir=inout } +B 5 -152.5 -2.5 -147.5 2.5 {name=vin0 dir=in } +B 5 147.5 -22.5 152.5 -17.5 {name=vout0 dir=out } +B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout } +B 5 -152.5 -42.5 -147.5 -37.5 {name=s0 dir=in } +B 5 -152.5 17.5 -147.5 22.5 {name=vin1 dir=in } +B 5 147.5 -2.5 152.5 2.5 {name=vout1 dir=out } +B 5 -152.5 -22.5 -147.5 -17.5 {name=s1 dir=in } +B 5 -152.5 37.5 -147.5 42.5 {name=vin2 dir=in } +B 5 147.5 17.5 152.5 22.5 {name=vout2 dir=out } +T {@symname} -63 -6 0 0 0.3 0.3 {} +T {@name} 135 -62 0 0 0.2 0.2 {} +T {vdd} 5 -44 0 1 0.2 0.2 {} +T {vin0} -125 -4 0 0 0.2 0.2 {} +T {vout0} 125 -24 0 1 0.2 0.2 {} +T {vss} 5 36 0 1 0.2 0.2 {} +T {s0} -125 -44 0 0 0.2 0.2 {} +T {vin1} -125 16 0 0 0.2 0.2 {} +T {vout1} 125 -4 0 1 0.2 0.2 {} +T {s1} -125 -24 0 0 0.2 0.2 {} +T {vin2} -125 36 0 0 0.2 0.2 {} +T {vout2} 125 16 0 1 0.2 0.2 {}
diff --git a/xschem/src/output_select/out_select_tb.sch b/xschem/src/output_select/out_select_tb.sch new file mode 100644 index 0000000..52ba249 --- /dev/null +++ b/xschem/src/output_select/out_select_tb.sch
@@ -0,0 +1,271 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -410 -230 -200 -80 { lab=#net1} +N -410 -140 -200 -60 { lab=#net2} +N -410 -50 -200 -40 { lab=vin0} +N -410 40 -200 -20 { lab=vin1} +N -410 140 -200 0 { lab=vin2} +N 240 -220 240 -190 { lab=vdd} +N 240 -130 240 -100 { lab=GND} +N -50 -120 -50 -90 { lab=vdd} +N 100 -60 130 -60 { lab=vout0} +N 100 -40 130 -40 { lab=vout1} +N 100 -20 130 -20 { lab=vout2} +N 330 60 330 80 { lab=vref} +N 330 60 330 80 { lab=vref} +N 330 140 330 160 { lab=GND} +N 390 280 390 360 { lab=v1} +N 390 310 460 310 { lab=v1} +N 390 200 390 220 { lab=vdd} +N 390 420 390 430 { lab=GND} +N 390 390 390 420 { lab=GND} +N 430 390 470 390 { lab=v1} +N 460 310 460 390 { lab=v1} +N 470 390 510 390 { lab=v1} +N 540 430 570 430 { lab=GND} +N 560 430 560 460 { lab=GND} +N 510 430 540 430 { lab=GND} +N 570 430 600 430 { lab=GND} +N 480 430 480 480 { lab=vbias1} +N 630 430 630 480 { lab=vbias2} +N 510 390 600 390 { lab=v1} +N 600 390 800 390 { lab=v1} +N 670 430 670 480 { lab=vbias3} +N 700 430 730 430 { lab=GND} +N 730 430 800 430 { lab=GND} +N 750 430 750 460 { lab=GND} +N 830 430 830 480 { lab=vbias4} +N 480 480 480 520 { lab=vbias1} +N 630 480 630 520 { lab=vbias2} +N 670 480 670 520 { lab=vbias3} +N 830 480 830 520 { lab=vbias4} +N 830 580 830 600 { lab=GND} +N 670 580 670 600 { lab=GND} +N 630 580 630 600 { lab=GND} +N 480 580 480 600 { lab=GND} +N -580 90 -580 120 { lab=vdd} +N -580 200 -580 230 { lab=GND} +N -670 140 -640 140 { lab=vbias1} +N -670 160 -640 160 { lab=vbias2} +N -670 180 -640 180 { lab=vref} +N -510 150 -420 150 { lab=vin2} +N -420 150 -410 140 { lab=vin2} +N 130 -20 170 -20 { lab=vout2} +N 450 -20 510 -20 { lab=vtest} +N 510 40 510 60 { lab=GND} +N 210 -20 210 10 { lab=vtest} +N 210 100 210 130 { lab=GND} +N 210 10 210 70 { lab=vtest} +N 120 100 170 100 { lab=v1} +N 210 130 210 150 { lab=GND} +N 310 -20 450 -20 { lab=vtest} +N 310 -20 310 40 { lab=vtest} +N 210 40 310 40 { lab=vtest} +N 210 -70 210 -50 { lab=vdd} +N 460 40 460 60 { lab=GND} +C {src/output_select/out_select.sym} -50 -40 0 0 {name=x1} +C {netlist_not_shown.sym} -210 -400 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/Class_D/Class_D_post.spice + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {vsource.sym} 240 -160 0 0 {name=V1 value=1.8} +C {vsource.sym} -410 -200 0 0 {name=V2 value=1.8} +C {vsource.sym} -410 -110 0 0 {name=V3 value=1.8} +C {vsource.sym} -410 -20 0 0 {name=V4 value=1.8} +C {vsource.sym} -410 70 0 0 {name=V5 value=1.8} +C {gnd.sym} -410 -170 0 0 {name=l1 lab=GND} +C {gnd.sym} -410 -80 0 0 {name=l2 lab=GND} +C {gnd.sym} -410 10 0 0 {name=l3 lab=GND} +C {gnd.sym} -410 100 0 0 {name=l4 lab=GND} +C {lab_wire.sym} 240 -210 0 0 {name=l6 sig_type=std_logic lab=vdd} +C {gnd.sym} 240 -100 0 0 {name=l7 lab=GND} +C {lab_wire.sym} -50 -100 0 0 {name=l8 sig_type=std_logic lab=vdd} +C {gnd.sym} -50 10 0 0 {name=l9 lab=GND} +C {lab_wire.sym} 130 -60 0 0 {name=l10 sig_type=std_logic lab=vout0} +C {lab_wire.sym} 130 -40 0 0 {name=l11 sig_type=std_logic lab=vout1} +C {lab_wire.sym} 130 -20 0 0 {name=l12 sig_type=std_logic lab=vout2} +C {code_shown.sym} 110 -340 0 0 {name=s1 only_toplevel=false value=" +.control +save all +tran 1n 100u + +.endc + + +"} +C {lab_wire.sym} -410 140 0 0 {name=l13 sig_type=std_logic lab=vin2} +C {lab_wire.sym} -410 40 0 0 {name=l14 sig_type=std_logic lab=vin1} +C {lab_wire.sym} -410 -50 0 0 {name=l15 sig_type=std_logic lab=vin0} +C {vsource.sym} 330 110 0 0 {name=V7 value=0.9} +C {lab_wire.sym} 330 60 0 0 {name=l16 sig_type=std_logic lab=vref} +C {gnd.sym} 330 160 0 0 {name=l17 lab=GND} +C {isource.sym} 390 250 0 0 {name=I2 value=15u} +C {lab_wire.sym} 390 200 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} 390 430 0 0 {name=l18 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 410 390 0 1 {name=M5 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 510 410 3 1 {name=M6 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} 440 310 0 1 {name=l62 sig_type=std_logic lab=v1} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 600 410 1 0 {name=M7 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} 560 460 0 0 {name=l54 lab=GND} +C {lab_wire.sym} 480 470 0 0 {name=l39 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 630 480 0 0 {name=l66 sig_type=std_logic lab=vbias2} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 700 410 3 1 {name=M1 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 800 410 1 0 {name=M2 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} 750 460 0 0 {name=l19 lab=GND} +C {lab_wire.sym} 670 480 0 1 {name=l20 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 830 480 0 1 {name=l21 sig_type=std_logic lab=vbias4} +C {capa.sym} 480 550 0 0 {name=C1 +m=1 +value=1u +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 630 550 0 0 {name=C2 +m=1 +value=1u +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 670 550 0 0 {name=C3 +m=1 +value=1u +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 830 550 0 0 {name=C4 +m=1 +value=1u +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 480 600 0 0 {name=l26 lab=GND} +C {gnd.sym} 630 600 0 0 {name=l27 lab=GND} +C {gnd.sym} 670 600 0 0 {name=l28 lab=GND} +C {gnd.sym} 830 600 0 0 {name=l29 lab=GND} +C {lab_wire.sym} -660 140 0 0 {name=l22 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} -660 160 0 0 {name=l23 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} -660 180 0 0 {name=l24 sig_type=std_logic lab=vref} +C {gnd.sym} -580 230 0 0 {name=l25 lab=GND} +C {lab_wire.sym} -580 100 0 0 {name=l30 sig_type=std_logic lab=vdd} +C {src/triangle/triangle.sym} -580 160 0 0 {name=x2} +C {capa.sym} 510 10 0 0 {name=C5 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 510 60 0 0 {name=l31 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 190 -20 0 0 {name=M4 +L=2 +W=4 +nf=2 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 190 100 0 0 {name=M3 +L=2 +W=4 +nf=2 +mult=16 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} 130 100 0 1 {name=l32 sig_type=std_logic lab=v1} +C {gnd.sym} 210 150 0 0 {name=l33 lab=GND} +C {lab_wire.sym} 210 -60 0 0 {name=l34 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 370 -20 0 0 {name=l35 sig_type=std_logic lab=vtest} +C {res.sym} 460 10 0 0 {name=R1 +value=1MEG +footprint=1206 +device=resistor +m=1} +C {gnd.sym} 460 60 0 0 {name=l5 lab=GND}
diff --git a/xschem/src/output_select/transmission_gate.sch b/xschem/src/output_select/transmission_gate.sch new file mode 100644 index 0000000..8d35478 --- /dev/null +++ b/xschem/src/output_select/transmission_gate.sch
@@ -0,0 +1,50 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -500 -210 -480 -210 { lab=vin} +N -500 -210 -500 -100 { lab=vin} +N -500 -100 -480 -100 { lab=vin} +N -420 -210 -400 -210 { lab=vout} +N -400 -210 -400 -100 { lab=vout} +N -420 -100 -400 -100 { lab=vout} +N -560 -150 -500 -150 { lab=vin} +N -400 -140 -320 -140 { lab=vout} +N -450 -280 -450 -250 { lab=ena_n} +N -450 -60 -450 -20 { lab=ena} +N -450 -210 -420 -210 { lab=vout} +N -450 -100 -420 -100 { lab=vout} +C {sky130_fd_pr/nfet_01v8.sym} -450 -80 3 0 {name=M1 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} -450 -230 1 0 {name=M2 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {ipin.sym} -560 -150 0 0 {name=p1 lab=vin} +C {opin.sym} -320 -140 0 0 {name=p2 lab=vout} +C {ipin.sym} -450 -280 1 0 {name=p3 lab=ena_n} +C {ipin.sym} -450 -20 3 0 {name=p4 lab=ena}
diff --git a/xschem/src/output_select/transmission_gate.sym b/xschem/src/output_select/transmission_gate.sym new file mode 100644 index 0000000..0402361 --- /dev/null +++ b/xschem/src/output_select/transmission_gate.sym
@@ -0,0 +1,25 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -80 -30 -80 30 {} +L 4 180 -30 180 30 {} +L 4 -80 -30 80 -30 {} +L 4 -80 30 80 30 {} +L 4 80 -30 180 -30 {} +L 4 80 30 180 30 {} +B 5 57.5 -32.5 62.5 -27.5 {name=ena_n dir=in } +B 5 -82.5 -2.5 -77.5 2.5 {name=vin dir=in } +B 5 177.5 -2.5 182.5 2.5 {name=vout dir=out } +B 5 57.5 27.5 62.5 32.5 {name=ena dir=in } +T {@symname} -36.5 -6 0 0 0.3 0.3 {} +T {@name} 235 -42 0 0 0.2 0.2 {} +T {ena_n} 45 -24 0 0 0.2 0.2 {} +T {vin} -75 -4 0 0 0.2 0.2 {} +T {vout} 225 -4 0 1 0.2 0.2 {} +T {ena} 45 16 0 0 0.2 0.2 {}
diff --git a/xschem/src/rctest.sch b/xschem/src/rctest.sch new file mode 100644 index 0000000..d927e83 --- /dev/null +++ b/xschem/src/rctest.sch
@@ -0,0 +1,44 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 250 -90 380 -90 { lab=r} +N 250 -30 380 -30 { lab=GND} +N 360 -60 360 -30 { lab=GND} +C {netlist_not_shown.sym} 0 -90 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/test/r_test.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + + +"} +C {gnd.sym} 310 -30 0 0 {name=l1 lab=GND} +C {lab_wire.sym} 320 -90 0 0 {name=l2 sig_type=std_logic lab=r} +C {code_shown.sym} 520 -120 0 0 {name=s1 only_toplevel=false value=" +* NGSPICE file created from r_test.ext - technology: sky130A + + +.control +save all +op +print 3/i(v1) +.endc + +"} +C {vsource.sym} 250 -60 0 0 {name=V1 value=3} +C {sky130_fd_pr/res_xhigh_po.sym} 380 -60 0 0 {name=R2 +W=0.35 +L=28 +model=res_xhigh_po +spiceprefix=X +mult=1}
diff --git a/xschem/src/ring_osc/ring_osc.sym b/xschem/src/ring_osc/ring_osc.sym new file mode 100644 index 0000000..66cf5fb --- /dev/null +++ b/xschem/src/ring_osc/ring_osc.sym
@@ -0,0 +1,19 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -40 -40 -40 20 {} +L 4 90 -40 90 20 {} +L 4 -40 -40 90 -40 {} +L 4 -40 20 90 20 {} +L 4 -60 -10 -40 -10 {} +B 5 37.5 -42.5 42.5 -37.5 {name=vdd dir=inout } +B 5 -62.5 -12.5 -57.5 -7.5 {name=stimuli dir=inout } +B 5 37.5 17.5 42.5 22.5 {name=gnd dir=inout } +T {ring_osc} 16 -16 0 0 0.3 0.3 {} +T {stimuli} 5 -14 0 1 0.2 0.2 {}
diff --git a/xschem/src/ring_osc/ring_osc_flat.sym b/xschem/src/ring_osc/ring_osc_flat.sym new file mode 100644 index 0000000..108a716 --- /dev/null +++ b/xschem/src/ring_osc/ring_osc_flat.sym
@@ -0,0 +1,19 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -50 -50 -50 10 {} +L 4 80 -50 80 10 {} +L 4 -50 -50 80 -50 {} +L 4 -50 10 80 10 {} +L 4 -70 -20 -50 -20 {} +B 5 27.5 -52.5 32.5 -47.5 {name=vdd dir=inout } +B 5 -72.5 -22.5 -67.5 -17.5 {name=stimuli dir=inout } +B 5 27.5 7.5 32.5 12.5 {name=gnd dir=inout } +T {ring_osc} 6 -26 0 0 0.3 0.3 {} +T {stimuli} -5 -24 0 1 0.2 0.2 {}
diff --git a/xschem/src/ring_osc/ring_osc_tb.sch b/xschem/src/ring_osc/ring_osc_tb.sch new file mode 100644 index 0000000..4fe0867 --- /dev/null +++ b/xschem/src/ring_osc/ring_osc_tb.sch
@@ -0,0 +1,72 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 460 -10 590 -10 { lab=#net1} +N 460 -10 460 20 { lab=#net1} +N 460 80 460 100 { lab=GND} +N 460 90 590 90 { lab=GND} +N 590 50 590 90 { lab=GND} +N 300 50 360 50 { lab=out} +N 300 110 300 130 { lab=GND} +C {netlist_not_shown.sym} 20 -100 0 0 {name=s1 only_toplevel=false value=" +.include /home/eda/magic/ring_osc/ring_osc_flat.spice + +"} +C {netlist_not_shown.sym} 150 -100 0 0 {name=TT_MODELS +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_03v3_nvt/sky130_fd_pr__nfet_03v3_nvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_nfet_01v8/sky130_fd_pr__esd_nfet_01v8__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_pfet_g5v0d10v5/sky130_fd_pr__esd_pfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d16v0/sky130_fd_pr__pfet_g5v0d16v0__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d10v5/sky130_fd_pr__nfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d16v0/sky130_fd_pr__nfet_g5v0d16v0__tt_discrete.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/esd_nfet_g5v0d10v5/sky130_fd_pr__esd_nfet_g5v0d10v5__tt.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/nonfet.spice +* Mismatch parameters +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_g5v0d10v5/sky130_fd_pr__nfet_g5v0d10v5__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__mismatch.corner.spice +.include \\\\$::SKYWATER_MODELS\\\\/cells/nfet_03v3_nvt/sky130_fd_pr__nfet_03v3_nvt__mismatch.corner.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice +* All models +.include \\\\$::SKYWATER_MODELS\\\\/models/all.spice +* Corner +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/rf.spice +" +} +C {vsource.sym} 590 20 0 0 {name=V1 value=1.8} +C {gnd.sym} 460 100 0 0 {name=l1 lab=GND} +C {gnd.sym} 300 130 0 0 {name=l2 lab=GND} +C {code_shown.sym} 30 70 0 0 {name=s2 only_toplevel=false value=" +.option RSHUNT=1e20 +.control +save all +tran 0.005n 500n +write ring_osc.raw +.endc +"} +C {lab_wire.sym} 340 50 0 0 {name=l3 sig_type=std_logic lab=out} +C {isource.sym} 300 80 0 0 {name=I0 value="pulse(0 1m 1n 1n 1n 1n 1)"} +C {src/ring_osc/ring_osc_flat.sym} 430 70 0 0 {name=x1}
diff --git a/xschem/src/ring_osc/ring_osc_xschem.sch b/xschem/src/ring_osc/ring_osc_xschem.sch new file mode 100644 index 0000000..f510ac5 --- /dev/null +++ b/xschem/src/ring_osc/ring_osc_xschem.sch
@@ -0,0 +1,36 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 190 -70 190 -50 { lab=vdd} +N 560 30 560 180 { lab=stimuli} +N 120 180 560 180 { lab=stimuli} +N 120 10 120 180 { lab=stimuli} +N 120 10 150 10 { lab=stimuli} +N 190 -90 190 -70 { lab=vdd} +N 560 30 580 30 { lab=stimuli} +N 290 130 290 150 { lab=gnd} +N 230 10 270 10 { lab=out1} +N 350 10 380 10 { lab=out2} +N 460 10 560 10 { lab=stimuli} +N 560 10 560 30 { lab=stimuli} +N 290 70 290 130 { lab=gnd} +N 180 30 180 70 { lab=gnd} +N 410 30 410 70 { lab=gnd} +N 300 30 300 70 { lab=gnd} +N 180 70 410 70 { lab=gnd} +N 180 -50 180 -10 { lab=vdd} +N 300 -50 300 -10 { lab=vdd} +N 410 -50 410 -10 { lab=vdd} +N 350 -50 410 -50 { lab=vdd} +N 180 -50 350 -50 { lab=vdd} +C {iopin.sym} 190 -90 0 0 {name=p1 lab=vdd} +C {iopin.sym} 580 30 0 0 {name=p2 lab=stimuli} +C {iopin.sym} 290 150 0 0 {name=p3 lab=gnd} +C {src/inverter/inverter.sym} 200 10 0 0 {name=x1} +C {src/inverter/inverter.sym} 320 10 0 0 {name=x2} +C {src/inverter/inverter.sym} 430 10 0 0 {name=x3} +C {lab_wire.sym} 250 10 0 0 {name=l1 sig_type=std_logic lab=out1} +C {lab_wire.sym} 370 10 0 0 {name=l2 sig_type=std_logic lab=out2}
diff --git a/xschem/src/ring_osc/ring_osc_xschem.sym b/xschem/src/ring_osc/ring_osc_xschem.sym new file mode 100644 index 0000000..8b79f13 --- /dev/null +++ b/xschem/src/ring_osc/ring_osc_xschem.sym
@@ -0,0 +1,19 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -40 -30 -40 30 {} +L 4 90 -30 90 30 {} +L 4 -40 -30 90 -30 {} +L 4 -40 30 90 30 {} +L 4 -60 -0 -40 -0 {} +B 5 37.5 -32.5 42.5 -27.5 {name=vdd dir=inout } +B 5 -62.5 -2.5 -57.5 2.5 {name=stimuli dir=inout } +B 5 37.5 27.5 42.5 32.5 {name=gnd dir=inout } +T {ring_osc} 16 -6 0 0 0.3 0.3 {} +T {stimuli} 5 -4 0 1 0.2 0.2 {}
diff --git a/xschem/src/triangle/triangle.sch b/xschem/src/triangle/triangle.sch new file mode 100644 index 0000000..aa14c6a --- /dev/null +++ b/xschem/src/triangle/triangle.sch
@@ -0,0 +1,98 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 460 20 480 20 { lab=vcmp} +N 460 -60 460 20 { lab=vcmp} +N 450 -60 520 -60 { lab=vcmp} +N 260 130 330 130 { lab=vt} +N 330 40 330 130 { lab=vt} +N 140 130 200 130 { lab=vi} +N 140 40 140 130 { lab=vi} +N 110 40 190 40 { lab=vi} +N 20 40 50 40 { lab=vsquare} +N 20 40 20 190 { lab=vsquare} +N 20 190 570 190 { lab=vsquare} +N 630 40 630 190 { lab=vsquare} +N 590 40 630 40 { lab=vsquare} +N 580 -60 630 -60 { lab=vsquare} +N 630 -60 630 40 { lab=vsquare} +N 540 0 540 20 { lab=vdd} +N 250 -10 250 20 { lab=vdd} +N 540 -10 540 0 { lab=vdd} +N 250 60 250 80 { lab=vss} +N 250 80 280 80 { lab=vss} +N 540 60 540 80 { lab=vss} +N 540 80 570 80 { lab=vss} +N 160 60 190 60 { lab=vbias1} +N 450 60 480 60 { lab=vbias2} +N 170 20 190 20 { lab=vref} +N 450 40 480 40 { lab=vref} +N 160 20 170 20 { lab=vref} +N -90 0 -40 0 { lab=vdd} +N -90 40 -40 40 { lab=vbias1} +N -90 70 -40 70 { lab=vref} +N 250 -60 330 -60 { lab=vt} +N 630 0 660 0 { lab=vsquare} +N -90 130 -50 130 { lab=vss} +N 50 60 80 60 { lab=vss} +N 420 -40 450 -40 { lab=vss} +N 550 -40 590 -40 { lab=vss} +N -90 100 -40 100 { lab=vbias2} +N 300 40 330 40 { lab=vt} +N 360 -60 390 -60 { lab=vt} +N 330 -60 360 -60 { lab=vt} +N 330 20 330 40 { lab=vt} +N 330 -60 330 -40 { lab=vt} +N 330 -40 330 20 { lab=vt} +N 570 190 630 190 { lab=vsquare} +C {lab_wire.sym} 250 -10 2 1 {name=l2 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 540 -10 2 1 {name=l3 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 180 60 2 1 {name=l15 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 470 60 2 1 {name=l16 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 180 20 0 0 {name=l17 sig_type=std_logic lab=vref} +C {lab_wire.sym} 470 40 0 0 {name=l18 sig_type=std_logic lab=vref} +C {lab_wire.sym} 330 80 2 1 {name=l19 sig_type=std_logic lab=vt} +C {lab_wire.sym} 540 190 2 1 {name=l20 sig_type=std_logic lab=vsquare} +C {lab_wire.sym} 510 -60 2 1 {name=l21 sig_type=std_logic lab=vcmp} +C {lab_wire.sym} 160 130 2 1 {name=l1 sig_type=std_logic lab=vi} +C {sky130_fd_pr/res_xhigh_po_0p35.sym} 80 40 1 1 {name=R3 +W=0.35 +L=32 +model=res_xhigh_po +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_xhigh_po_0p35.sym} 420 -60 1 1 {name=R1 +W=0.35 +L=4 +model=res_xhigh_po +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_xhigh_po_0p35.sym} 550 -60 1 1 {name=R2 +W=0.35 +L=9 +model=res_xhigh_po +spiceprefix=X +mult=1} +C {iopin.sym} -80 0 0 1 {name=p1 lab=vdd} +C {ipin.sym} -80 40 0 0 {name=p2 lab=vbias1} +C {opin.sym} 260 -60 2 0 {name=p3 lab=vt} +C {lab_wire.sym} -70 0 0 1 {name=l4 sig_type=std_logic lab=vdd} +C {lab_wire.sym} -40 40 0 0 {name=l5 sig_type=std_logic lab=vbias1} +C {ipin.sym} -80 70 0 0 {name=p4 lab=vref} +C {lab_wire.sym} -40 70 0 0 {name=l6 sig_type=std_logic lab=vref} +C {opin.sym} 650 0 2 1 {name=p5 lab=vsquare} +C {iopin.sym} -80 130 0 1 {name=p6 lab=vss} +C {lab_wire.sym} -70 130 0 1 {name=l7 sig_type=std_logic lab=vss} +C {lab_wire.sym} 60 60 0 0 {name=l8 sig_type=std_logic lab=vss} +C {lab_wire.sym} 280 80 0 0 {name=l9 sig_type=std_logic lab=vss} +C {lab_wire.sym} 570 80 0 0 {name=l10 sig_type=std_logic lab=vss} +C {lab_wire.sym} 580 -40 0 1 {name=l11 sig_type=std_logic lab=vss} +C {lab_wire.sym} 430 -40 0 1 {name=l12 sig_type=std_logic lab=vss} +C {ipin.sym} -80 100 0 0 {name=p7 lab=vbias2} +C {lab_wire.sym} -70 100 0 1 {name=l13 sig_type=std_logic lab=vbias2} +C {src/OTA_tri/OTA_tri.sym} 270 70 0 0 {name=x1} +C {src/OTA/OTA.sym} 570 -60 0 0 {name=x2} +C {sky130_fd_pr/cap_mim_m3_1.sym} 230 130 3 0 {name=C1 model=cap_mim_m3_1 W=15 L=15 MF=8 spiceprefix=X}
diff --git a/xschem/src/triangle/triangle.sym b/xschem/src/triangle/triangle.sym new file mode 100644 index 0000000..784286e --- /dev/null +++ b/xschem/src/triangle/triangle.sym
@@ -0,0 +1,35 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -60 -40 -60 40 {} +L 4 70 -40 70 40 {} +L 4 -60 -40 50 -40 {} +L 4 -60 40 50 40 {} +L 4 -10 10 0 -10 {} +L 4 0 -10 10 10 {} +L 4 10 10 20 -10 {} +L 4 20 -10 30 10 {} +L 4 -20 -10 -10 10 {} +L 4 50 -40 70 -40 {} +L 4 50 40 70 40 {} +B 5 -2.5 -42.5 2.5 -37.5 {name=vdd dir=inout } +B 5 -62.5 -22.5 -57.5 -17.5 {name=vbias1 dir=in } +B 5 -62.5 -2.5 -57.5 2.5 {name=vbias2 dir=in } +B 5 -62.5 17.5 -57.5 22.5 {name=vref dir=in } +B 5 -2.5 37.5 2.5 42.5 {name=vss dir=inout } +B 5 67.5 17.5 72.5 22.5 {name=vsquare dir=out } +B 5 67.5 -12.5 72.5 -7.5 {name=vt dir=out } +T {@name} 25 -62 0 0 0.2 0.2 {} +T {vdd} 5 -34 0 1 0.2 0.2 {} +T {vbias1} -55 -24 0 0 0.2 0.2 {} +T {vref} -55 16 0 0 0.2 0.2 {} +T {vsquare} 65 16 0 1 0.2 0.2 {} +T {vss} 5 26 0 1 0.2 0.2 {} +T {vt} 65 -14 0 1 0.2 0.2 {} +T {vbias2} -55 -4 0 0 0.2 0.2 {}
diff --git a/xschem/src/triangle/triangle_post.sym b/xschem/src/triangle/triangle_post.sym new file mode 100644 index 0000000..300dec1 --- /dev/null +++ b/xschem/src/triangle/triangle_post.sym
@@ -0,0 +1,35 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -70 -40 -70 40 {} +L 4 60 -40 60 40 {} +L 4 -70 -40 40 -40 {} +L 4 -70 40 40 40 {} +L 4 -20 10 -10 -10 {} +L 4 -10 -10 0 10 {} +L 4 0 10 10 -10 {} +L 4 10 -10 20 10 {} +L 4 -30 -10 -20 10 {} +L 4 40 -40 60 -40 {} +L 4 40 40 60 40 {} +B 5 -12.5 -42.5 -7.5 -37.5 {name=vdd dir=inout } +B 5 -72.5 -22.5 -67.5 -17.5 {name=vbias1 dir=in } +B 5 -72.5 -2.5 -67.5 2.5 {name=vbias2 dir=in } +B 5 -72.5 17.5 -67.5 22.5 {name=vref dir=in } +B 5 -12.5 37.5 -7.5 42.5 {name=vss dir=inout } +B 5 57.5 17.5 62.5 22.5 {name=vsquare dir=out } +B 5 57.5 -12.5 62.5 -7.5 {name=vt dir=out } +T {@name} 15 -62 0 0 0.2 0.2 {} +T {vdd} -5 -34 0 1 0.2 0.2 {} +T {vbias1} -65 -24 0 0 0.2 0.2 {} +T {vref} -65 16 0 0 0.2 0.2 {} +T {vsquare} 55 16 0 1 0.2 0.2 {} +T {vss} -5 26 0 1 0.2 0.2 {} +T {vt} 55 -14 0 1 0.2 0.2 {} +T {vbias2} -65 -4 0 0 0.2 0.2 {}
diff --git a/xschem/src/triangle/triangle_revised_post.sym b/xschem/src/triangle/triangle_revised_post.sym new file mode 100644 index 0000000..fbfdac7 --- /dev/null +++ b/xschem/src/triangle/triangle_revised_post.sym
@@ -0,0 +1,35 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=primitive +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 10 -40 10 40 {} +L 4 140 -40 140 40 {} +L 4 10 -40 120 -40 {} +L 4 10 40 120 40 {} +L 4 60 10 70 -10 {} +L 4 70 -10 80 10 {} +L 4 80 10 90 -10 {} +L 4 90 -10 100 10 {} +L 4 50 -10 60 10 {} +L 4 120 -40 140 -40 {} +L 4 120 40 140 40 {} +B 5 67.5 -42.5 72.5 -37.5 {name=vdd dir=inout } +B 5 7.5 -22.5 12.5 -17.5 {name=vbias1 dir=in } +B 5 7.5 -2.5 12.5 2.5 {name=vbias2 dir=in } +B 5 7.5 17.5 12.5 22.5 {name=vref dir=in } +B 5 67.5 37.5 72.5 42.5 {name=vss dir=inout } +B 5 137.5 17.5 142.5 22.5 {name=vsquare dir=out } +B 5 137.5 -12.5 142.5 -7.5 {name=vt dir=out } +T {@name} 95 -62 0 0 0.2 0.2 {} +T {vdd} 75 -34 0 1 0.2 0.2 {} +T {vbias1} 15 -24 0 0 0.2 0.2 {} +T {vref} 15 16 0 0 0.2 0.2 {} +T {vsquare} 135 16 0 1 0.2 0.2 {} +T {vss} 75 26 0 1 0.2 0.2 {} +T {vt} 135 -14 0 1 0.2 0.2 {} +T {vbias2} 15 -4 0 0 0.2 0.2 {}
diff --git a/xschem/src/triangle/triangle_tb.sch b/xschem/src/triangle/triangle_tb.sch new file mode 100644 index 0000000..5ed8832 --- /dev/null +++ b/xschem/src/triangle/triangle_tb.sch
@@ -0,0 +1,218 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -170 -10 -170 10 { lab=vref} +N -170 -10 -170 10 { lab=vref} +N -170 70 -170 90 { lab=GND} +N -350 70 -350 90 { lab=GND} +N -350 -20 -350 10 { lab=vdd} +N -110 210 -110 290 { lab=v1} +N -110 240 -40 240 { lab=v1} +N -110 130 -110 150 { lab=vdd} +N -110 350 -110 360 { lab=GND} +N -110 320 -110 350 { lab=GND} +N -70 320 -30 320 { lab=v1} +N -40 240 -40 320 { lab=v1} +N -30 320 10 320 { lab=v1} +N 40 360 70 360 { lab=GND} +N 60 360 60 390 { lab=GND} +N 10 360 40 360 { lab=GND} +N 70 360 100 360 { lab=GND} +N -20 360 -20 410 { lab=vbias1} +N 130 360 130 410 { lab=vbias2} +N 10 320 100 320 { lab=v1} +N 100 320 300 320 { lab=v1} +N 170 360 170 410 { lab=vbias3} +N 200 360 230 360 { lab=GND} +N 230 360 300 360 { lab=GND} +N 250 360 250 390 { lab=GND} +N 330 360 330 410 { lab=vbias4} +N -20 410 -20 450 { lab=vbias1} +N 130 410 130 450 { lab=vbias2} +N 170 410 170 450 { lab=vbias3} +N 330 410 330 450 { lab=vbias4} +N 330 510 330 530 { lab=GND} +N 170 510 170 530 { lab=GND} +N 130 510 130 530 { lab=GND} +N -20 510 -20 530 { lab=GND} +N 330 -20 330 10 { lab=vdd} +N 330 90 330 120 { lab=GND} +N 240 30 270 30 { lab=vbias1} +N 240 50 270 50 { lab=vbias2} +N 240 70 270 70 { lab=vref} +N 400 40 470 40 { lab=vt} +N 470 -10 470 40 { lab=vt} +N 470 -10 490 -10 { lab=vt} +N 470 40 470 130 { lab=vt} +N 470 130 490 130 { lab=vt} +N 460 10 490 10 { lab=vbias3} +N 460 150 490 150 { lab=vbias4} +N 450 110 490 110 { lab=vref} +N 460 -30 490 -30 { lab=vref} +N 550 -60 550 -30 { lab=vdd} +N 550 10 550 40 { lab=GND} +N 550 70 550 110 { lab=vdd} +N 550 150 550 190 { lab=GND} +C {vsource.sym} -170 40 0 0 {name=V1 value=0.9} +C {vsource.sym} -350 40 0 0 {name=V2 value=1.8} +C {lab_wire.sym} -170 -10 0 0 {name=l4 sig_type=std_logic lab=vref} +C {netlist_not_shown.sym} 110 -270 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_tri_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice +.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_revised_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_revised_post.spice +.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_tri_revised_post.spice +.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_revised_post.spice +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {code_shown.sym} -250 -290 0 0 {name=s1 only_toplevel=false value=" +.nodeset v(vt)=0.9 v(vsquare)=0.9 +.control +save all +op + +tran 1n 50u +*dc V3 0 1.8 0.01 +*write tri.raw + +.endc +"} +C {gnd.sym} -170 90 0 0 {name=l6 lab=GND} +C {gnd.sym} -350 90 0 0 {name=l5 lab=GND} +C {lab_wire.sym} -350 -10 0 0 {name=l8 sig_type=std_logic lab=vdd} +C {isource.sym} -110 180 0 0 {name=I2 value=15u} +C {lab_wire.sym} -110 130 0 0 {name=l53 sig_type=std_logic lab=vdd} +C {gnd.sym} -110 360 0 0 {name=l16 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} -90 320 0 1 {name=M5 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 10 340 3 1 {name=M6 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {lab_wire.sym} -60 240 0 1 {name=l62 sig_type=std_logic lab=v1} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 100 340 1 0 {name=M7 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} 60 390 0 0 {name=l54 lab=GND} +C {lab_wire.sym} -20 400 0 0 {name=l39 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 130 410 0 0 {name=l66 sig_type=std_logic lab=vbias2} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 200 340 3 1 {name=M1 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 300 340 1 0 {name=M2 +L=2 +W=4 +nf=2 +mult=8 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} +C {gnd.sym} 250 390 0 0 {name=l17 lab=GND} +C {lab_wire.sym} 170 410 0 1 {name=l18 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 330 410 0 1 {name=l19 sig_type=std_logic lab=vbias4} +C {capa.sym} -20 480 0 0 {name=C1 +m=1 +value=1u +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 130 480 0 0 {name=C2 +m=1 +value=1u +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 170 480 0 0 {name=C3 +m=1 +value=1u +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} 330 480 0 0 {name=C4 +m=1 +value=1u +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} -20 530 0 0 {name=l26 lab=GND} +C {gnd.sym} 130 530 0 0 {name=l27 lab=GND} +C {gnd.sym} 170 530 0 0 {name=l28 lab=GND} +C {gnd.sym} 330 530 0 0 {name=l29 lab=GND} +C {lab_wire.sym} 250 30 0 0 {name=l1 sig_type=std_logic lab=vbias1} +C {lab_wire.sym} 250 50 0 0 {name=l2 sig_type=std_logic lab=vbias2} +C {lab_wire.sym} 250 70 0 0 {name=l3 sig_type=std_logic lab=vref} +C {gnd.sym} 330 120 0 0 {name=l7 lab=GND} +C {lab_wire.sym} 330 -10 0 0 {name=l9 sig_type=std_logic lab=vdd} +C {src/comparator/comparator.sym} 580 30 0 0 {name=x2} +C {src/comparator/comparator.sym} 580 170 0 0 {name=x3} +C {lab_wire.sym} 460 10 0 0 {name=l10 sig_type=std_logic lab=vbias3} +C {lab_wire.sym} 460 150 0 0 {name=l11 sig_type=std_logic lab=vbias4} +C {lab_wire.sym} 470 -30 0 0 {name=l12 sig_type=std_logic lab=vref} +C {lab_wire.sym} 460 110 0 0 {name=l13 sig_type=std_logic lab=vref} +C {gnd.sym} 550 190 0 0 {name=l14 lab=GND} +C {gnd.sym} 550 40 0 0 {name=l15 lab=GND} +C {lab_wire.sym} 550 90 0 0 {name=l20 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 550 -50 0 0 {name=l21 sig_type=std_logic lab=vdd} +C {lab_wire.sym} 450 40 0 0 {name=l22 sig_type=std_logic lab=vt} +C {src/triangle/triangle_revised_post.sym} 260 50 0 0 {name=x1}
diff --git a/xschem/src/user_analog_project_wrapper/user_analog_project_wrapper.sch b/xschem/src/user_analog_project_wrapper/user_analog_project_wrapper.sch new file mode 100644 index 0000000..33c6c09 --- /dev/null +++ b/xschem/src/user_analog_project_wrapper/user_analog_project_wrapper.sch
@@ -0,0 +1,193 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 4300 190 4370 190 { lab=io_analog[2]} +N 4300 260 4370 260 { lab=io_analog[3]} +N 4300 320 4370 320 { lab=io_analog[4]} +N 4360 -410 4430 -410 { lab=io_analog[6]} +N 4360 -350 4430 -350 { lab=io_analog[7]} +N 4360 -290 4430 -290 { lab=io_analog[8]} +N 4800 -330 4830 -330 { lab=vccd2} +N 4800 -360 4830 -360 { lab=vccd1} +N 4800 -270 4830 -270 { lab=vssd2} +N 4800 -300 4830 -300 { lab=vssd1} +N 4800 -420 4830 -420 { lab=vssa1} +N 4430 70 4510 70 { lab=io_analog[5]} +N 4510 70 4640 70 { lab=io_analog[5]} +N 4640 -360 4640 70 { lab=io_analog[5]} +N 4640 -360 4740 -360 { lab=io_analog[5]} +N 4640 -330 4740 -330 { lab=io_analog[5]} +N 4610 -420 4740 -420 { lab=vssa2} +N 4610 -270 4740 -270 { lab=vssa2} +N 4610 -300 4740 -300 { lab=vssa2} +N 4610 -390 4830 -390 { lab=vssa2} +N 4610 -420 4610 -210 { lab=vssa2} +N 4610 -210 4610 -10 { lab=vssa2} +N 4430 -10 4610 -10 { lab=vssa2} +N 4430 -150 4490 -150 { lab=io_analog[6]} +N 4490 -410 4490 -150 { lab=io_analog[6]} +N 4430 -410 4490 -410 { lab=io_analog[6]} +N 4430 110 4430 320 { lab=io_analog[4]} +N 4370 320 4430 320 { lab=io_analog[4]} +N 4030 -170 4130 -170 { lab=io_analog[10]} +N 4030 -150 4130 -150 { lab=io_analog[1]} +N 4430 30 4520 30 { lab=io_analog[0]} +N 4520 30 4750 30 { lab=io_analog[0]} +N 4430 150 4750 150 { lab=io_analog[4]} +N 4490 -150 4690 -150 { lab=io_analog[6]} +N 3920 -220 4030 -220 { lab=io_analog[10]} +N 4030 -220 4030 -170 { lab=io_analog[10]} +N 3920 -60 4030 -60 { lab=io_analog[1]} +N 4030 -150 4030 -60 { lab=io_analog[1]} +N 4640 -310 4980 -310 { lab=io_analog[5]} +N 4980 -350 4980 -310 { lab=io_analog[5]} +N 4980 -350 5110 -350 { lab=io_analog[5]} +N 5040 -330 5110 -330 { lab=vssa2} +N 5040 -330 5040 -230 { lab=vssa2} +N 4610 -230 5040 -230 { lab=vssa2} +N 4610 -460 5110 -460 { lab=vssa2} +N 4610 -460 4610 -420 { lab=vssa2} +N 4800 -480 4830 -480 { lab=vdda1} +N 4590 -450 4830 -450 { lab=vdda2} +N 4590 -480 4740 -480 { lab=vdda2} +N 4590 -480 4590 -50 { lab=vdda2} +N 4430 -50 4590 -50 { lab=vdda2} +N 4790 -200 4790 -180 { lab=io_analog[5]} +N 4640 -200 4790 -200 { lab=io_analog[5]} +N 4790 -120 4790 -100 { lab=vssa2} +N 4610 -100 4790 -100 { lab=vssa2} +N 4850 -50 4850 -0 { lab=vdda1} +N 4850 -50 5010 -50 { lab=vdda1} +N 5010 -480 5010 -50 { lab=vdda1} +N 4850 60 4850 80 { lab=vssa2} +N 4610 80 4850 80 { lab=vssa2} +N 4610 -10 4610 80 { lab=vssa2} +N 4850 180 4850 220 { lab=vssa2} +N 4610 220 4850 220 { lab=vssa2} +N 4610 80 4610 220 { lab=vssa2} +N 4850 100 4850 120 { lab=io_analog[5]} +N 4560 100 4850 100 { lab=io_analog[5]} +N 4560 70 4560 100 { lab=io_analog[5]} +N 3820 -480 3820 -250 { lab=vdda2} +N 3820 -480 4590 -480 { lab=vdda2} +N 3820 -190 3820 -170 { lab=vssa2} +N 3820 -170 4610 -330 { lab=vssa2} +N 3820 -90 4850 -20 { lab=vdda1} +N 3820 -30 4610 -190 { lab=vssa2} +N 4830 -480 5010 -480 { lab=vdda1} +N 5110 -530 5110 -480 { lab=vdda2} +N 4700 -530 5110 -530 { lab=vdda2} +N 4700 -530 4700 -480 { lab=vdda2} +C {iopin.sym} 4830 -480 0 0 {name=p1 lab=vdda1} +C {iopin.sym} 4830 -450 0 0 {name=p2 lab=vdda2} +C {iopin.sym} 4830 -420 0 0 {name=p3 lab=vssa1} +C {iopin.sym} 4830 -390 0 0 {name=p4 lab=vssa2} +C {iopin.sym} 4830 -360 0 0 {name=p5 lab=vccd1} +C {iopin.sym} 4830 -330 0 0 {name=p6 lab=vccd2} +C {iopin.sym} 4830 -300 0 0 {name=p7 lab=vssd1} +C {iopin.sym} 4830 -270 0 0 {name=p8 lab=vssd2} +C {ipin.sym} 3450 -200 0 0 {name=p9 lab=wb_clk_i} +C {ipin.sym} 3450 -170 0 0 {name=p10 lab=wb_rst_i} +C {ipin.sym} 3450 -140 0 0 {name=p11 lab=wbs_stb_i} +C {ipin.sym} 3450 -110 0 0 {name=p12 lab=wbs_cyc_i} +C {ipin.sym} 3450 -80 0 0 {name=p13 lab=wbs_we_i} +C {ipin.sym} 3450 -50 0 0 {name=p14 lab=wbs_sel_i[3:0]} +C {ipin.sym} 3450 -20 0 0 {name=p15 lab=wbs_dat_i[31:0]} +C {ipin.sym} 3450 10 0 0 {name=p16 lab=wbs_adr_i[31:0]} +C {opin.sym} 3440 70 0 0 {name=p17 lab=wbs_ack_o} +C {opin.sym} 3440 100 0 0 {name=p18 lab=wbs_dat_o[31:0]} +C {ipin.sym} 3450 140 0 0 {name=p19 lab=la_data_in[127:0]} +C {opin.sym} 3440 170 0 0 {name=p20 lab=la_data_out[127:0]} +C {ipin.sym} 3450 250 0 0 {name=p21 lab=io_in[26:0]} +C {ipin.sym} 3450 280 0 0 {name=p22 lab=io_in_3v3[26:0]} +C {ipin.sym} 3440 560 0 0 {name=p23 lab=user_clock2} +C {opin.sym} 3440 310 0 0 {name=p24 lab=io_out[26:0]} +C {opin.sym} 3440 340 0 0 {name=p25 lab=io_oeb[26:0]} +C {iopin.sym} 3410 400 0 0 {name=p26 lab=gpio_analog[17:0]} +C {iopin.sym} 3410 430 0 0 {name=p27 lab=gpio_noesd[17:0]} +C {iopin.sym} 3410 460 0 0 {name=p29 lab=io_analog[10:0]} +C {iopin.sym} 3410 490 0 0 {name=p30 lab=io_clamp_high[2:0]} +C {iopin.sym} 3410 520 0 0 {name=p31 lab=io_clamp_low[2:0]} +C {opin.sym} 3430 590 0 0 {name=p32 lab=user_irq[2:0]} +C {ipin.sym} 3450 200 0 0 {name=p28 lab=la_oenb[127:0]} +C {src/Class_D/Class_D.sym} 4280 -30 0 0 {name=x1} +C {src/ESD/ESD.sym} 3870 -220 0 0 {name=x2} +C {src/ESD/ESD.sym} 3870 -60 0 0 {name=x5} +C {src/ESD/ESD.sym} 4800 150 0 1 {name=x6} +C {src/ESD/io_clamp.sym} 5260 -340 0 1 {name=x9} +C {src/ESD/io_clamp.sym} 5260 -470 0 1 {name=x10} +C {src/ESD/ESD.sym} 4740 -150 0 1 {name=x3} +C {src/ESD/ESD.sym} 4800 30 0 1 {name=x7} +C {lab_wire.sym} 4330 190 0 0 {name=l14 sig_type=std_logic lab=io_analog[2]} +C {lab_wire.sym} 4330 260 0 0 {name=l20 sig_type=std_logic lab=io_analog[3]} +C {lab_wire.sym} 4330 320 0 0 {name=l21 sig_type=std_logic lab=io_analog[4]} +C {lab_wire.sym} 4390 -410 0 0 {name=l22 sig_type=std_logic lab=io_analog[6]} +C {lab_wire.sym} 4390 -350 0 0 {name=l23 sig_type=std_logic lab=io_analog[7]} +C {lab_wire.sym} 4390 -290 0 0 {name=l24 sig_type=std_logic lab=io_analog[8]} +C {sky130_fd_pr/res_generic_m1.sym} 4770 -330 3 1 {name=R1 +W=74.20 +L=18.85 +model=res_generic_m5 +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_generic_m1.sym} 4770 -360 3 1 {name=R2 +W=74.20 +L=17.70 +model=res_generic_m5 +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_generic_m1.sym} 4770 -270 3 1 {name=R3 +W=74.00 +L=20.55 +model=res_generic_m3 +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_generic_m1.sym} 4770 -300 3 1 {name=R4 +W=78.15 +L=17.55 +model=res_generic_m4 +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_generic_m1.sym} 4770 -420 3 1 {name=R5 +W=74.00 +L=16.80 +model=res_generic_m4 +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_generic_m1.sym} 4460 -290 3 1 {name=R6 +W=25.05 +L=6.55 +model=res_generic_m3 +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_generic_m1.sym} 4460 -350 3 1 {name=R7 +W=25.05 +L=7.55 +model=res_generic_m3 +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_generic_m1.sym} 4400 260 3 1 {name=R8 +W=25.05 +L=3.7 +model=res_generic_m3 +spiceprefix=X +mult=1} +C {sky130_fd_pr/res_generic_m1.sym} 4400 190 3 1 {name=R9 +W=25.05 +L=4.15 +model=res_generic_m3 +spiceprefix=X +mult=1} +C {lab_wire.sym} 4470 70 0 1 {name=l1 sig_type=std_logic lab=io_analog[5]} +C {lab_wire.sym} 4070 -170 0 0 {name=l2 sig_type=std_logic lab=io_analog[10]} +C {lab_wire.sym} 4070 -150 0 0 {name=l3 sig_type=std_logic lab=io_analog[1]} +C {lab_wire.sym} 4470 30 0 1 {name=l4 sig_type=std_logic lab=io_analog[0]} +C {sky130_fd_pr/res_generic_m1.sym} 4770 -480 3 1 {name=R10 +W=74.00 +L=10.05 +model=res_generic_m5 +spiceprefix=X +mult=1}
diff --git a/xschem/src/user_analog_project_wrapper/user_analog_project_wrapper.sym b/xschem/src/user_analog_project_wrapper/user_analog_project_wrapper.sym new file mode 100644 index 0000000..a561ba9 --- /dev/null +++ b/xschem/src/user_analog_project_wrapper/user_analog_project_wrapper.sym
@@ -0,0 +1,111 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -190 130 -190 {} +L 4 -130 190 130 190 {} +L 4 -130 -190 -130 190 {} +L 4 130 -190 130 190 {} +L 4 -150 -180 -130 -180 {} +L 4 -150 -160 -130 -160 {} +L 4 -150 -140 -130 -140 {} +L 4 -150 -120 -130 -120 {} +L 4 -150 -100 -130 -100 {} +L 4 -150 -80 -130 -80 {} +L 4 -150 -60 -130 -60 {} +L 4 -150 -40 -130 -40 {} +L 4 130 -20 150 -20 {} +L 4 130 0 150 0 {} +L 4 -150 -20 -130 -20 {} +L 4 130 20 150 20 {} +L 4 -150 0 -130 0 {} +L 4 -150 20 -130 20 {} +L 4 -150 40 -130 40 {} +L 4 130 40 150 40 {} +L 4 130 60 150 60 {} +L 4 -150 60 -130 60 {} +L 4 130 180 150 180 {} +L 7 130 -180 150 -180 {} +L 7 130 -160 150 -160 {} +L 7 130 -140 150 -140 {} +L 7 130 -120 150 -120 {} +L 7 130 -100 150 -100 {} +L 7 130 -80 150 -80 {} +L 7 130 -60 150 -60 {} +L 7 130 -40 150 -40 {} +L 7 130 80 150 80 {} +L 7 130 100 150 100 {} +L 7 130 120 150 120 {} +L 7 130 140 150 140 {} +L 7 130 160 150 160 {} +B 5 147.5 -182.5 152.5 -177.5 {name=vdda1 dir=inout } +B 5 147.5 -162.5 152.5 -157.5 {name=vdda2 dir=inout } +B 5 147.5 -142.5 152.5 -137.5 {name=vssa1 dir=inout } +B 5 147.5 -122.5 152.5 -117.5 {name=vssa2 dir=inout } +B 5 147.5 -102.5 152.5 -97.5 {name=vccd1 dir=inout } +B 5 147.5 -82.5 152.5 -77.5 {name=vccd2 dir=inout } +B 5 147.5 -62.5 152.5 -57.5 {name=vssd1 dir=inout } +B 5 147.5 -42.5 152.5 -37.5 {name=vssd2 dir=inout } +B 5 -152.5 -182.5 -147.5 -177.5 {name=wb_clk_i dir=in } +B 5 -152.5 -162.5 -147.5 -157.5 {name=wb_rst_i dir=in } +B 5 -152.5 -142.5 -147.5 -137.5 {name=wbs_stb_i dir=in } +B 5 -152.5 -122.5 -147.5 -117.5 {name=wbs_cyc_i dir=in } +B 5 -152.5 -102.5 -147.5 -97.5 {name=wbs_we_i dir=in } +B 5 -152.5 -82.5 -147.5 -77.5 {name=wbs_sel_i[3:0] dir=in } +B 5 -152.5 -62.5 -147.5 -57.5 {name=wbs_dat_i[31:0] dir=in } +B 5 -152.5 -42.5 -147.5 -37.5 {name=wbs_adr_i[31:0] dir=in } +B 5 147.5 -22.5 152.5 -17.5 {name=wbs_ack_o dir=out } +B 5 147.5 -2.5 152.5 2.5 {name=wbs_dat_o[31:0] dir=out } +B 5 -152.5 -22.5 -147.5 -17.5 {name=la_data_in[127:0] dir=in } +B 5 147.5 17.5 152.5 22.5 {name=la_data_out[127:0] dir=out } +B 5 -152.5 -2.5 -147.5 2.5 {name=la_oenb[127:0] dir=in } +B 5 -152.5 17.5 -147.5 22.5 {name=io_in[26:0] dir=in } +B 5 -152.5 37.5 -147.5 42.5 {name=io_in_3v3[26:0] dir=in } +B 5 147.5 37.5 152.5 42.5 {name=io_out[26:0] dir=out } +B 5 147.5 57.5 152.5 62.5 {name=io_oeb[26:0] dir=out } +B 5 147.5 77.5 152.5 82.5 {name=gpio_analog[17:0] dir=inout } +B 5 147.5 97.5 152.5 102.5 {name=gpio_noesd[17:0] dir=inout } +B 5 147.5 117.5 152.5 122.5 {name=io_analog[10:0] dir=inout } +B 5 147.5 137.5 152.5 142.5 {name=io_clamp_high[2:0] dir=inout } +B 5 147.5 157.5 152.5 162.5 {name=io_clamp_low[2:0] dir=inout } +B 5 -152.5 57.5 -147.5 62.5 {name=user_clock2 dir=in } +B 5 147.5 177.5 152.5 182.5 {name=user_irq[2:0] dir=out } +T {@symname} -119.5 114 0 0 0.3 0.3 {} +T {@name} 135 -202 0 0 0.2 0.2 {} +T {vdda1} 125 -184 0 1 0.2 0.2 {} +T {vdda2} 125 -164 0 1 0.2 0.2 {} +T {vssa1} 125 -144 0 1 0.2 0.2 {} +T {vssa2} 125 -124 0 1 0.2 0.2 {} +T {vccd1} 125 -104 0 1 0.2 0.2 {} +T {vccd2} 125 -84 0 1 0.2 0.2 {} +T {vssd1} 125 -64 0 1 0.2 0.2 {} +T {vssd2} 125 -44 0 1 0.2 0.2 {} +T {wb_clk_i} -125 -184 0 0 0.2 0.2 {} +T {wb_rst_i} -125 -164 0 0 0.2 0.2 {} +T {wbs_stb_i} -125 -144 0 0 0.2 0.2 {} +T {wbs_cyc_i} -125 -124 0 0 0.2 0.2 {} +T {wbs_we_i} -125 -104 0 0 0.2 0.2 {} +T {wbs_sel_i[3:0]} -125 -84 0 0 0.2 0.2 {} +T {wbs_dat_i[31:0]} -125 -64 0 0 0.2 0.2 {} +T {wbs_adr_i[31:0]} -125 -44 0 0 0.2 0.2 {} +T {wbs_ack_o} 125 -24 0 1 0.2 0.2 {} +T {wbs_dat_o[31:0]} 125 -4 0 1 0.2 0.2 {} +T {la_data_in[127:0]} -125 -24 0 0 0.2 0.2 {} +T {la_data_out[127:0]} 125 16 0 1 0.2 0.2 {} +T {la_oenb[127:0]} -125 -4 0 0 0.2 0.2 {} +T {io_in[26:0]} -125 16 0 0 0.2 0.2 {} +T {io_in_3v3[26:0]} -125 36 0 0 0.2 0.2 {} +T {io_out[26:0]} 125 36 0 1 0.2 0.2 {} +T {io_oeb[26:0]} 125 56 0 1 0.2 0.2 {} +T {gpio_analog[17:0]} 125 76 0 1 0.2 0.2 {} +T {gpio_noesd[17:0]} 125 96 0 1 0.2 0.2 {} +T {io_analog[10:0]} 125 116 0 1 0.2 0.2 {} +T {io_clamp_high[2:0]} 125 136 0 1 0.2 0.2 {} +T {io_clamp_low[2:0]} 125 156 0 1 0.2 0.2 {} +T {user_clock2} -125 56 0 0 0.2 0.2 {} +T {user_irq[2:0]} 125 176 0 1 0.2 0.2 {}
diff --git a/xschem/src/user_analog_project_wrapper/user_analog_project_wrapper_tb.sch b/xschem/src/user_analog_project_wrapper/user_analog_project_wrapper_tb.sch new file mode 100644 index 0000000..ff57b79 --- /dev/null +++ b/xschem/src/user_analog_project_wrapper/user_analog_project_wrapper_tb.sch
@@ -0,0 +1,386 @@ +v {xschem version=2.9.9 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N -1150 -300 -1150 -270 { lab=vref} +N -1150 -210 -1150 -170 { lab=GND} +N -1030 -210 -1030 -190 { lab=GND} +N -1090 -210 -1090 -180 { lab=GND} +N -710 -300 -710 -270 { lab=GND} +N 1130 -40 1210 -40 { lab=audio_p} +N 1150 -40 1150 -30 { lab=audio_p} +N 1150 30 1150 50 { lab=GND} +N 1150 200 1150 220 { lab=GND} +N 1120 140 1150 140 { lab=audio_n} +N 1210 10 1210 20 { lab=audio_p} +N 1150 140 1210 140 { lab=audio_n} +N 1210 80 1210 140 { lab=audio_n} +N 1210 -40 1210 10 { lab=audio_p} +N -1090 -300 -1090 -270 { lab=avdd} +N -1030 -300 -1030 -270 { lab=dvdd} +N -110 -360 -60 -360 { lab=io_analog[1]} +N -540 -360 -510 -360 { lab=#net1} +N -710 -360 -600 -360 { lab=vin} +N -400 -300 -400 -270 { lab=GND} +N -450 -360 -230 -360 { lab=io_analog[10]} +N -540 -200 -510 -200 { lab=#net2} +N -400 -140 -400 -110 { lab=GND} +N -450 -200 -400 -200 { lab=io_analog[1]} +N -640 -200 -600 -200 { lab=vref} +N -400 -200 -170 -200 { lab=io_analog[1]} +N -170 -320 -170 -200 { lab=io_analog[1]} +N -170 -340 -170 -320 { lab=io_analog[1]} +N 700 -40 730 -40 { lab=#net3} +N 590 -40 640 -40 { lab=io_analog[6:8]} +N 790 -40 830 -40 { lab=out_p} +N 880 -400 910 -400 { lab=#net4} +N 770 -400 820 -400 { lab=#net5} +N 970 -400 1010 -400 { lab=avdd} +N 880 -300 910 -300 { lab=#net6} +N 770 -300 820 -300 { lab=#net7} +N 970 -300 1010 -300 { lab=GND} +N 700 -400 770 -400 { lab=#net5} +N 710 -300 770 -300 { lab=#net7} +N 700 -300 710 -300 { lab=#net7} +N 700 140 730 140 { lab=#net8} +N 590 140 640 140 { lab=io_analog[2:4]} +N 790 140 830 140 { lab=out_n} +N 890 -200 920 -200 { lab=#net9} +N 780 -200 830 -200 { lab=#net10} +N 980 -200 1020 -200 { lab=dvdd} +N 710 -200 780 -200 { lab=#net10} +N 530 140 590 140 { lab=io_analog[2:4]} +N 520 140 530 140 { lab=io_analog[2:4]} +N 700 -200 710 -200 { lab=#net10} +N 830 -40 1070 -40 { lab=out_p} +N 830 140 970 140 { lab=out_n} +N 970 140 1060 140 { lab=out_n} +N -170 -360 -170 -340 { lab=io_analog[1]} +N -170 -360 -110 -360 { lab=io_analog[1]} +N -230 -380 -230 -360 { lab=io_analog[10]} +N -230 -380 -60 -380 { lab=io_analog[10]} +N 270 -390 700 -390 { lab=#net5} +N 700 -400 700 -390 { lab=#net5} +N 270 -370 700 -370 { lab=#net5} +N 700 -390 700 -370 { lab=#net5} +N 270 -350 270 -330 { lab=#net7} +N 270 -330 700 -330 { lab=#net7} +N 700 -330 700 -300 { lab=#net7} +N 270 -270 700 -270 { lab=#net7} +N 700 -300 700 -270 { lab=#net7} +N 270 -250 700 -250 { lab=#net7} +N 700 -270 700 -250 { lab=#net7} +N 270 -310 270 -290 { lab=#net10} +N 270 -290 650 -290 { lab=#net10} +N 650 -290 650 -200 { lab=#net10} +N 650 -200 700 -200 { lab=#net10} +N 270 -90 360 -90 { lab=io_analog[10:0]} +N 520 -40 590 -40 { lab=io_analog[6:8]} +N 870 290 900 290 { lab=#net11} +N 760 290 810 290 { lab=io_analog[5]} +N 960 290 1000 290 { lab=dvdd} +N 710 290 760 290 { lab=io_analog[5]} +N 860 450 890 450 { lab=#net12} +N 750 450 800 450 { lab=io_analog[0]} +N 950 450 990 450 { lab=#net13} +N 700 450 750 450 { lab=io_analog[0]} +N 1050 450 1230 450 { lab=avdd} +C {gnd.sym} -1150 -170 0 0 {name=l2 lab=GND} +C {netlist_not_shown.sym} 1450 -770 0 0 {name=TT_MODELS1 +spice_ignore=false +only_toplevel=true +format="tcleval( @value )" +value=" +.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice +.include /home/eda/magic/class_d_audio_amplifier/Class_D/Class_D_post.spice + +* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice +.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice +* Special cells +.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice + +" +} +C {vsource.sym} -1150 -240 0 0 {name=V5 value=0.9} +C {vsource.sym} -1030 -240 0 0 {name=V1 value=1.8} +C {gnd.sym} -1030 -190 0 0 {name=l4 lab=GND} +C {vsource.sym} -1090 -240 0 0 {name=V2 value="pulse(0 1.8 0 1u 1u 1 2)"} +C {gnd.sym} -1090 -180 0 0 {name=l6 lab=GND} +C {lab_wire.sym} -1150 -280 0 0 {name=l5 sig_type=std_logic lab=vref} +C {lab_wire.sym} -1030 -280 0 0 {name=l7 sig_type=std_logic lab=dvdd} +C {lab_wire.sym} -1090 -280 0 0 {name=l8 sig_type=std_logic lab=avdd} +C {vsource.sym} -710 -330 0 0 {name=V3 value="sin(0.9 0.4 5k)"} +C {gnd.sym} -710 -270 0 0 {name=l10 lab=GND} +C {ind.sym} 1100 -40 1 0 {name=L1 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 1150 0 0 0 {name=C1 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {ind.sym} 1090 140 3 1 {name=L2 +m=1 +value=28u +footprint=1206 +device=inductor} +C {capa.sym} 1150 170 0 1 {name=C4 +m=1 +value=1.3u +footprint=1206 +device="ceramic capacitor"} +C {res.sym} 1210 50 2 0 {name=R6 +value=8 +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} 1160 -40 0 1 {name=l43 sig_type=std_logic lab=audio_p} +C {lab_wire.sym} 1160 140 0 1 {name=l44 sig_type=std_logic lab=audio_n} +C {gnd.sym} 1150 220 0 0 {name=l55 lab=GND} +C {gnd.sym} 1150 50 0 0 {name=l58 lab=GND} +C {code_shown.sym} -1080 -980 0 0 {name=s2 only_toplevel=false value=" +.option rshunt=1e20 +.nodeset all=0.7 +*.option VNTOL=1e-6 ABSTOL=1e-9 +*.option savecurrents +*set the absolute voltage error tolerance and absolute current error tolerance +.control +save out_p out_n audio_p audio_n I(V1) I(V2) @r6[i] x1.x1.vtriang x1.x1.vin_n x1.x1.vin_n +*save all +*save vtriang audio_p audio_n I(V2) @r6[i] out_p out_n +*op +tran 1n 5m 0.5m +*linearize V(audio) +*linearize V(out) +*fft V(out) +*fft V(audio) +*plot mag(V(audio)) +*plot mag(V(out)) +let pout=(V(audio_p)-V(audio_n))*(V(audio_p)-V(audio_n))/@r6[i] +let pin=1.8*(I(V2)+I(V1)) +meas tran pload avg pout from=1m to=5m +meas tran p_supply avg pin from=1m to=5m +*print pload/p_supply +set nfreqs=5 +*fourier 10k V(out_p)-V(out_n) + +fourier 5k V(audio_p)-V(audio_n) +write class_d_5k_04_presim_with_wrapper.raw + +.endc + + +"} +C {lab_wire.sym} -640 -360 0 0 {name=l22 sig_type=std_logic lab=vin} +C {ind.sym} -570 -360 1 0 {name=L3 +m=1 +value=1n +footprint=1206 +device=inductor} +C {res.sym} -480 -360 1 0 {name=R4 +value=0.05 +footprint=1206 +device=resistor +m=1} +C {capa.sym} -400 -330 0 0 {name=C2 +m=1 +value=1p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} -400 -270 0 0 {name=l11 lab=GND} +C {ind.sym} -570 -200 1 0 {name=L4 +m=1 +value=1n +footprint=1206 +device=inductor} +C {res.sym} -480 -200 1 0 {name=R5 +value=0.05 +footprint=1206 +device=resistor +m=1} +C {capa.sym} -400 -170 0 0 {name=C3 +m=1 +value=1p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} -400 -110 0 0 {name=l13 lab=GND} +C {ind.sym} 760 -40 3 1 {name=L7 +m=1 +value=0.3n +footprint=1206 +device=inductor} +C {res.sym} 670 -40 3 1 {name=R9 +value=0.02 +footprint=1206 +device=resistor +m=1} +C {capa.sym} 590 -10 0 1 {name=C7 +m=1 +value=3p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 590 20 0 1 {name=l18 lab=GND} +C {ind.sym} 940 -400 3 1 {name=L11 +m=1 +value=0.3n +footprint=1206 +device=inductor} +C {res.sym} 850 -400 3 1 {name=R13 +value=0.02 +footprint=1206 +device=resistor +m=1} +C {capa.sym} 770 -370 0 1 {name=C11 +m=1 +value=3p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 770 -340 0 1 {name=l24 lab=GND} +C {ind.sym} 940 -300 3 1 {name=L12 +m=1 +value=0.3n +footprint=1206 +device=inductor} +C {res.sym} 850 -300 3 1 {name=R14 +value=0.02 +footprint=1206 +device=resistor +m=1} +C {capa.sym} 770 -270 0 1 {name=C12 +m=1 +value=3p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 770 -240 0 1 {name=l25 lab=GND} +C {ind.sym} 760 140 3 1 {name=L16 +m=1 +value=0.3n +footprint=1206 +device=inductor} +C {res.sym} 670 140 3 1 {name=R18 +value=0.02 +footprint=1206 +device=resistor +m=1} +C {capa.sym} 590 170 0 1 {name=C16 +m=1 +value=3p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 590 200 0 1 {name=l23 lab=GND} +C {ind.sym} 950 -200 3 1 {name=L18 +m=1 +value=0.3n +footprint=1206 +device=inductor} +C {res.sym} 860 -200 3 1 {name=R20 +value=0.02 +footprint=1206 +device=resistor +m=1} +C {capa.sym} 780 -170 0 1 {name=C18 +m=1 +value=3p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 780 -140 0 1 {name=l29 lab=GND} +C {lab_wire.sym} 1000 -400 0 1 {name=l30 sig_type=std_logic lab=avdd} +C {gnd.sym} 1010 -300 0 1 {name=l1 lab=GND} +C {lab_wire.sym} 1010 -200 0 1 {name=l31 sig_type=std_logic lab=dvdd} +C {lab_wire.sym} -620 -200 0 0 {name=l33 sig_type=std_logic lab=vref} +C {lab_wire.sym} 910 140 0 1 {name=l45 sig_type=std_logic lab=out_n} +C {capa.sym} -640 -170 0 0 {name=C20 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {capa.sym} -630 -330 0 0 {name=C21 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} -640 -140 0 0 {name=l49 lab=GND} +C {gnd.sym} -630 -300 0 0 {name=l50 lab=GND} +C {capa.sym} 890 -10 0 0 {name=C23 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 890 20 0 1 {name=l52 lab=GND} +C {capa.sym} 1000 -370 0 0 {name=C27 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 1000 -340 0 1 {name=l57 lab=GND} +C {capa.sym} 1010 -170 0 0 {name=C31 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 1010 -140 0 1 {name=l62 lab=GND} +C {src/user_analog_project_wrapper/user_analog_project_wrapper.sym} 120 -210 0 0 {name=x1} +C {lab_wire.sym} 330 -90 0 1 {name=l3 sig_type=std_logic lab=io_analog[10:0]} +C {lab_wire.sym} 970 -40 0 1 {name=l9 sig_type=std_logic lab=out_p} +C {lab_wire.sym} 540 -40 0 1 {name=l12 sig_type=std_logic lab=io_analog[6:8]} +C {lab_wire.sym} 530 140 0 1 {name=l14 sig_type=std_logic lab=io_analog[2:4]} +C {ind.sym} 930 290 3 1 {name=L5 +m=1 +value=0.3n +footprint=1206 +device=inductor} +C {res.sym} 840 290 3 1 {name=R1 +value=0.02 +footprint=1206 +device=resistor +m=1} +C {capa.sym} 760 320 0 1 {name=C5 +m=1 +value=3p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 760 350 0 1 {name=l15 lab=GND} +C {lab_wire.sym} 990 290 0 1 {name=l16 sig_type=std_logic lab=dvdd} +C {capa.sym} 990 320 0 0 {name=C6 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 990 350 0 1 {name=l17 lab=GND} +C {lab_wire.sym} 720 290 0 1 {name=l19 sig_type=std_logic lab=io_analog[5]} +C {ind.sym} 920 450 3 1 {name=L6 +m=1 +value=0.3n +footprint=1206 +device=inductor} +C {res.sym} 830 450 3 1 {name=R2 +value=0.02 +footprint=1206 +device=resistor +m=1} +C {capa.sym} 750 480 0 1 {name=C8 +m=1 +value=3p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 750 510 0 1 {name=l20 lab=GND} +C {lab_wire.sym} 1210 450 0 1 {name=l21 sig_type=std_logic lab=avdd} +C {capa.sym} 1210 480 0 0 {name=C9 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} +C {gnd.sym} 1210 510 0 1 {name=l26 lab=GND} +C {lab_wire.sym} 710 450 0 1 {name=l27 sig_type=std_logic lab=io_analog[0]} +C {res.sym} 1020 450 3 1 {name=R3 +value=83k +footprint=1206 +device=resistor +m=1} +C {lab_wire.sym} -210 -380 0 1 {name=l28 sig_type=std_logic lab=io_analog[10]} +C {lab_wire.sym} -250 -200 0 1 {name=l32 sig_type=std_logic lab=io_analog[1]}
diff --git a/xschem/xschemrc b/xschem/xschemrc index 98fead5..ce73123 100644 --- a/xschem/xschemrc +++ b/xschem/xschemrc
@@ -28,13 +28,16 @@ #### Flush any previous definition set XSCHEM_LIBRARY_PATH {} #### include devices/*.sym -append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library -#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here. -append XSCHEM_LIBRARY_PATH :$env(PWD) -append XSCHEM_LIBRARY_PATH :/usr/share/pdk/sky130A/libs.tech/xschem -#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem) -append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library +append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library/devices +append XSCHEM_LIBRARY_PATH :/home/eda/pdk/sky130A/libs.tech/xschem +#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here. +#append XSCHEM_LIBRARY_PATH :/home/eda/xschem/xschem_library +#append XSCHEM_LIBRARY_PATH :/home/eda/.xschem/xschem_library/xschem_sky130 +# append XSCHEM_LIBRARY_PATH :/mnt/sda7/home/schippes/pdks/sky130A/libs.tech/xschem +#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem) +#append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library +append XSCHEM_LIBRARY_PATH :/home/eda/xschem/xschem_library ########################################################################### #### SET CUSTOM COLORS FOR XSCHEM LIBRARIES MATCHING CERTAIN PATTERNS ########################################################################### @@ -54,14 +57,13 @@ #### Start without a design if no filename given on command line: #### To avoid absolute paths, use a path that is relative to one of the #### XSCHEM_LIBRARY_PATH directories. Default: empty -set XSCHEM_START_WINDOW {sky130_tests/top.sch} +set XSCHEM_START_WINDOW {} ########################################################################### #### DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED ########################################################################### #### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations) -# set netlist_dir $env(HOME)/.xschem/simulations -set netlist_dir . +#set netlist_dir $env(HOME)/.xschem/simulations ########################################################################### #### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS @@ -257,8 +259,8 @@ ########################################################################### #### list of tcl files to preload. # lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl -lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl -lappend tcl_files /usr/share/pdk/sky130A/libs.tech/xschem/scripts/sky130_models.tcl +#lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl +#lappend tcl_files /home/eda/.xschem/xschem_library/xschem_sky130/scripts/sky130_models.tcl ########################################################################### #### XSCHEM TOOLBAR ########################################################################### @@ -269,5 +271,13 @@ ########################################################################### #### SKYWATER PDK SPECIFIC VARIABLES ########################################################################### -set SKYWATER_MODELS ~/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest -set SKYWATER_STDCELLS ~/skywater-pdk/libraries/sky130_fd_sc_hd/latest + +## (spice patched) skywater-pdk install +set SKYWATER_MODELS /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest +set SKYWATER_STDCELLS /home/eda/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest + + +set gaw_tcl_address {localhost 2020} +## opencircuitdesign pdks install +#set SKYWATER_MODELS /home/eda/pdk/sky130A/libs.tech/ngspice +#set SKYWATER_STDCELLS /home/eda/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice