| /root/ucsc_openram_test_chip_v2/Makefile |
| /root/ucsc_openram_test_chip_v2/docs/environment.yml |
| /root/ucsc_openram_test_chip_v2/docs/Makefile |
| /root/ucsc_openram_test_chip_v2/docs/source/index.rst |
| /root/ucsc_openram_test_chip_v2/docs/source/conf.py |
| /root/ucsc_openram_test_chip_v2/verilog/dv/Makefile |
| /root/ucsc_openram_test_chip_v2/verilog/dv/la_test/Makefile |
| /root/ucsc_openram_test_chip_v2/verilog/dv/la_test/la_test.c |
| /root/ucsc_openram_test_chip_v2/verilog/dv/la_test/la_test_tb.v |
| /root/ucsc_openram_test_chip_v2/verilog/dv/la_test2/la_test2_tb.v |
| /root/ucsc_openram_test_chip_v2/verilog/dv/la_test2/la_test2.c |
| /root/ucsc_openram_test_chip_v2/verilog/dv/la_test2/Makefile |
| /root/ucsc_openram_test_chip_v2/verilog/dv/la_test1/la_test1.c |
| /root/ucsc_openram_test_chip_v2/verilog/dv/la_test1/Makefile |
| /root/ucsc_openram_test_chip_v2/verilog/dv/la_test1/la_test1_tb.v |
| /root/ucsc_openram_test_chip_v2/verilog/dv/io_ports/Makefile |
| /root/ucsc_openram_test_chip_v2/verilog/dv/io_ports/io_ports_tb.v |
| /root/ucsc_openram_test_chip_v2/verilog/dv/io_ports/io_ports.c |
| /root/ucsc_openram_test_chip_v2/verilog/dv/gpio_test/Makefile |
| /root/ucsc_openram_test_chip_v2/verilog/dv/gpio_test/gpio_test_tb.v |
| /root/ucsc_openram_test_chip_v2/verilog/dv/gpio_test/gpio_test.c |
| /root/ucsc_openram_test_chip_v2/verilog/dv/mprj_stimulus/Makefile |
| /root/ucsc_openram_test_chip_v2/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/ucsc_openram_test_chip_v2/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/ucsc_openram_test_chip_v2/verilog/dv/wb_port/wb_port_tb.v |
| /root/ucsc_openram_test_chip_v2/verilog/dv/wb_port/Makefile |
| /root/ucsc_openram_test_chip_v2/verilog/dv/wb_port/wb_port.c |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/openram_testchip.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/sky130_sram_1kbyte_1rw_32x256_8.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/sky130_sram_2kbyte_1rw_32x512_8.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/uprj_netlists.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/sky130_sram_4kbyte_1rw_64x512_8.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/openram_defines.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/sky130_sram_4kbyte_1rw1r_32x1024_8.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/user_project_wrapper.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/sky130_sram_4kbyte_1rw_32x1024_8.v |
| /root/ucsc_openram_test_chip_v2/verilog/rtl/sky130_sram_8kbyte_1rw_64x1024_8.v |
| /root/ucsc_openram_test_chip_v2/gds/uniquify.sh |
| /root/ucsc_openram_test_chip_v2/openlane/Makefile |
| /root/ucsc_openram_test_chip_v2/openlane/user_project_wrapper/config.json |
| /root/ucsc_openram_test_chip_v2/openlane/user_project_wrapper/base.sdc |
| /root/ucsc_openram_test_chip_v2/openlane/user_project_wrapper/user_project_wrapper.sdc |
| /root/ucsc_openram_test_chip_v2/openlane/user_project_wrapper/config.tcl |
