jobs/mpw_precheck/c052a17e-8cf8-4059-8abd-3aa5d95ab057/logs/precheck.log

2021-12-16 22:09:37 - [INFO] - {{Project Git Info}} Repository: https://github.com/VLSIDA/openram_testchip.git | Branch: main | Commit: ce65f0064ab72841112285bce9212c6673d290ce
2021-12-16 22:09:37 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: ucsc_openram_test_chip_v2
2021-12-16 22:09:44 - [INFO] - {{Project GDS Info}} user_project_wrapper: 2d03d9cbf301b6fce1fa591b4794ba3b6caf290b
2021-12-16 22:09:44 - [INFO] - {{Tools Info}} KLayout: v0.27.3 | Magic: v8.3.220
2021-12-16 22:09:44 - [INFO] - {{PDKs Info}} Open PDKs: 14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2021-12-16 22:09:44 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'ucsc_openram_test_chip_v2/jobs/mpw_precheck/c052a17e-8cf8-4059-8abd-3aa5d95ab057/logs'
2021-12-16 22:09:44 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Manifest Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
2021-12-16 22:09:44 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
2021-12-16 22:09:45 - [INFO] - An approved LICENSE (Apache-2.0) was found in ucsc_openram_test_chip_v2.
2021-12-16 22:09:45 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2021-12-16 22:09:46 - [INFO] - An approved LICENSE (Apache-2.0) was found in ucsc_openram_test_chip_v2.
2021-12-16 22:09:46 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2021-12-16 22:09:46 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 47 non-compliant file(s) with the SPDX Standard.
2021-12-16 22:09:46 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['ucsc_openram_test_chip_v2/Makefile', 'ucsc_openram_test_chip_v2/docs/environment.yml', 'ucsc_openram_test_chip_v2/docs/Makefile', 'ucsc_openram_test_chip_v2/docs/source/index.rst', 'ucsc_openram_test_chip_v2/docs/source/conf.py', 'ucsc_openram_test_chip_v2/verilog/dv/Makefile', 'ucsc_openram_test_chip_v2/verilog/dv/la_test/Makefile', 'ucsc_openram_test_chip_v2/verilog/dv/la_test/la_test.c', 'ucsc_openram_test_chip_v2/verilog/dv/la_test/la_test_tb.v', 'ucsc_openram_test_chip_v2/verilog/dv/la_test2/la_test2_tb.v', 'ucsc_openram_test_chip_v2/verilog/dv/la_test2/la_test2.c', 'ucsc_openram_test_chip_v2/verilog/dv/la_test2/Makefile', 'ucsc_openram_test_chip_v2/verilog/dv/la_test1/la_test1.c', 'ucsc_openram_test_chip_v2/verilog/dv/la_test1/Makefile', 'ucsc_openram_test_chip_v2/verilog/dv/la_test1/la_test1_tb.v']
2021-12-16 22:09:46 - [INFO] - For the full SPDX compliance report check: ucsc_openram_test_chip_v2/jobs/mpw_precheck/c052a17e-8cf8-4059-8abd-3aa5d95ab057/logs/spdx_compliance_report.log
2021-12-16 22:09:46 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Manifest
2021-12-16 22:09:46 - [INFO] - Caravel version matches, for the full report check: ucsc_openram_test_chip_v2/jobs/mpw_precheck/c052a17e-8cf8-4059-8abd-3aa5d95ab057/logs/manifest_check.log
2021-12-16 22:09:46 - [INFO] - {{MANIFEST CHECKS PASSED}} Manifest Checks Passed. Caravel version matches.
2021-12-16 22:09:46 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Makefile
2021-12-16 22:09:46 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2021-12-16 22:09:46 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Default
2021-12-16 22:09:46 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2021-12-16 22:09:52 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2021-12-16 22:09:52 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Documentation
2021-12-16 22:09:52 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2021-12-16 22:09:52 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: Consistency
2021-12-16 22:09:52 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/__user_project_wrapper.v
2021-12-16 22:09:52 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/__user_project_wrapper.v
2021-12-16 22:09:52 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/defines.v
2021-12-16 22:09:52 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/defines.v
2021-12-16 22:10:05 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
2021-12-16 22:10:05 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (46 instances). 
2021-12-16 22:10:05 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
2021-12-16 22:10:05 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
2021-12-16 22:10:05 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2021-12-16 22:10:05 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2021-12-16 22:10:05 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2021-12-16 22:10:05 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (3782 instances). 
2021-12-16 22:10:05 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2021-12-16 22:10:05 - [WARNING] - LAYOUT CHECK FAILED: The GDS layout for user_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['sky130_ef_sc_hd__decap_12' 'sky130_sram_1kbyte_1rw_32x256_8$1'
 'sky130_sram_2kbyte_1rw_32x512_8$1' 'sky130_sram_4kbyte_1rw_32x1024_8$1'
 'sky130_sram_4kbyte_1rw_64x512_8$1' 'sky130_sram_8kbyte_1rw_64x1024_8$1']
2021-12-16 22:10:05 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2021-12-16 22:10:05 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2021-12-16 22:10:05 - [WARNING] - {{NETLIST CONSISTENCY CHECK FAILED}} user_project_wrapper netlist failed 1 consistency check(s): ['LAYOUT'].
2021-12-16 22:10:06 - [WARNING] - {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
2021-12-16 22:10:06 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
2021-12-16 22:10:06 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/gds/user_project_wrapper_empty.gds.gz
2021-12-16 22:10:06 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/gds/user_project_wrapper_empty.gds.gz
2021-12-16 22:32:33 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view ucsc_openram_test_chip_v2/jobs/mpw_precheck/c052a17e-8cf8-4059-8abd-3aa5d95ab057/outputs/user_project_wrapper.xor.gds
2021-12-16 22:32:33 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2021-12-16 22:32:33 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC