added wishbone_wrapper as another source file

verilog/rtl/uprj_netlists.v

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 44cc2b2..3330e84 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,6 +25,7 @@
 `else
     `include "user_project_wrapper.v"
     `include "openram_testchip.v"
+	`include "wishbone_wrapper.v"
     `include "sky130_sram_1kbyte_1rw1r_8x1024_8.v"
     `include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
     `include "sky130_sram_2kbyte_1rw1r_32x512_8.v"