| commit | 805c9a0728def3bab0f4238c346ef59a7c0386d3 | [log] [tgz] |
|---|---|---|
| author | hadirkhan10 <hadirkhan10@gmail.com> | Sun Dec 19 23:07:21 2021 -0800 |
| committer | hadirkhan10 <hadirkhan10@gmail.com> | Sun Dec 19 23:07:21 2021 -0800 |
| tree | 065e0737f59ca86518d651a15cdd6b4a025a99b8 | |
| parent | 9dbcb8c58d9f215d0938f95f28b71f1be3e5dc72 [diff] |
added wishbone_wrapper as another source file
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 44cc2b2..3330e84 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -25,6 +25,7 @@ `else `include "user_project_wrapper.v" `include "openram_testchip.v" + `include "wishbone_wrapper.v" `include "sky130_sram_1kbyte_1rw1r_8x1024_8.v" `include "sky130_sram_1kbyte_1rw1r_32x256_8.v" `include "sky130_sram_2kbyte_1rw1r_32x512_8.v"