Add missing disconnected wire declaration

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index acf0976..089f2ea 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -345,6 +345,9 @@
 
 
 // Single port memories
+
+wire disconn8, disconn9, disconn10, disconn11, disconn12;
+
 sky130_sram_1kbyte_1rw_32x256_8 SRAM8
     (
       `ifdef USE_POWER_PINS