verilog/rtl/mkAudiofifo.v

/*
//Copyright 2021 S SIVA PRASAD ssprasad12a@gmail.com

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/

//
// Generated by Bluespec Compiler, version 2017.07.A (build 1da80f1, 2017-07-21)
//
// On Wed Oct 13 11:06:55 IST 2021
//
//
// Ports:
// Name                         I/O  size props
// RDY_data                       O     1
// RDY_deq_data                   O     1
// first                          O    32
// RDY_first                      O     1
// empty                          O     1
// RDY_empty                      O     1 const
// full                           O     1
// RDY_full                       O     1 const
// nempty                         O     1
// RDY_nempty                     O     1 const
// nfull                          O     1
// RDY_nfull                      O     1 const
// CLK_wr_clk                     I     1 clock
// RST_N_wr_rstn                  I     1 reset
// CLK_rd_clk                     I     1 clock
// data_enq_data                  I    32
// EN_data                        I     1
// EN_deq_data                    I     1
// EN_first                       I     1 unused
//
// No combinational paths from inputs to outputs
//
//
// generated by ssp for audio fifo

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkAudiofifo(CLK_wr_clk,
		   RST_N_wr_rstn,
		   CLK_rd_clk,
		

		   data_enq_data,
		   EN_data,
		   RDY_data,

		   EN_deq_data,
		   RDY_deq_data,

		   EN_first,
		   first,
		   RDY_first,

		   empty,
		   RDY_empty,

		   full,
		   RDY_full,

		   nempty,
		   RDY_nempty,

		   nfull,
		   RDY_nfull);
  input  CLK_wr_clk;
  input  RST_N_wr_rstn;
  input  CLK_rd_clk;
  

  // action method data
  input  [31 : 0] data_enq_data;
  input  EN_data;
  output RDY_data;

  // action method deq_data
  input  EN_deq_data;
  output RDY_deq_data;

  // actionvalue method first
  input  EN_first;
  output [31 : 0] first;
  output RDY_first;

  // value method empty
  output empty;
  output RDY_empty;

  // value method full
  output full;
  output RDY_full;

  // value method nempty
  output nempty;
  output RDY_nempty;

  // value method nfull
  output nfull;
  output RDY_nfull;

  // signals for module outputs
  wire [31 : 0] first;
  wire RDY_data,
       RDY_deq_data,
       RDY_empty,
       RDY_first,
       RDY_full,
       RDY_nempty,
       RDY_nfull,
       empty,
       full,
       nempty,
       nfull;

  // ports of submodule cdcfifo
  wire [31 : 0] cdcfifo_dD_OUT, cdcfifo_sD_IN;
  wire cdcfifo_dDEQ, cdcfifo_dEMPTY_N, cdcfifo_sENQ, cdcfifo_sFULL_N;

  // rule scheduling signals
  wire CAN_FIRE_data,
       CAN_FIRE_deq_data,
       CAN_FIRE_first,
       WILL_FIRE_data,
       WILL_FIRE_deq_data,
       WILL_FIRE_first;

  // action method data
  assign RDY_data = cdcfifo_sFULL_N ;
  assign CAN_FIRE_data = cdcfifo_sFULL_N ;
  assign WILL_FIRE_data = EN_data ;

  // action method deq_data
  assign RDY_deq_data = cdcfifo_dEMPTY_N ;
  assign CAN_FIRE_deq_data = cdcfifo_dEMPTY_N ;
  assign WILL_FIRE_deq_data = EN_deq_data ;

  // actionvalue method first
  assign first = cdcfifo_dD_OUT ;
  assign RDY_first = cdcfifo_dEMPTY_N ;
  assign CAN_FIRE_first = cdcfifo_dEMPTY_N ;
  assign WILL_FIRE_first = EN_first ;

  // value method empty
  assign empty = !cdcfifo_dEMPTY_N ;
  assign RDY_empty = 1'd1 ;

  // value method full
  assign full = !cdcfifo_sFULL_N ;
  assign RDY_full = 1'd1 ;

  // value method nempty
  assign nempty = cdcfifo_dEMPTY_N ;
  assign RDY_nempty = 1'd1 ;

  // value method nfull
  assign nfull = cdcfifo_sFULL_N ;
  assign RDY_nfull = 1'd1 ;

  // submodule cdcfifo
  SyncFIFO #(.dataWidth(32'd32),
	     .depth(32'd16),
	     .indxWidth(32'd4)) cdcfifo(.sCLK(CLK_wr_clk),
					.dCLK(CLK_rd_clk),
					.sRST(RST_N_wr_rstn),
					.sD_IN(cdcfifo_sD_IN),
					.sENQ(cdcfifo_sENQ),
					.dDEQ(cdcfifo_dDEQ),
					.sFULL_N(cdcfifo_sFULL_N),
					.dEMPTY_N(cdcfifo_dEMPTY_N),
					.dD_OUT(cdcfifo_dD_OUT));

  // submodule cdcfifo
  assign cdcfifo_sD_IN = data_enq_data ;
  assign cdcfifo_sENQ = EN_data ;
  assign cdcfifo_dDEQ = EN_deq_data ;
endmodule  // mkAudiofifo