commit	c928ee3b18cb4dcb77c15ce375cdfc78f9d18ef2	[log] [tgz]
author	dineshannayya <dinesh.annayya@gmail.com>	Fri Nov 19 21:20:20 2021 +0530
committer	dineshannayya <dinesh.annayya@gmail.com>	Fri Nov 19 21:20:20 2021 +0530
tree	f306da5cd1908a4e5171ca0482c28567707d8117
parent	7e64246e9aeac33073daa9f5b9ef7b376d34d7b7 [diff]

4x SRAM + 4x MBIST integrated with wishbone interconnect

def/glbl_cfg.def.gz[Added - diff]
def/mbist.def.gz[Deleted - diff]
def/mbist1.def.gz[Added - diff]
def/mbist2.def.gz[Added - diff]
def/user_project_wrapper.def.gz[diff]
def/wb_host.def.gz[diff]
def/wb_interconnect.def.gz[Added - diff]
gds/glbl_cfg.gds.gz[Added - diff]
gds/mbist.gds.gz[Deleted - diff]
gds/mbist1.gds.gz[Added - diff]
gds/mbist2.gds.gz[Added - diff]
gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds.gz[Added - diff]
gds/user_project_wrapper.gds.gz[diff]
gds/wb_host.gds.gz[diff]
gds/wb_interconnect.gds.gz[Added - diff]
lef/glbl_cfg.lef.gz[Added - diff]
lef/mbist.lef.gz[Deleted - diff]
lef/mbist1.lef.gz[Added - diff]
lef/mbist2.lef.gz[Added - diff]
lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef.gz[Added - diff]
lef/user_project_wrapper.lef.gz[diff]
lef/wb_host.lef.gz[diff]
lef/wb_interconnect.lef.gz[Added - diff]
lib/sram_1rw1r_32_256_8_sky130_FF_1p8V_25C.lib[Added - diff]
lib/sram_1rw1r_32_256_8_sky130_SS_1p8V_25C.lib[Added - diff]
lib/sram_1rw1r_32_256_8_sky130_TT_1p8V_25C.lib[Added - diff]
mag/glbl_cfg.mag.gz[Added - diff]
mag/mbist.mag.gz[Deleted - diff]
mag/mbist1.mag.gz[Added - diff]
mag/mbist2.mag.gz[Added - diff]
mag/user_project_wrapper.mag.gz[diff]
mag/wb_host.mag.gz[diff]
mag/wb_interconnect.mag.gz[Added - diff]
maglef/glbl_cfg.mag.gz[Added - diff]
maglef/mbist.mag.gz[Deleted - diff]
maglef/mbist1.mag.gz[Added - diff]
maglef/mbist2.mag.gz[Added - diff]
maglef/user_project_wrapper.mag.gz[diff]
maglef/wb_host.mag.gz[diff]
maglef/wb_interconnect.mag.gz[Added - diff]
openlane/Makefile[diff]
openlane/glbl_cfg/base.sdc[Added - diff]
openlane/glbl_cfg/config.tcl[Copied from openlane/mbist/config.tcl - diff]
openlane/glbl_cfg/pdn.tcl[Added - diff]
openlane/glbl_cfg/pin_order.cfg[Added - diff]
openlane/mbist/base.sdc[Deleted - diff]
openlane/mbist/pin_order.cfg[Deleted - diff]
openlane/mbist1/base.sdc[Added - diff]
openlane/mbist1/config.tcl[Copied from openlane/mbist/config.tcl - diff]
openlane/mbist1/interactive.tcl[Added - diff]
openlane/mbist1/pin_order.cfg[Added - diff]
openlane/mbist1/sta.tcl[Renamed from openlane/mbist/sta.tcl - diff]
openlane/mbist2/base.sdc[Added - diff]
openlane/mbist2/config.tcl[Renamed from openlane/mbist/config.tcl - diff]
openlane/mbist2/interactive.tcl[Added - diff]
openlane/mbist2/pin_order.cfg[Added - diff]
openlane/mbist2/sta.tcl[Copied from openlane/mbist/sta.tcl - diff]
openlane/user_project_wrapper/base.sdc[diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/sta.tcl[diff]
openlane/wb_host/config.tcl[diff]
openlane/wb_host/pin_order.cfg[diff]
openlane/wb_interconnect/.sta.tcl.swp[Added - diff]
openlane/wb_interconnect/base.sdc[Added - diff]
openlane/wb_interconnect/config.tcl[Copied from openlane/mbist/config.tcl - diff]
openlane/wb_interconnect/pdn.tcl[Added - diff]
openlane/wb_interconnect/pin_order.cfg[Added - diff]
openlane/wb_interconnect/sta.tcl[Added - diff]
signoff/glbl_cfg/OPENLANE_VERSION[Added - diff]
signoff/glbl_cfg/PDK_SOURCES[Added - diff]
signoff/glbl_cfg/final_summary_report.csv[Added - diff]
signoff/mbist1/OPENLANE_VERSION[Added - diff]
signoff/mbist1/PDK_SOURCES[Added - diff]
signoff/mbist1/final_summary_report.csv[Added - diff]
signoff/mbist2/OPENLANE_VERSION[Added - diff]
signoff/mbist2/PDK_SOURCES[Added - diff]
signoff/mbist2/final_summary_report.csv[Added - diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
signoff/wb_host/final_summary_report.csv[diff]
signoff/wb_interconnect/OPENLANE_VERSION[Added - diff]
signoff/wb_interconnect/PDK_SOURCES[Added - diff]
signoff/wb_interconnect/final_summary_report.csv[Added - diff]
spi/lvs/glbl_cfg.spice.gz[Added - diff]
spi/lvs/mbist.spice.gz[Deleted - diff]
spi/lvs/mbist1.spice.gz[Added - diff]
spi/lvs/mbist2.spice.gz[Added - diff]
spi/lvs/user_project_wrapper.spice.gz[diff]
spi/lvs/wb_host.spice.gz[diff]
spi/lvs/wb_interconnect.spice.gz[Added - diff]
verilog/dv/user_basic/user_basic_tb.v[diff]
verilog/dv/user_mbist_test1/user_mbist_test1_tb.v[diff]
verilog/dv/wb_port/wb_port.c[diff]
verilog/dv/wb_port/wb_port_tb.v[diff]
verilog/gl/glbl_cfg.v[Added - diff]
verilog/gl/mbist.v[Deleted - diff]
verilog/gl/mbist1.v[Added - diff]
verilog/gl/mbist2.v[Added - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/gl/wb_host.v[diff]
verilog/gl/wb_interconnect.v[Added - diff]
verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv[Added - diff]
verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v[Added - diff]
verilog/rtl/clk_skew_adjust/synth/Makefile[Added - diff]
verilog/rtl/clk_skew_adjust/synth/synth.tcl[Added - diff]
verilog/rtl/glbl/src/glbl_cfg.sv[Added - diff]
verilog/rtl/glbl/src/run_iverilog[Added - diff]
verilog/rtl/glbl/src/run_verilator[Added - diff]
verilog/rtl/mbist/run_iverilog[Added - diff]
verilog/rtl/mbist/run_verilator[Added - diff]
verilog/rtl/mbist/src/core/mbist_addr_gen.sv[Renamed from verilog/rtl/mbist/src/mbist_addr_gen.sv - diff]
verilog/rtl/mbist/src/core/mbist_data_cmp.sv[Renamed from verilog/rtl/mbist/src/mbist_data_cmp.sv - diff]
verilog/rtl/mbist/src/core/mbist_fsm.sv[Renamed from verilog/rtl/mbist/src/mbist_fsm.sv - diff]
verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_mux.sv[Renamed from verilog/rtl/mbist/src/mbist_mux.sv - diff]
verilog/rtl/mbist/src/core/mbist_op_sel.sv[Renamed from verilog/rtl/mbist/src/mbist_op_sel.sv - diff]
verilog/rtl/mbist/src/core/mbist_pat_sel.sv[Renamed from verilog/rtl/mbist/src/mbist_pat_sel.sv - diff]
verilog/rtl/mbist/src/core/mbist_repair_addr.sv[Renamed from verilog/rtl/mbist/src/mbist_repair_addr.sv - diff]
verilog/rtl/mbist/src/core/mbist_sti_sel.sv[Renamed from verilog/rtl/mbist/src/mbist_sti_sel.sv - diff]
verilog/rtl/mbist/src/top/mbist_top1.sv[Renamed from verilog/rtl/mbist/src/mbist_top.sv - diff]
verilog/rtl/mbist/src/top/mbist_top2.sv[Copied from verilog/rtl/mbist/src/mbist_top.sv - diff]
verilog/rtl/sram_macros/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/wb_host/src/run_iverilog[Added - diff]
verilog/rtl/wb_host/src/run_verilator[Added - diff]
verilog/rtl/wb_host/src/wb_host.sv[diff]
verilog/rtl/wb_interconnect/src/run_iverilog[Added - diff]
verilog/rtl/wb_interconnect/src/run_verilator[Added - diff]
verilog/rtl/wb_interconnect/src/wb_interconnect.sv[Added - diff]

131 files changed

tree: f306da5cd1908a4e5171ca0482c28567707d8117

README.md

  MBIST Controller


Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.

Overview
MBIST Controller Block Diagram
Key Feature
Prerequisites
Tests preparation
- Running Simuation
Tool sets
Documentation

Overview

MBIST is a self-testing and repair mechanism which tests the memories through an effective set of algorithms to detect possibly all the faults that could be present inside a typical memory cell whether it is stuck-at (SAF), transition delay faults (TDF), coupling (CF) or neighborhood pattern sensitive faults (NPSF). This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.

MBIST Block Diagram

Key features

    * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
    * Mbist controller with memory repair supported
    * Currently only Row Redudency is supported
    * 4 Address location memory repair reported
    * 2KB SRAM
    * Wishbone compatible design
    * Written in System Verilog
    * Open-source tool set
       * simulation - iverilog
       * synthesis  - yosys
       * backend/sta - openlane tool set
    * Verification suite provided.

Prerequisites

Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice.

Step-1: Docker in ubuntu 20.04 version

   sudo apt update
   sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common
   curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo apt-key add -
   sudo add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu focal stable"
   sudo apt update
   apt-cache policy docker-ce
   sudo apt install docker-ce

   #Add User Name to docker
   sudo usermod -aG docker <your user name>
   # Reboot the system to enable the docker setup

Step-2: Update the Submodule, To to project area

   git submodule init
   git submodule update

Step-3: clone Openlane scripts under workarea

   git clone https://github.com/The-OpenROAD-Project/OpenLane.git

Step-4: add Environment setting

    export CARAVEL_ROOT=<Carvel Installed Path>
    export OPENLANE_ROOT=<OpenLane Installed Path>
    export OPENLANE_IMAGE_NAME=efabless/openlane:latest
    export PDK_ROOT=<PDK Installed PATH>
    export PDK_PATH=<PDK Install Path>/sky130A

Step-5: To install the PDK

   source ~/.bashrc
   cd OpenLane
   make pdk

Tests preparation

The simulation package includes the following tests:

wb_port - User Wishbone validation
user_mbist_test1 - Standalone Mbist Controller Specific Test for Non Error/Single/Two/Three/Four/Five Location Error

Running Simulation

Examples:

    make verify-wb_port  
    make verify-user_mbist_test1
    make verify-wb_port SIM=RTL DUMP=OFF
    make verify-wb_port SIM=RTL DUMP=ON
    make verify-user_mbist_test1 SIM=RTL DUMP=OFF
    make verify-user_mbist_test1 SIM=RTL DUMP=ON

Tool Sets

Mbist Controller flow uses Openlane tool sets.

Synthesis
1. yosys - Performs RTL synthesis
2. abc - Performs technology mapping
3. OpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
Floorplan and PDN
1. init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
2. ioplacer - Places the macro input and output ports
3. pdn - Generates the power distribution network
4. tapcell - Inserts welltap and decap cells in the floorplan
Placement
1. RePLace - Performs global placement
2. Resizer - Performs optional optimizations on the design
3. OpenPhySyn - Performs timing optimizations on the design
4. OpenDP - Perfroms detailed placement to legalize the globally placed components
CTS
1. TritonCTS - Synthesizes the clock distribution network (the clock tree)
Routing
1. FastRoute - Performs global routing to generate a guide file for the detailed router
2. CU-GR - Another option for performing global routing.
3. TritonRoute - Performs detailed routing
4. SPEF-Extractor - Performs SPEF extraction
GDSII Generation
1. Magic - Streams out the final GDSII layout file from the routed def
2. Klayout - Streams out the final GDSII layout file from the routed def as a back-up
Checks
1. Magic - Performs DRC Checks & Antenna Checks
2. Klayout - Performs DRC Checks
3. Netgen - Performs LVS Checks
4. CVC - Performs Circuit Validity Checks

Contacts

Report an issue: https://github.com/dineshannayya/mbist_ctrl/issues

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