Magic DRC violation fix around SRAM
diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz
index 28c6861..4e3b708 100644
--- a/def/user_project_wrapper.def.gz
+++ b/def/user_project_wrapper.def.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index dde406c..a63d179 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 63f7a11..02a9852 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index e14b7eb..c9cf907 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ
diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz
index cd6d42b..df5a7c1 100644
--- a/maglef/user_project_wrapper.mag.gz
+++ b/maglef/user_project_wrapper.mag.gz
Binary files differ
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 8234283..7948440 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -110,12 +110,12 @@
met1 2000.00 1400.00 2683.10 1816.54, \
met2 2000.00 1400.00 2683.10 1816.54, \
met3 2000.00 1400.00 2683.10 1816.54, \
- met1 2000.00 2000.00 2683.10 2316.54, \
- met2 2000.00 2000.00 2683.10 2316.54, \
- met3 2000.00 2000.00 2683.10 2316.54, \
- met1 2000.00 2600.00 2683.10 3000.54, \
- met2 2000.00 2600.00 2683.10 3000.54, \
- met3 2000.00 2600.00 2683.10 3000.54, \
+ met1 2000.00 2000.00 2683.10 2416.54, \
+ met2 2000.00 2000.00 2683.10 2416.54, \
+ met3 2000.00 2000.00 2683.10 2416.54, \
+ met1 2000.00 2600.00 2683.10 3016.54, \
+ met2 2000.00 2600.00 2683.10 3016.54, \
+ met3 2000.00 2600.00 2683.10 3016.54, \
met1 200.00 1200.00 679.78 1597.5, \
met2 200.00 1200.00 679.78 1597.5, \
met3 200.00 1200.00 679.78 1597.5, \
diff --git a/openlane/user_project_wrapper/sta.tcl b/openlane/user_project_wrapper/sta.tcl
index cb6aebb..e002811 100644
--- a/openlane/user_project_wrapper/sta.tcl
+++ b/openlane/user_project_wrapper/sta.tcl
@@ -49,8 +49,12 @@
read_spef -path u_mbist1 ../../spef/mbist_top1.spef
read_spef -path u_mbist2 ../../spef/mbist_top1.spef
-read_spef -path u_mbist3 ../../spef/mbist_top2.spef
-read_spef -path u_mbist4 ../../spef/mbist_top2.spef
+read_spef -path u_mbist3 ../../spef/mbist_top1.spef
+read_spef -path u_mbist4 ../../spef/mbist_top1.spef
+read_spef -path u_mbist5 ../../spef/mbist_top2.spef
+read_spef -path u_mbist6 ../../spef/mbist_top2.spef
+read_spef -path u_mbist7 ../../spef/mbist_top2.spef
+read_spef -path u_mbist8 ../../spef/mbist_top2.spef
read_spef -path u_wb_host ../../spef/wb_host.spef
read_spef -path u_intercon ../../spef/wb_interconnect.spef
read_spef -path u_glbl ../../spef/glbl_cfg.spef
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index aafc833..ba571d7 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h49m38s,-1,3.697073474470735,10.2784,1.8485367372353676,-1,526.16,19,0,0,0,0,0,0,-1,0,0,-1,-1,1471079,11805,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.05,3.54,3.98,0.16,0.07,-1,232,2436,232,2436,0,0,0,19,0,0,0,0,0,0,0,4,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h46m19s,-1,3.697073474470735,10.2784,1.8485367372353676,-1,525.3,19,0,0,0,0,0,0,-1,0,0,-1,-1,1471131,11807,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.05,3.54,3.98,0.16,0.07,-1,232,2436,232,2436,0,0,0,19,0,0,0,0,0,0,0,4,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index 64d0202..b2baa53 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ
