| ############################################################################### |
| # Created by write_sdc |
| # Sat Nov 13 06:33:41 2021 |
| ############################################################################### |
| current_design glbl_cfg |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name mclk -period 10.0000 [get_ports {mclk}] |
| set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}] -setup 0.2000 |
| |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reset_n}] |
| set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {sdr_init_done}] |
| |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reset_n}] |
| set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {sdr_init_done}] |
| |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_en}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[10]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[11]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[12]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[3]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[4]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[5]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[6]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[7]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[8]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[9]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[10]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[11]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[3]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[4]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[5]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[6]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[7]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[8]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[9]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[3]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[3]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[3]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[3]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[3]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[10]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[11]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[12]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[13]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[14]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[15]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[16]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[17]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[18]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[19]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[20]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[21]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[22]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[23]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[24]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[25]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[26]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[27]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[28]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[29]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[30]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[31]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[3]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[4]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[5]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[6]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[7]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[8]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[9]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[10]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[11]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[12]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[13]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[14]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[15]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[3]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[4]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[5]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[6]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[7]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[8]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[9]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[10]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[11]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[12]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[13]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[14]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[15]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[16]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[17]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[18]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[19]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[20]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[21]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[22]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[23]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[24]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[25]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[26]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[27]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[28]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[29]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[2]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[30]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[31]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[3]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[4]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[5]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[6]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[7]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[8]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[9]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {soft_irq}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[0]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[1]}] |
| set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[2]}] |
| |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_en}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {soft_irq}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[2]}] |
| |
| # Set max delay for clock skew |
| set_max_delay 3.5 -from [get_ports {wbd_clk_int}] |
| set_max_delay 2.5 -from wbd_clk_int -to wbd_clk_glbl |
| |
| set_case_analysis 0 [get_ports {cfg_cska_glbl[0]}] |
| set_case_analysis 0 [get_ports {cfg_cska_glbl[1]}] |
| set_case_analysis 0 [get_ports {cfg_cska_glbl[2]}] |
| set_case_analysis 0 [get_ports {cfg_cska_glbl[3]}] |
| |
| |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_en}] |
| set_load -pin_load 0.0334 [get_ports {reg_ack}] |
| set_load -pin_load 0.0334 [get_ports {soft_irq}] |
| set_load -pin_load 0.0334 [get_ports {wbd_clk_glbl}] |
| set_load -pin_load 0.0334 [get_ports {cfg_colbits[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_colbits[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_req_depth[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_req_depth[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_cas[2]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_cas[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_cas[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[12]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[11]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[10]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[9]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[8]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[7]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[6]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[5]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[4]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[3]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[2]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfmax[2]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfmax[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfmax[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[11]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[10]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[9]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[8]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[7]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[6]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[5]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[4]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[3]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[2]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[3]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[2]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[3]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[2]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[3]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[2]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[3]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[2]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[3]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[2]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[0]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_width[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_sdr_width[0]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[31]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[30]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[29]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[28]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[27]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[26]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[25]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[24]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[23]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[22]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[21]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[20]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[19]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[18]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[17]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[16]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[15]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[14]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[13]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[12]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[11]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[10]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[9]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[8]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[7]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[6]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[5]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[4]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[3]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[2]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[1]}] |
| set_load -pin_load 0.0334 [get_ports {fuse_mhartid[0]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[15]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[14]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[13]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[12]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[11]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[10]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[9]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[8]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[7]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[6]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[5]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[4]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[3]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[2]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[1]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[0]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[2]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[1]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reset_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sdr_init_done}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}] |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
