| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,flow_completed,0h6m4s,0h3m18s,1503.7037037037037,0.54,751.8518518518518,0.44,663.52,406,0,0,0,0,0,0,0,0,0,0,-1,13895,2345,0.0,0.0,0.0,-0.18,-1.03,0.0,0.0,0.0,-0.61,-5.43,7959291.0,0.08,0.52,0.32,0.18,0.01,-1,318,1183,67,932,0,0,0,267,0,0,0,0,0,0,0,4,16,19,14,424,7276,0,7700,90.66183136899366,11.03,10,AREA 0,5,50,1,153.6,153.18,0.55,0.0,sky130_fd_sc_hd,4,4 |
