| commit | 8e42005c4e6b60f5b8a2a433154b35c9c8116f95 | [log] [tgz] |
|---|---|---|
| author | BYCakar <51989341+BYCakar@users.noreply.github.com> | Tue Oct 19 14:07:34 2021 +0200 |
| committer | GitHub <noreply@github.com> | Tue Oct 19 14:07:34 2021 +0200 |
| tree | ebf283ab83d83e6a356bce104281bc98e19f0524 | |
| parent | 056a4c72cf3ff3340c00955c51d970c6b440a0c6 [diff] |
Update README.md
| :exclamation: Important Note |
|---|
Used RTL files from the repository: https://github.com/alexforencich/verilog-ethernet
Refer to README for this sample project documentation.