commit	056a4c72cf3ff3340c00955c51d970c6b440a0c6	[log] [tgz]
author	BYCakar <51989341+BYCakar@users.noreply.github.com>	Tue Oct 19 13:55:26 2021 +0200
committer	GitHub <noreply@github.com>	Tue Oct 19 13:55:26 2021 +0200
tree	b042ae84fd6458640e1fe58acd83535b4e1b806f
parent	9d4892197408ae6e4fa411c630ab5afaf90293de [diff]

Add files via upload

verilog/rtl/arbiter.v[Added - diff]
verilog/rtl/arp.v[Added - diff]
verilog/rtl/arp_cache.v[Added - diff]
verilog/rtl/arp_eth_rx.v[Added - diff]
verilog/rtl/arp_eth_tx.v[Added - diff]
verilog/rtl/axis_async_fifo.v[Added - diff]
verilog/rtl/axis_async_fifo_adapter.v[Added - diff]
verilog/rtl/axis_gmii_rx.v[Added - diff]
verilog/rtl/axis_gmii_tx.v[Added - diff]
verilog/rtl/eth_arb_mux.v[Added - diff]
verilog/rtl/eth_axis_rx.v[Added - diff]
verilog/rtl/eth_axis_tx.v[Added - diff]
verilog/rtl/eth_mac_1g.v[Added - diff]
verilog/rtl/eth_mac_mii.v[Added - diff]
verilog/rtl/eth_mac_mii_fifo.v[Added - diff]
verilog/rtl/fpga_core.v[Added - diff]
verilog/rtl/ip.v[Added - diff]
verilog/rtl/ip_arb_mux.v[Added - diff]
verilog/rtl/ip_complete.v[Added - diff]
verilog/rtl/ip_eth_rx.v[Added - diff]
verilog/rtl/ip_eth_tx.v[Added - diff]
verilog/rtl/lfsr.v[Added - diff]
verilog/rtl/mii_phy_if.v[Added - diff]
verilog/rtl/priority_encoder.v[Added - diff]
verilog/rtl/ssio_sdr_in.v[Added - diff]
verilog/rtl/udp.v[Added - diff]
verilog/rtl/udp_complete.v[Added - diff]
verilog/rtl/udp_ip_rx.v[Added - diff]
verilog/rtl/udp_ip_tx.v[Added - diff]

29 files changed

tree: b042ae84fd6458640e1fe58acd83535b4e1b806f

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.