Fix configs for openlane mpw-3 compatibility.
Everything hardens properly, still need to do GL sim
diff --git a/envsetup b/envsetup
index 077ea1d..f9abd01 100644
--- a/envsetup
+++ b/envsetup
@@ -7,3 +7,7 @@
# For sim.
export GCC_PATH=/opt/riscv32imc/bin/
export PDK_PATH=/home/harrison/workspace/sky130/sky130A/
+
+# Hack for mpw-3
+export OPENLANE_TAG=master
+
diff --git a/openlane/collapsering_macro/config.tcl b/openlane/collapsering_macro/config.tcl
index 76760b1..21447f0 100755
--- a/openlane/collapsering_macro/config.tcl
+++ b/openlane/collapsering_macro/config.tcl
@@ -40,8 +40,8 @@
# Remaining "clock" signals in this design have manually instantiated clock
# buffers and no timing relationships so it doesn't really matter.
# TODO(hdpham): Add additional constraints for remaining clock nets.
-set ::env(CLOCK_PORT) "dummy_not_used"
-set ::env(CLOCK_NET) "ring.clk_ff0"
+set ::env(CLOCK_PORT) "clk_out"
+# set ::env(CLOCK_NET) "ring.clk_ff0"
set ::env(CLOCK_PERIOD) "10"
set ::env(FP_SIZING) absolute
@@ -50,7 +50,7 @@
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-set ::env(PL_BASIC_PLACEMENT) 1
+# set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.75
# Maximum layer used for routing is metal 4.
diff --git a/openlane/digitalcore_macro/config.tcl b/openlane/digitalcore_macro/config.tcl
index 984323c..c41f505 100755
--- a/openlane/digitalcore_macro/config.tcl
+++ b/openlane/digitalcore_macro/config.tcl
@@ -34,12 +34,16 @@
set ::env(CLOCK_PORT) "wb_clk_i ring0_clk ring1_clk"
set ::env(CLOCK_PERIOD) "15"
+# Try to minimize fanout to fix slew violations.
+# set ::env(SYNTH_MAX_FANOUT) 4
+# set ::env(CLOCK_BUFFER_FANOUT) 14
+
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 500 500"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-set ::env(PL_TIME_DRIVEN) 1
+# set ::env(PL_TIME_DRIVEN) 1
set ::env(PL_TARGET_DENSITY) 0.4
# Maximum layer used for routing is metal 4.
diff --git a/openlane/ringosc_macro/config.tcl b/openlane/ringosc_macro/config.tcl
index 60d4a8f..7175337 100755
--- a/openlane/ringosc_macro/config.tcl
+++ b/openlane/ringosc_macro/config.tcl
@@ -47,7 +47,7 @@
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-set ::env(PL_BASIC_PLACEMENT) 1
+# set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.75
# Maximum layer used for routing is metal 4.
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 7cef48f..070ccac 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -51,19 +51,16 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v \
$script_dir/../../ip/randsack/rtl/digitalcore_macro.v \
$script_dir/../../ip/randsack/rtl/collapsering_macro.v \
$script_dir/../../ip/randsack/rtl/ringosc_macro.v"
set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/user_proj_example.lef \
$script_dir/../../lef/digitalcore_macro.lef \
$script_dir/../../lef/collapsering_macro.lef \
$script_dir/../../lef/ringosc_macro.lef"
set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/user_proj_example.gds \
$script_dir/../../gds/digitalcore_macro.gds \
$script_dir/../../gds/collapsering_macro.gds \
$script_dir/../../gds/ringosc_macro.gds"
@@ -73,6 +70,9 @@
# Don't use high resistance li1 for long routes.
set ::env(GLB_RT_OBS) "li1 0 0 2920 3520"
+set ::env(GLB_RT_ALLOW_CONGESTION) 1
+set ::env(GLB_RT_ADJUSTMENT) 0.70
+
# disable pdn check nodes becuase it hangs with multiple power domains.
# any issue with pdn connections will be flagged with LVS so it is not a critical check.
set ::env(FP_PDN_CHECK_NODES) 0
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index bde06b6..47b53a4 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -88,6 +88,11 @@
wire [27:0] ring0_trim_b;
wire [2:0] ring0_clkmux;
+ wire ring1_clk;
+ wire ring1_start;
+ wire [25:0] ring1_trim_a;
+ wire [2:0] ring1_clkmux;
+
digitalcore_macro digitalcore (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
@@ -125,10 +130,16 @@
.ring0_start(ring0_start),
.ring0_trim_a(ring0_trim_a),
.ring0_trim_b(ring0_trim_b),
- .ring0_clkmux(ring0_clkmux)
+ .ring0_clkmux(ring0_clkmux),
+
+ // ring1 ringosc macro
+ .ring1_clk(ring1_clk),
+ .ring1_start(ring1_start),
+ .ring1_trim_a(ring1_trim_a),
+ .ring1_clkmux(ring1_clkmux)
);
-collapsering_macro collapsering0 (
+collapsering_macro ring0 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
@@ -141,6 +152,18 @@
.clkmux(ring0_clkmux)
);
+ringosc_macro ring1 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+
+ .clk_out(ring1_clk),
+ .start(ring1_start),
+ .trim_a(ring1_trim_a),
+ .clkmux(ring1_clkmux)
+);
+
endmodule // user_project_wrapper
`default_nettype wire
