Wrapper now hardens and DRC/LVS clean.

Still need to double check timing and add remaining IP blocks.

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index c94b7a0..80814ac 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -51,16 +51,25 @@
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+	$script_dir/../../verilog/rtl/user_proj_example.v \
+	$script_dir/../../ip/randsack/rtl/digitalcore_macro.v \
+	$script_dir/../../ip/randsack/rtl/collapsering_macro.v"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/user_proj_example.lef"
+	$script_dir/../../lef/user_proj_example.lef \
+	$script_dir/../../lef/digitalcore_macro.lef \
+	$script_dir/../../lef/collapsering_macro.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/user_proj_example.gds"
+	$script_dir/../../gds/user_proj_example.gds \
+	$script_dir/../../gds/digitalcore_macro.gds \
+	$script_dir/../../gds/collapsering_macro.gds"
 
 set ::env(GLB_RT_MAXLAYER) 5
 
+# Don't use high resistance li1 for long routes.
+set ::env(GLB_RT_OBS)  "li1 0 0 2920 3520"
+
 # disable pdn check nodes becuase it hangs with multiple power domains.
 # any issue with pdn connections will be flagged with LVS so it is not a critical check.
 set ::env(FP_PDN_CHECK_NODES) 0
@@ -80,3 +89,5 @@
 set ::env(FILL_INSERTION) 0
 set ::env(TAP_DECAP_INSERTION) 0
 set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(ROUTING_CORES) 10

openlane/user_project_wrapper/macro.cfg

diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..732f5ab 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,2 @@
-mprj 1175 1690 N
+digitalcore 1000 500 N
+collapsering0 700 620 N

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 646c96d..bde06b6 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -88,7 +88,7 @@
   wire [27:0] ring0_trim_b;
   wire [2:0] ring0_clkmux;
 
-digitalcore_macro mprj (
+digitalcore_macro digitalcore (
 `ifdef USE_POWER_PINS
   .vccd1(vccd1),  // User area 1 1.8V power
   .vssd1(vssd1),  // User area 1 digital ground
@@ -129,6 +129,11 @@
 );
 
 collapsering_macro collapsering0 (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),  // User area 1 1.8V power
+  .vssd1(vssd1),  // User area 1 digital ground
+`endif
+
   .clk_out(ring0_clk),
   .start(ring0_start),
   .trim_a(ring0_trim_a),