Add ring0 test out

ip/randsack/rtl/digitalcore_macro.v

diff --git a/ip/randsack/rtl/digitalcore_macro.v b/ip/randsack/rtl/digitalcore_macro.v
index 16e2be4..4f134bc 100644
--- a/ip/randsack/rtl/digitalcore_macro.v
+++ b/ip/randsack/rtl/digitalcore_macro.v
@@ -299,9 +299,24 @@
   assign uart_rx = io_in[35];
 
   assign io_out[5:0] = 6'b0;
-  assign io_out[37:6] = gpio_out | {uart_tx & uart_enabled, 4'b0, ring0_test_out, 26'b0};
+  assign io_out[37:6] = gpio_out |
+    {
+      /*io37=*/uart_tx & uart_enabled,
+      4'b0,
+      /*io32=*/ring0_test_out,
+      /*io31=*/ring1_test_out,
+      25'b0
+    };
+
   assign io_oeb[5:0] = 6'b0;
-  assign io_oeb[37:6] = gpio_oeb & {~uart_enabled, {4{1'b1}}, ~ring0_test_en, {26{1'b1}}};
+  assign io_oeb[37:6] = gpio_oeb &
+    {
+      /*io37=*/~uart_enabled,
+      {4{1'b1}},
+      /*io32=*/~ring0_test_en,
+      /*io31=*/~ring1_test_en,
+      {25{1'b1}}
+    };
 
   assign la_data_out = 128'b0;
 

verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c

diff --git a/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c b/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c
index ff29a94..ace6adf 100644
--- a/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c
+++ b/verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c
@@ -25,6 +25,7 @@
 #define RANDSACK_PWM0_BASE  0x30810000
 #define RANDSACK_UART0_BASE 0x30820000
 #define RANDSACK_RING0_BASE 0x30830000
+#define RANDSACK_RING1_BASE 0x30840000
 
 #define RANDSACK_GPIO_DATA  0x00
 #define RANDSACK_GPIO_ENA   0x04
@@ -35,10 +36,12 @@
 #define RANDSACK_RING_CONTROL_ADDR  0x04
 #define RANDSACK_RING_TRIMA_ADDR    0x08
 #define RANDSACK_RING_TRIMB_ADDR    0x0c
-#define RANDSACK_RING_CLKMUX_OFFSET 8
 
-#define RANDSACK_RING_CONTROL_RESET_MASK (1 << 0)
-#define RANDSACK_RING_CONTROL_START_MASK (1 << 1)
+#define RANDSACK_RING_CONTROL_CLKMUX_OFFSET 8
+
+#define RANDSACK_RING_CONTROL_RESET_MASK    (1 << 0)
+#define RANDSACK_RING_CONTROL_START_MASK    (1 << 1)
+#define RANDSACK_RING_CONTROL_TEST_EN_MASK  (1 << 2)
 
 int i = 0;
 int clk = 0;
@@ -70,6 +73,22 @@
   reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
   reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
   reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+  reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
 
   /* Apply configuration */
   reg_mprj_xfer = 1;
@@ -77,28 +96,32 @@
     ;
 
   // Enable GPIOs and write pattern.
-  REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_ENA) = 0xffff0000;
-  REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_DATA) = 0x55550000;
+  REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_ENA) = 0x0000ffff;
+  REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_DATA) = 0x00005555;
 
-  // Reset ring osc.
+  // Reset ring1 osc.
+  REG(RANDSACK_RING1_BASE + RANDSACK_RING_TRIMA_ADDR) = 50;
+  REG(RANDSACK_RING1_BASE + RANDSACK_RING_CONTROL_ADDR) = RANDSACK_RING_CONTROL_START_MASK + RANDSACK_RING_CONTROL_TEST_EN_MASK;
+
+  // Reset ring0 osc.
   REG(RANDSACK_RING0_BASE + RANDSACK_RING_TRIMA_ADDR) = 50;
   REG(RANDSACK_RING0_BASE + RANDSACK_RING_TRIMB_ADDR) = 60;
   REG(RANDSACK_RING0_BASE + RANDSACK_RING_CONTROL_ADDR) = RANDSACK_RING_CONTROL_RESET_MASK;
   REG(RANDSACK_RING0_BASE + RANDSACK_RING_CONTROL_ADDR) = 0;
 
-  // Start ring osc.
-  REG(RANDSACK_RING0_BASE + RANDSACK_RING_CONTROL_ADDR) = RANDSACK_RING_CONTROL_START_MASK + (4 << RANDSACK_RING_CLKMUX_OFFSET);
+  // Start ring0 osc.
+  REG(RANDSACK_RING0_BASE + RANDSACK_RING_CONTROL_ADDR) = RANDSACK_RING_CONTROL_START_MASK + (4 << RANDSACK_RING_CONTROL_CLKMUX_OFFSET) + RANDSACK_RING_CONTROL_TEST_EN_MASK;
 
-  REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_DATA) = 0xaaaa0000;
+  REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_DATA) = 0x0000aaaa;
 
   // Wait for valid value.
   while (REG(RANDSACK_RING0_BASE + RANDSACK_RING_COUNT_ADDR) < 114) {
-    REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_DATA) = 0xdead0000;
+    REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_DATA) = 0x0000dead;
   }
 
   // Check to make sure the counter stopped.  Our CPU is really slow so this
   // is a safe check.
   if (REG(RANDSACK_RING0_BASE + RANDSACK_RING_COUNT_ADDR) == 114) {
-    REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_DATA) = 0xfeed0000;
+    REG(RANDSACK_GPIO0_BASE + RANDSACK_GPIO_DATA) = 0x0000feed;
   }
 }

verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v

diff --git a/verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v b/verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v
index ef24cb6..ca9b157 100644
--- a/verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v
+++ b/verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v
@@ -32,7 +32,7 @@
   wire [37:0] mprj_io;
   wire [15:0] checkbits;
 
-  assign checkbits = mprj_io[37:22];
+  assign checkbits = mprj_io[21:6];
 
   // Force housekeeping SPI.
   assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;