commit | b24cde692a9371bbebcf8b32ce919932bcb01d5c | [log] [tgz] |
---|---|---|
author | Anish <anish@anishsinghani.com> | Mon Nov 08 11:49:44 2021 -0500 |
committer | Anish <anish@anishsinghani.com> | Mon Nov 08 11:49:44 2021 -0500 |
tree | 8b6efbbc8c847f41bf0bd23da8d66a8473c273be | |
parent | 83b1bbae21e2ccc3a4fe07a5876e166b047a06b8 [diff] |
Add RTL and testbenches for accelerator
This is a cryptography accelerator chip for the mpw-three tapeout. It includes an AES256 core (with some key-entropy restrictions to reduce the number of bits in the key), a SHA256 core, a VGA game demo, and some other experimental structures.
For documentation on the AES and SHA cores (including the original Chisel source code), see asinghani/crypto-accelerator