Cryptography Accelerator v2

This is a cryptography accelerator chip for the mpw-three tapeout. It includes an AES256 core (with some key-entropy restrictions to reduce the number of bits in the key), a SHA256 core, a VGA game demo, and some other experimental structures.

For documentation on the AES and SHA cores (including the original Chisel source code), see asinghani/crypto-accelerator