| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/accelerator_top,accelerator_top,accelerator_top,flow_completed,0h41m47s,-1,97807.17131227073,1.576653306,24451.792828067682,25.55,2323.64,38552,0,0,0,0,0,0,0,70,0,0,-1,2488946,435767,-33.32,-78.07,-1,0.0,-1,-63966.09,-153443.22,-1,0.0,-1,1577187323.0,0.04,40.62,33.29,6.35,0.79,-1,33540,95196,2596,63927,0,0,0,35734,0,0,0,0,0,0,0,4,8348,8493,51,910,21936,0,22846,29.41176470588235,34,33,AREA 0,5,25,1,153.6,153.18,0.29,0.0,sky130_fd_sc_hd,4,4 |
