Caravel User Project

Overview

This repo contains a sample user project that utilizes the caravel chip user space. The user project is a simple counter that showcases how to make use of caravel's user space utilities like IO pads, logic analyzer probes, and wishbone port. The repo also demonstrates the recommended strucute for the open-mpw shuttle projects.

Caravel Integration

Files Integration

Caravel files are kept seperate from the user project by having caravel as submodule. The submodule commit should point to the latest of caravel master. The following files should have a symbolic link to caravel's corresponding files:

Root Makefile: This is to make sure that you adhere to the required implementation of the compress and uncompress targets. Also, caravel's Makefile provides useful targets like running lvs, drc, and xor checks. Run make help to display the available targets.
Openlane Makefile: This provides an easier way for running openlane to harden your macros. Refer to [ Hardening the User Project Macro]. Also, the makefile retains the openlane summary reports under the signoff directory.
Pin order file for the user wrapper: The hardened user project wrapper macro must have the same pin order specified in caravel‘s repo. Failing to adhere to the same order will fail the gds integration of the macro with caravel’s backend.

To create the symbolic links run the following:

# In case caravel is submoduled under the project root, export CARAVEL_PATH=caravel
export CARAVEL_PATH=<caravel-path> 

ln -s $CARAVEL_PATH/Makefile  Makefile
ln -s $CARAVEL_PATH/openlane/Makefile openlane/Makefile
ln -s $CARAVEL_PATH/openlane/user_project_wrapper_empty/pin_order.cfg openlane/user_project_wrapper/pin_order.cfg

Verilog Integration

You need to create a wrapper around your macro that adheres to the template at user_project_wrapper. The wrapper top module must be named user_project_wrapper and must have the same input and output ports. The wrapper gives access to the user space utilities provided by caravel like IO ports, logic analyzer probes, and wishbone bus connection to the management SoC.

For this sample project, the user macro makes use of:

The IO ports are used for displaying the count register values on the IO pads.
The LA probes are used for supplying an optional reset and clock signals and for setting an initial value for the count register.
The wishbeone port is also connected to the count register allowing for reading/writing the count value through the management SoC.

Refer to user_project_wrapper for more information.

Running Full Chip Simulation

The verilog testbenches are under this verilog/dv. For more information on setting up the simulation enviroment and the available testbenches for this sample project, refer to [README] (verilog/dv/README.md).

Hardening the User Project Macro using Openlane

For instructions on how to install openlane and the pdk refere to README.

There are two options for hardening the user project macro using openlane:

Hardening the user macro, then embedding it in the wrapper
Flattening the user macro with the wrapper.

For more details on this, refer to this README.

For this sample project, we went for the first option where the user macro is hardened first, then it is inserted in the user wrapper as a macro.

To reproduce hardening this project, run the following:

export OPENLANE_TAG=v0.12
cd openlane
# Runs openlane to harder user_proj_example
make user_proj_example
# Runs openlane to harder user_project_wrapper
make user_project_wrapper

Checklist for Open-MPW Submission

[x] The project repo adheres to the same directory structure in this repo.
[x] The project repo contain info.yaml at the project root.
[x] Top level macro is named user_project_wrapper.
[x] Full Chip Simulation passes for RTL and GL (gate-level)
[x] Hardened Macros are LVS and DRC clean
[x] Hardened user_project_wrapper adheres to the same pin order specified at pin_order
[x] XOR check passes with zero total difference.
[x] Openlane summary reports are retained under ./signoff/