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foss-eda-tools / third_party / shuttle / sky130 / mpw-003 / slot-003 / a5ea8a3fc039c2cb12b3899d271db194f78b80ef
commita5ea8a3fc039c2cb12b3899d271db194f78b80ef[log] [tgz]
authorembelon <78412338+embelon@users.noreply.github.com>Thu Nov 25 21:25:13 2021 +0100
committerembelon <78412338+embelon@users.noreply.github.com>Thu Nov 25 21:25:13 2021 +0100
tree4ddaebed9ad59e439da9affefc25c840e20d1bb0
parent9e314b9ee3de1b0feb510430b969385ebff7ec21 [diff]
Updated submodule wb_hyperram to newest version.
1 file changed
tree: 4ddaebed9ad59e439da9affefc25c840e20d1bb0
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. caravel
  13. wb_hyperram
  14. wb_openram_wrapper
  15. wb_ram_bus_mux
  16. .gitignore
  17. .gitmodules
  18. LICENSE
  19. Makefile
  20. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Additional memory (internal 1kB of OpenRAM and HyperRAM driver for external memory chip) connected through Wishbone to Caravel SoC for MPW submission

Memory blockSpaceAddressSize
HyperRAM ext. chipRAM0x3000_0000 - 0x307f_ffff8MB
HyperRAM ext. chipRegisters0x3080_0000 - 0x3080_ffffmax 64k registers, 16bit each
HyperRAM driverCSRs0x3081_0000 - 0x3081_ffffmax 64kB, 16k CSRs
OpenRAMRAM0x30c0_0000 - 0x30c0_ffffmax 64kB